1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so 3 * Samsung Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; 24 mmc0 = &mshc_0;
25 mmc2 = &mshc_2; 25 mmc2 = &mshc_2;
26 pinctrl0 = &pinctrl_alive; 26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 36 serial0 = &serial_0;
37 serial1 = &serial_1; 37 serial1 = &serial_1;
38 serial2 = &serial_2; 38 serial2 = &serial_2;
39 serial3 = &serial_3; 39 serial3 = &serial_3;
40 spi0 = &spi_0; 40 spi0 = &spi_0;
41 spi1 = &spi_1; 41 spi1 = &spi_1;
42 spi2 = &spi_2; 42 spi2 = &spi_2;
43 spi3 = &spi_3; 43 spi3 = &spi_3;
44 spi4 = &spi_4; 44 spi4 = &spi_4;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91 scl-gpios = <&gpd0 0 GPIO_ACTI 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 max98504: amplifier@31 { 96 max98504: amplifier@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 99
100 DIOVDD-supply = <&ldo3 100 DIOVDD-supply = <&ldo3_reg>;
101 DVDD-supply = <&ldo3_r 101 DVDD-supply = <&ldo3_reg>;
102 PVDD-supply = <&vph_pw 102 PVDD-supply = <&vph_pwr_regulator>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { 106 vph_pwr_regulator: regulator-vph-pwr {
107 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
108 regulator-name = "VPH_PWR"; 108 regulator-name = "VPH_PWR";
109 regulator-min-microvolt = <420 109 regulator-min-microvolt = <4200000>;
110 regulator-max-microvolt = <420 110 regulator-max-microvolt = <4200000>;
111 }; 111 };
112 112
113 irda_regulator: regulator-irda { 113 irda_regulator: regulator-irda {
114 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
115 enable-active-high; 115 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 116 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 117 regulator-name = "irda_regulator";
118 }; 118 };
119 119
120 sound { 120 sound {
121 compatible = "samsung,tm2-audi 121 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 122 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 123 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 124 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 125 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 126 model = "wm5110";
127 audio-routing = /* Headphone * !! 127 samsung,audio-routing =
128 "HP", "HPOUT1L !! 128 /* Headphone */
129 "HP", "HPOUT1R !! 129 "HP", "HPOUT1L",
130 !! 130 "HP", "HPOUT1R",
131 /* Speaker */ !! 131
132 "SPK", "SPKOUT !! 132 /* Speaker */
133 "SPKOUT", "HPO !! 133 "SPK", "SPKOUT",
134 "SPKOUT", "HPO !! 134 "SPKOUT", "HPOUT2L",
135 !! 135 "SPKOUT", "HPOUT2R",
136 /* Receiver */ !! 136
137 "RCV", "HPOUT3 !! 137 /* Receiver */
138 "RCV", "HPOUT3 !! 138 "RCV", "HPOUT3L",
>> 139 "RCV", "HPOUT3R";
139 }; 140 };
140 }; 141 };
141 142
142 &adc { 143 &adc {
143 vdd-supply = <&ldo3_reg>; 144 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 145 status = "okay";
145 146
146 thermistor-ap { 147 thermistor-ap {
147 compatible = "murata,ncp03wf10 148 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 149 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 150 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 151 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 152 io-channels = <&adc 0>;
152 }; 153 };
153 154
154 thermistor-battery { 155 thermistor-battery {
155 compatible = "murata,ncp03wf10 156 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 157 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 158 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 159 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 160 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 161 #thermal-sensor-cells = <0>;
161 }; 162 };
162 163
163 thermistor-charger { 164 thermistor-charger {
164 compatible = "murata,ncp03wf10 165 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 166 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 167 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 168 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 169 io-channels = <&adc 2>;
169 }; 170 };
170 }; 171 };
171 172
172 &bus_g2d_400 { 173 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 174 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 175 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 176 exynos,saturation-ratio = <10>;
176 status = "okay"; 177 status = "okay";
177 }; 178 };
178 179
179 &bus_g2d_266 { 180 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 181 devfreq = <&bus_g2d_400>;
181 status = "okay"; 182 status = "okay";
182 }; 183 };
183 184
184 &bus_gscl { 185 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 186 devfreq = <&bus_g2d_400>;
186 status = "okay"; 187 status = "okay";
187 }; 188 };
188 189
189 &bus_hevc { 190 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 191 devfreq = <&bus_g2d_400>;
191 status = "okay"; 192 status = "okay";
192 }; 193 };
193 194
194 &bus_jpeg { 195 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 196 devfreq = <&bus_g2d_400>;
196 status = "okay"; 197 status = "okay";
197 }; 198 };
198 199
199 &bus_mfc { 200 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 201 devfreq = <&bus_g2d_400>;
201 status = "okay"; 202 status = "okay";
202 }; 203 };
203 204
204 &bus_mscl { 205 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 206 devfreq = <&bus_g2d_400>;
206 status = "okay"; 207 status = "okay";
207 }; 208 };
208 209
209 &bus_noc0 { 210 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 211 devfreq = <&bus_g2d_400>;
211 status = "okay"; 212 status = "okay";
212 }; 213 };
213 214
214 &bus_noc1 { 215 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 216 devfreq = <&bus_g2d_400>;
216 status = "okay"; 217 status = "okay";
217 }; 218 };
218 219
219 &bus_noc2 { 220 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 221 devfreq = <&bus_g2d_400>;
221 status = "okay"; 222 status = "okay";
222 }; 223 };
223 224
224 &cmu_aud { 225 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 226 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 227 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 228 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 229 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 230 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 231 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 232 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 233 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 234
234 <&cmu_aud CLK_DIV_AUD_CA5>, 235 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 236 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 237 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 238 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 239 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 240 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 241 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 242 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 243 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 244 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 245 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 246
246 assigned-clock-parents = <&cmu_top CLK 247 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 248 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 249 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 250 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 251 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 252 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 253 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 254 <&cmu_top CLK_SCLK_AUDIO0>;
254 255
255 assigned-clock-rates = <0>, <0>, <0>, 256 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 257 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 258 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 259 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 260 };
260 261
261 &cmu_fsys { 262 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 263 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 264 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 265 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 266 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 267 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 268 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 269 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 270 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 271 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 272 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 273 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 274 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 275 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 276 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 277 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 278 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 279 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 280 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 281 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 282 <66700000>, <66700000>;
282 }; 283 };
283 284
284 &cmu_gscl { 285 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 286 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 287 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 288 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 289 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 290 };
290 291
291 &cmu_mfc { 292 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 293 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 294 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 295 };
295 296
296 &cmu_mif { 297 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 298 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 299 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 300 assigned-clock-rates = <0>, <333000000>;
300 }; 301 };
301 302
302 &cmu_mscl { 303 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 304 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 305 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 306 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 307 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 308 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 309 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 310 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 311 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 312 };
312 313
313 &cmu_top { 314 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 315 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 316 assigned-clock-rates = <196608001>;
316 }; 317 };
317 318
318 &cpu0 { 319 &cpu0 {
319 cpu-supply = <&buck3_reg>; 320 cpu-supply = <&buck3_reg>;
320 }; 321 };
321 322
322 &cpu4 { 323 &cpu4 {
323 cpu-supply = <&buck2_reg>; 324 cpu-supply = <&buck2_reg>;
324 }; 325 };
325 326
326 &decon { 327 &decon {
327 status = "okay"; 328 status = "okay";
328 }; 329 };
329 330
330 &decon_tv { 331 &decon_tv {
331 status = "okay"; 332 status = "okay";
332 333
333 ports { 334 ports {
334 #address-cells = <1>; 335 #address-cells = <1>;
335 #size-cells = <0>; 336 #size-cells = <0>;
336 337
337 port@0 { 338 port@0 {
338 reg = <0>; 339 reg = <0>;
339 tv_to_hdmi: endpoint { 340 tv_to_hdmi: endpoint {
340 remote-endpoin 341 remote-endpoint = <&hdmi_to_tv>;
341 }; 342 };
342 }; 343 };
343 }; 344 };
344 }; 345 };
345 346
346 &dsi { 347 &dsi {
347 status = "okay"; 348 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 349 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 350 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 351 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 352 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 353 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 354 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 355 pinctrl-0 = <&te_irq>;
355 }; 356 };
356 357
357 &gpu { 358 &gpu {
358 mali-supply = <&buck6_reg>; 359 mali-supply = <&buck6_reg>;
359 status = "okay"; 360 status = "okay";
360 }; 361 };
361 362
362 &hdmi { 363 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 364 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 365 status = "okay";
365 vdd-supply = <&ldo6_reg>; 366 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 367 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 368 vdd_pll-supply = <&ldo6_reg>;
368 369
369 ports { 370 ports {
370 #address-cells = <1>; 371 #address-cells = <1>;
371 #size-cells = <0>; 372 #size-cells = <0>;
372 373
373 port@0 { 374 port@0 {
374 reg = <0>; 375 reg = <0>;
375 hdmi_to_tv: endpoint { 376 hdmi_to_tv: endpoint {
376 remote-endpoin 377 remote-endpoint = <&tv_to_hdmi>;
377 }; 378 };
378 }; 379 };
379 380
380 port@1 { 381 port@1 {
381 reg = <1>; 382 reg = <1>;
382 hdmi_to_mhl: endpoint 383 hdmi_to_mhl: endpoint {
383 remote-endpoin 384 remote-endpoint = <&mhl_to_hdmi>;
384 }; 385 };
385 }; 386 };
386 }; 387 };
387 }; 388 };
388 389
389 &hsi2c_0 { 390 &hsi2c_0 {
390 status = "okay"; 391 status = "okay";
391 clock-frequency = <2500000>; 392 clock-frequency = <2500000>;
392 393
393 pmic@66 { 394 pmic@66 {
394 compatible = "samsung,s2mps13- 395 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 396 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL 397 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
397 reg = <0x66>; 398 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 399 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; 400 wakeup-source;
400 401
401 s2mps13_osc: clocks { 402 s2mps13_osc: clocks {
402 compatible = "samsung, 403 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 404 #clock-cells = <1>;
404 clock-output-names = " 405 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 406 "s2mps13_bt";
406 }; 407 };
407 408
408 regulators { 409 regulators {
409 ldo1_reg: LDO1 { 410 ldo1_reg: LDO1 {
410 regulator-name 411 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 412 regulator-min-microvolt = <900000>;
412 regulator-max- 413 regulator-max-microvolt = <900000>;
413 regulator-alwa 414 regulator-always-on;
414 }; 415 };
415 416
416 ldo2_reg: LDO2 { 417 ldo2_reg: LDO2 {
417 regulator-name 418 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 419 regulator-min-microvolt = <2800000>;
419 regulator-max- 420 regulator-max-microvolt = <2800000>;
420 regulator-alwa 421 regulator-always-on;
421 regulator-stat 422 regulator-state-mem {
422 regula 423 regulator-off-in-suspend;
423 }; 424 };
424 }; 425 };
425 426
426 ldo3_reg: LDO3 { 427 ldo3_reg: LDO3 {
427 regulator-name 428 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 429 regulator-min-microvolt = <1800000>;
429 regulator-max- 430 regulator-max-microvolt = <1800000>;
430 regulator-alwa 431 regulator-always-on;
431 }; 432 };
432 433
433 ldo4_reg: LDO4 { 434 ldo4_reg: LDO4 {
434 regulator-name 435 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 436 regulator-min-microvolt = <1300000>;
436 regulator-max- 437 regulator-max-microvolt = <1300000>;
437 regulator-alwa 438 regulator-always-on;
438 regulator-stat 439 regulator-state-mem {
439 regula 440 regulator-off-in-suspend;
440 }; 441 };
441 }; 442 };
442 443
443 ldo5_reg: LDO5 { 444 ldo5_reg: LDO5 {
444 regulator-name 445 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 446 regulator-min-microvolt = <1000000>;
446 regulator-max- 447 regulator-max-microvolt = <1000000>;
447 regulator-alwa 448 regulator-always-on;
448 regulator-stat 449 regulator-state-mem {
449 regula 450 regulator-off-in-suspend;
450 }; 451 };
451 }; 452 };
452 453
453 ldo6_reg: LDO6 { 454 ldo6_reg: LDO6 {
454 regulator-name 455 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 456 regulator-min-microvolt = <1000000>;
456 regulator-max- 457 regulator-max-microvolt = <1000000>;
457 regulator-stat 458 regulator-state-mem {
458 regula 459 regulator-off-in-suspend;
459 }; 460 };
460 }; 461 };
461 462
462 ldo7_reg: LDO7 { 463 ldo7_reg: LDO7 {
463 regulator-name 464 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 465 regulator-min-microvolt = <1800000>;
465 regulator-max- 466 regulator-max-microvolt = <1800000>;
466 regulator-alwa 467 regulator-always-on;
467 regulator-stat 468 regulator-state-mem {
468 regula 469 regulator-off-in-suspend;
469 }; 470 };
470 }; 471 };
471 472
472 ldo8_reg: LDO8 { 473 ldo8_reg: LDO8 {
473 regulator-name 474 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 475 regulator-min-microvolt = <1800000>;
475 regulator-max- 476 regulator-max-microvolt = <1800000>;
476 regulator-alwa 477 regulator-always-on;
477 regulator-stat 478 regulator-state-mem {
478 regula 479 regulator-off-in-suspend;
479 }; 480 };
480 }; 481 };
481 482
482 ldo9_reg: LDO9 { 483 ldo9_reg: LDO9 {
483 regulator-name 484 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 485 regulator-min-microvolt = <1800000>;
485 regulator-max- 486 regulator-max-microvolt = <1800000>;
486 regulator-alwa 487 regulator-always-on;
487 regulator-stat 488 regulator-state-mem {
488 regula 489 regulator-off-in-suspend;
489 }; 490 };
490 }; 491 };
491 492
492 ldo10_reg: LDO10 { 493 ldo10_reg: LDO10 {
493 regulator-name 494 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 495 regulator-min-microvolt = <3000000>;
495 regulator-max- 496 regulator-max-microvolt = <3000000>;
496 regulator-stat 497 regulator-state-mem {
497 regula 498 regulator-off-in-suspend;
498 }; 499 };
499 }; 500 };
500 501
501 ldo11_reg: LDO11 { 502 ldo11_reg: LDO11 {
502 regulator-name 503 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 504 regulator-min-microvolt = <1000000>;
504 regulator-max- 505 regulator-max-microvolt = <1000000>;
505 regulator-alwa 506 regulator-always-on;
506 regulator-stat 507 regulator-state-mem {
507 regula 508 regulator-off-in-suspend;
508 }; 509 };
509 }; 510 };
510 511
511 ldo12_reg: LDO12 { 512 ldo12_reg: LDO12 {
512 regulator-name 513 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 514 regulator-min-microvolt = <800000>;
514 regulator-max- 515 regulator-max-microvolt = <1350000>;
515 regulator-alwa 516 regulator-always-on;
516 }; 517 };
517 518
518 ldo13_reg: LDO13 { 519 ldo13_reg: LDO13 {
519 regulator-name 520 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 521 regulator-min-microvolt = <950000>;
521 regulator-max- 522 regulator-max-microvolt = <950000>;
522 regulator-alwa 523 regulator-always-on;
523 regulator-stat 524 regulator-state-mem {
524 regula 525 regulator-off-in-suspend;
525 }; 526 };
526 }; 527 };
527 528
528 ldo14_reg: LDO14 { 529 ldo14_reg: LDO14 {
529 regulator-name 530 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 531 regulator-min-microvolt = <1200000>;
531 regulator-max- 532 regulator-max-microvolt = <1200000>;
532 regulator-alwa 533 regulator-always-on;
533 regulator-stat 534 regulator-state-mem {
534 regula 535 regulator-off-in-suspend;
535 }; 536 };
536 }; 537 };
537 538
538 ldo15_reg: LDO15 { 539 ldo15_reg: LDO15 {
539 regulator-name 540 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 541 regulator-min-microvolt = <1200000>;
541 regulator-max- 542 regulator-max-microvolt = <1200000>;
542 regulator-alwa 543 regulator-always-on;
543 regulator-stat 544 regulator-state-mem {
544 regula 545 regulator-off-in-suspend;
545 }; 546 };
546 }; 547 };
547 548
548 ldo16_reg: LDO16 { 549 ldo16_reg: LDO16 {
549 regulator-name 550 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 551 regulator-min-microvolt = <1400000>;
551 regulator-max- 552 regulator-max-microvolt = <3400000>;
552 regulator-alwa 553 regulator-always-on;
553 }; 554 };
554 555
555 ldo17_reg: LDO17 { 556 ldo17_reg: LDO17 {
556 regulator-name 557 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 558 regulator-min-microvolt = <2800000>;
558 regulator-max- 559 regulator-max-microvolt = <2800000>;
559 }; 560 };
560 561
561 ldo18_reg: LDO18 { 562 ldo18_reg: LDO18 {
562 regulator-name 563 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 564 regulator-min-microvolt = <1800000>;
564 regulator-max- 565 regulator-max-microvolt = <1800000>;
565 }; 566 };
566 567
567 ldo19_reg: LDO19 { 568 ldo19_reg: LDO19 {
568 regulator-name 569 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 570 regulator-min-microvolt = <1800000>;
570 regulator-max- 571 regulator-max-microvolt = <1800000>;
571 regulator-alwa 572 regulator-always-on;
572 }; 573 };
573 574
574 ldo20_reg: LDO20 { 575 ldo20_reg: LDO20 {
575 regulator-name 576 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 577 regulator-min-microvolt = <2800000>;
577 regulator-max- 578 regulator-max-microvolt = <2800000>;
578 regulator-alwa 579 regulator-always-on;
579 }; 580 };
580 581
581 ldo21_reg: LDO21 { 582 ldo21_reg: LDO21 {
582 regulator-name 583 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 584 regulator-min-microvolt = <1800000>;
584 regulator-max- 585 regulator-max-microvolt = <1800000>;
585 }; 586 };
586 587
587 ldo22_reg: LDO22 { 588 ldo22_reg: LDO22 {
588 regulator-name 589 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 590 regulator-min-microvolt = <1800000>;
590 regulator-max- 591 regulator-max-microvolt = <1800000>;
591 }; 592 };
592 593
593 ldo23_reg: LDO23 { 594 ldo23_reg: LDO23 {
594 regulator-name 595 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 596 regulator-min-microvolt = <1050000>;
596 regulator-max- 597 regulator-max-microvolt = <1050000>;
597 }; 598 };
598 599
599 ldo24_reg: LDO24 { 600 ldo24_reg: LDO24 {
600 regulator-name 601 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 602 regulator-min-microvolt = <1200000>;
602 regulator-max- 603 regulator-max-microvolt = <1200000>;
603 }; 604 };
604 605
605 ldo25_reg: LDO25 { 606 ldo25_reg: LDO25 {
606 regulator-name 607 regulator-name = "UNUSED_LDO25";
607 regulator-min- 608 regulator-min-microvolt = <2800000>;
608 regulator-max- 609 regulator-max-microvolt = <2800000>;
609 }; 610 };
610 611
611 ldo26_reg: LDO26 { 612 ldo26_reg: LDO26 {
612 regulator-name 613 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 614 regulator-min-microvolt = <2800000>;
614 regulator-max- 615 regulator-max-microvolt = <2800000>;
615 }; 616 };
616 617
617 ldo27_reg: LDO27 { 618 ldo27_reg: LDO27 {
618 regulator-name 619 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 620 regulator-min-microvolt = <3000000>;
620 regulator-max- 621 regulator-max-microvolt = <3000000>;
621 }; 622 };
622 623
623 ldo28_reg: LDO28 { 624 ldo28_reg: LDO28 {
624 regulator-name 625 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 626 regulator-min-microvolt = <1800000>;
626 regulator-max- 627 regulator-max-microvolt = <1800000>;
627 }; 628 };
628 629
629 ldo29_reg: LDO29 { 630 ldo29_reg: LDO29 {
630 regulator-name 631 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 632 regulator-min-microvolt = <3000000>;
632 regulator-max- 633 regulator-max-microvolt = <3000000>;
633 }; 634 };
634 635
635 ldo30_reg: LDO30 { 636 ldo30_reg: LDO30 {
636 regulator-name 637 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 638 regulator-min-microvolt = <3300000>;
638 regulator-max- 639 regulator-max-microvolt = <3300000>;
639 }; 640 };
640 641
641 ldo31_reg: LDO31 { 642 ldo31_reg: LDO31 {
642 /* 643 /*
643 * LDO31 diffe 644 * LDO31 differs from target to target,
644 * its definit 645 * its definition is in the .dts
645 */ 646 */
646 }; 647 };
647 648
648 ldo32_reg: LDO32 { 649 ldo32_reg: LDO32 {
649 regulator-name 650 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 651 regulator-min-microvolt = <1800000>;
651 regulator-max- 652 regulator-max-microvolt = <1800000>;
652 }; 653 };
653 654
654 ldo33_reg: LDO33 { 655 ldo33_reg: LDO33 {
655 regulator-name 656 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 657 regulator-min-microvolt = <2500000>;
657 regulator-max- 658 regulator-max-microvolt = <3300000>;
658 regulator-ramp 659 regulator-ramp-delay = <12500>;
659 }; 660 };
660 661
661 ldo34_reg: LDO34 { 662 ldo34_reg: LDO34 {
662 regulator-name 663 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 664 regulator-min-microvolt = <1000000>;
664 regulator-max- 665 regulator-max-microvolt = <2100000>;
665 }; 666 };
666 667
667 ldo35_reg: LDO35 { 668 ldo35_reg: LDO35 {
668 regulator-name 669 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 670 regulator-min-microvolt = <1800000>;
670 regulator-max- 671 regulator-max-microvolt = <2800000>;
671 }; 672 };
672 673
673 ldo36_reg: LDO36 { 674 ldo36_reg: LDO36 {
674 regulator-name 675 regulator-name = "VSIL_1.0V";
675 regulator-min- 676 regulator-min-microvolt = <1000000>;
676 regulator-max- 677 regulator-max-microvolt = <1000000>;
677 }; 678 };
678 679
679 ldo37_reg: LDO37 { 680 ldo37_reg: LDO37 {
680 regulator-name 681 regulator-name = "VF_1.8V";
681 regulator-min- 682 regulator-min-microvolt = <1800000>;
682 regulator-max- 683 regulator-max-microvolt = <1800000>;
683 }; 684 };
684 685
685 ldo38_reg: LDO38 { 686 ldo38_reg: LDO38 {
686 /* 687 /*
687 * LDO38 diffe 688 * LDO38 differs from target to target,
688 * its definit 689 * its definition is in the .dts
689 */ 690 */
690 }; 691 };
691 692
692 ldo39_reg: LDO39 { 693 ldo39_reg: LDO39 {
693 regulator-name 694 regulator-name = "V_HRM_1.8V";
694 regulator-min- 695 regulator-min-microvolt = <1800000>;
695 regulator-max- 696 regulator-max-microvolt = <1800000>;
696 }; 697 };
697 698
698 ldo40_reg: LDO40 { 699 ldo40_reg: LDO40 {
699 regulator-name 700 regulator-name = "V_HRM_3.3V";
700 regulator-min- 701 regulator-min-microvolt = <3300000>;
701 regulator-max- 702 regulator-max-microvolt = <3300000>;
702 }; 703 };
703 704
704 buck1_reg: BUCK1 { 705 buck1_reg: BUCK1 {
705 regulator-name 706 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 707 regulator-min-microvolt = <600000>;
707 regulator-max- 708 regulator-max-microvolt = <1500000>;
708 regulator-alwa 709 regulator-always-on;
709 regulator-stat 710 regulator-state-mem {
710 regula 711 regulator-off-in-suspend;
711 }; 712 };
712 }; 713 };
713 714
714 buck2_reg: BUCK2 { 715 buck2_reg: BUCK2 {
715 regulator-name 716 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 717 regulator-min-microvolt = <900000>;
717 regulator-max- 718 regulator-max-microvolt = <1300000>;
718 regulator-alwa 719 regulator-always-on;
719 regulator-stat 720 regulator-state-mem {
720 regula 721 regulator-off-in-suspend;
721 }; 722 };
722 }; 723 };
723 724
724 buck3_reg: BUCK3 { 725 buck3_reg: BUCK3 {
725 regulator-name 726 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 727 regulator-min-microvolt = <800000>;
727 regulator-max- 728 regulator-max-microvolt = <1200000>;
728 regulator-alwa 729 regulator-always-on;
729 regulator-stat 730 regulator-state-mem {
730 regula 731 regulator-off-in-suspend;
731 }; 732 };
732 }; 733 };
733 734
734 buck4_reg: BUCK4 { 735 buck4_reg: BUCK4 {
735 regulator-name 736 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 737 regulator-min-microvolt = <600000>;
737 regulator-max- 738 regulator-max-microvolt = <1500000>;
738 regulator-alwa 739 regulator-always-on;
739 regulator-stat 740 regulator-state-mem {
740 regula 741 regulator-off-in-suspend;
741 }; 742 };
742 }; 743 };
743 744
744 buck5_reg: BUCK5 { 745 buck5_reg: BUCK5 {
745 regulator-name 746 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 747 regulator-min-microvolt = <600000>;
747 regulator-max- 748 regulator-max-microvolt = <1500000>;
748 regulator-alwa 749 regulator-always-on;
749 regulator-stat 750 regulator-state-mem {
750 regula 751 regulator-off-in-suspend;
751 }; 752 };
752 }; 753 };
753 754
754 buck6_reg: BUCK6 { 755 buck6_reg: BUCK6 {
755 regulator-name 756 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 757 regulator-min-microvolt = <600000>;
757 regulator-max- 758 regulator-max-microvolt = <1500000>;
758 regulator-alwa 759 regulator-always-on;
759 regulator-stat 760 regulator-state-mem {
760 regula 761 regulator-off-in-suspend;
761 }; 762 };
762 }; 763 };
763 764
764 buck7_reg: BUCK7 { 765 buck7_reg: BUCK7 {
765 regulator-name 766 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 767 regulator-min-microvolt = <1200000>;
767 regulator-max- 768 regulator-max-microvolt = <1200000>;
768 regulator-alwa 769 regulator-always-on;
769 }; 770 };
770 771
771 buck8_reg: BUCK8 { 772 buck8_reg: BUCK8 {
772 regulator-name 773 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 774 regulator-min-microvolt = <1350000>;
774 regulator-max- 775 regulator-max-microvolt = <3300000>;
775 regulator-alwa 776 regulator-always-on;
776 }; 777 };
777 778
778 buck9_reg: BUCK9 { 779 buck9_reg: BUCK9 {
779 regulator-name 780 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 781 regulator-min-microvolt = <1350000>;
781 regulator-max- 782 regulator-max-microvolt = <3300000>;
782 regulator-alwa 783 regulator-always-on;
783 }; 784 };
784 785
785 buck10_reg: BUCK10 { 786 buck10_reg: BUCK10 {
786 regulator-name 787 regulator-name = "vdd_mem2";
787 regulator-min- 788 regulator-min-microvolt = <550000>;
788 regulator-max- 789 regulator-max-microvolt = <1500000>;
789 regulator-alwa 790 regulator-always-on;
790 }; 791 };
791 }; 792 };
792 }; 793 };
793 }; 794 };
794 795
795 &hsi2c_4 { 796 &hsi2c_4 {
796 status = "okay"; 797 status = "okay";
797 798
798 s3fwrn5: nfc@27 { 799 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 800 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 801 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 802 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ 803 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV 804 en-gpios = <&gpf1 4 GPIO_ACTIVE_LOW>;
804 wake-gpios = <&gpj0 2 GPIO_ACT 805 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 806 };
806 }; 807 };
807 808
808 &hsi2c_5 { 809 &hsi2c_5 {
809 status = "okay"; 810 status = "okay";
810 811
811 stmfts: touchscreen@49 { 812 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 813 compatible = "st,stmfts";
813 reg = <0x49>; 814 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 815 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 816 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 817 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 818 vdd-supply = <&ldo31_reg>;
818 }; 819 };
819 }; 820 };
820 821
821 &hsi2c_7 { 822 &hsi2c_7 {
822 status = "okay"; 823 status = "okay";
823 clock-frequency = <1000000>; 824 clock-frequency = <1000000>;
824 825
825 bridge@39 { 826 bridge@39 {
826 reg = <0x39>; 827 reg = <0x39>;
827 compatible = "sil,sii8620"; 828 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 829 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 830 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 831 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 832 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 833 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 834 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 835 clock-names = "xtal";
835 836
836 ports { 837 ports {
837 #address-cells = <1>; 838 #address-cells = <1>;
838 #size-cells = <0>; 839 #size-cells = <0>;
839 840
840 port@0 { 841 port@0 {
841 reg = <0>; 842 reg = <0>;
842 mhl_to_hdmi: e 843 mhl_to_hdmi: endpoint {
843 remote 844 remote-endpoint = <&hdmi_to_mhl>;
844 }; 845 };
845 }; 846 };
846 847
847 port@1 { 848 port@1 {
848 reg = <1>; 849 reg = <1>;
849 mhl_to_musb_co 850 mhl_to_musb_con: endpoint {
850 remote 851 remote-endpoint = <&musb_con_to_mhl>;
851 }; 852 };
852 }; 853 };
853 }; 854 };
854 }; 855 };
855 }; 856 };
856 857
857 &hsi2c_8 { 858 &hsi2c_8 {
858 status = "okay"; 859 status = "okay";
859 860
860 pmic@66 { 861 pmic@66 {
861 compatible = "maxim,max77843"; 862 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 863 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 864 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 865 reg = <0x66>;
865 866
866 muic: extcon { 867 muic: extcon {
867 compatible = "maxim,ma 868 compatible = "maxim,max77843-muic";
868 869
869 musb_con: connector { 870 musb_con: connector {
870 compatible = " 871 compatible = "samsung,usb-connector-11pin",
871 " 872 "usb-b-connector";
872 label = "micro 873 label = "micro-USB";
873 type = "micro" 874 type = "micro";
874 875
875 ports { 876 ports {
876 #addre 877 #address-cells = <1>;
877 #size- 878 #size-cells = <0>;
878 879
879 port@0 880 port@0 {
880 881 /*
881 882 * TODO: The DTS this is based on does not have
882 883 * port@0 which is a required property. The ports
883 884 * look incomplete and need fixing.
884 885 * Add a disabled port just to satisfy dtschema.
885 886 */
886 887 reg = <0>;
887 888 status = "disabled";
888 }; 889 };
889 890
890 port@3 891 port@3 {
891 892 reg = <3>;
892 893 musb_con_to_mhl: endpoint {
893 894 remote-endpoint = <&mhl_to_musb_con>;
894 895 };
895 }; 896 };
896 }; 897 };
897 }; 898 };
898 899
899 ports { 900 ports {
900 port { 901 port {
901 muic_t 902 muic_to_usb: endpoint {
902 903 remote-endpoint = <&usb_to_muic>;
903 }; 904 };
904 }; 905 };
905 }; 906 };
906 }; 907 };
907 908
908 regulators { 909 regulators {
909 compatible = "maxim,ma 910 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 911 safeout1_reg: SAFEOUT1 {
911 regulator-name 912 regulator-name = "SAFEOUT1";
912 regulator-min- 913 regulator-min-microvolt = <3300000>;
913 regulator-max- 914 regulator-max-microvolt = <4950000>;
914 }; 915 };
915 916
916 safeout2_reg: SAFEOUT2 917 safeout2_reg: SAFEOUT2 {
917 regulator-name 918 regulator-name = "SAFEOUT2";
918 regulator-min- 919 regulator-min-microvolt = <3300000>;
919 regulator-max- 920 regulator-max-microvolt = <4950000>;
920 }; 921 };
921 922
922 charger_reg: CHARGER { 923 charger_reg: CHARGER {
923 regulator-name 924 regulator-name = "CHARGER";
924 regulator-min- 925 regulator-min-microamp = <100000>;
925 regulator-max- 926 regulator-max-microamp = <3150000>;
926 }; 927 };
927 }; 928 };
928 929
929 haptic: motor-driver { 930 haptic: motor-driver {
930 compatible = "maxim,ma 931 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 932 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 933 pwms = <&pwm 0 33670 0>;
933 }; 934 };
934 }; 935 };
935 }; 936 };
936 937
937 &hsi2c_11 { 938 &hsi2c_11 {
938 status = "okay"; 939 status = "okay";
939 }; 940 };
940 941
941 &i2s0 { 942 &i2s0 {
942 status = "okay"; 943 status = "okay";
943 }; 944 };
944 945
945 &i2s1 { 946 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 947 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 948 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 949 status = "okay";
949 }; 950 };
950 951
951 &mshc_0 { 952 &mshc_0 {
952 status = "okay"; 953 status = "okay";
953 mmc-ddr-1_8v; 954 mmc-ddr-1_8v;
954 mmc-hs200-1_8v; 955 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 956 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 957 cap-mmc-highspeed;
957 non-removable; 958 non-removable;
958 card-detect-delay = <200>; 959 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 960 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 961 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 962 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 963 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 964 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 965 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 966 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 967 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 968 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 969 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 970 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 971 assigned-clock-rates = <800000000>;
971 }; 972 };
972 973
973 &mshc_2 { 974 &mshc_2 {
974 status = "okay"; 975 status = "okay";
975 cap-sd-highspeed; 976 cap-sd-highspeed;
976 disable-wp; 977 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 978 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 979 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 980 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 981 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 982 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 983 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 984 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 985 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 986 bus-width = <4>;
986 }; 987 };
987 988
988 &pcie { 989 &pcie {
989 status = "okay"; 990 status = "okay";
990 pinctrl-names = "default"; 991 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 992 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>; 993 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>; 994 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ 995 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
995 <&cmu_top CLK_MOUT_S 996 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK 997 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK 998 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
998 assigned-clock-rates = <0>, <100000000 999 assigned-clock-rates = <0>, <100000000>;
999 interrupt-map-mask = <0 0 0 0>; 1000 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 1001 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1001 }; 1002 };
1002 1003
1003 &pcie_phy { 1004 &pcie_phy {
1004 status = "okay"; 1005 status = "okay";
1005 }; 1006 };
1006 1007
1007 &ppmu_d0_general { 1008 &ppmu_d0_general {
1008 status = "okay"; 1009 status = "okay";
1009 events { 1010 events {
1010 ppmu_event0_d0_general: ppmu- 1011 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 1012 event-name = "ppmu-event0-d0-general";
1012 }; 1013 };
1013 }; 1014 };
1014 }; 1015 };
1015 1016
1016 &ppmu_d1_general { 1017 &ppmu_d1_general {
1017 status = "okay"; 1018 status = "okay";
1018 events { 1019 events {
1019 ppmu_event0_d1_general: ppmu- 1020 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 1021 event-name = "ppmu-event0-d1-general";
1021 }; 1022 };
1022 }; 1023 };
1023 }; 1024 };
1024 1025
1025 &pinctrl_alive { 1026 &pinctrl_alive {
1026 pinctrl-names = "default"; 1027 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 1028 pinctrl-0 = <&initial_alive>;
1028 1029
1029 initial_alive: initial-state { 1030 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 1031 PIN_IN(gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 1032 PIN_IN(gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 1033 PIN_IN(gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 1034 PIN_IN(gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 1035 PIN_IN(gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 1036 PIN_IN(gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 1037 PIN_IN(gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 1038 PIN_IN(gpa0-7, NONE, FAST_SR1);
1038 1039
1039 PIN_IN(gpa1-0, UP, FAST_SR1); 1040 PIN_IN(gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); 1041 PIN_IN(gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 1042 PIN_IN(gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 1043 PIN_IN(gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 1044 PIN_IN(gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 1045 PIN_IN(gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 1046 PIN_IN(gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 1047 PIN_IN(gpa1-7, NONE, FAST_SR1);
1047 1048
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 1049 PIN_IN(gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 1050 PIN_IN(gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 1051 PIN_IN(gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 1052 PIN_IN(gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 1053 PIN_IN(gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 1054 PIN_IN(gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 1055 PIN_IN(gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 1056 PIN_IN(gpa2-7, NONE, FAST_SR1);
1056 1057
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 1058 PIN_IN(gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 1059 PIN_IN(gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 1060 PIN_IN(gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 1061 PIN_IN(gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 1062 PIN_IN(gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 1063 PIN_IN(gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 1064 PIN_IN(gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 1065 PIN_IN(gpa3-7, DOWN, FAST_SR1);
1065 1066
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 1067 PIN_IN(gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 1068 PIN_IN(gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 1069 PIN_IN(gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); 1070 PIN_IN(gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 1071 PIN_OT(gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 1072 PIN_IN(gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 1073 PIN_IN(gpf1-7, DOWN, FAST_SR1);
1073 1074
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 1075 PIN_IN(gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 1076 PIN_IN(gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 1077 PIN_IN(gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 1078 PIN_IN(gpf2-3, DOWN, FAST_SR1);
1078 1079
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 1080 PIN_IN(gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 1081 PIN_IN(gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 1082 PIN_IN(gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 1083 PIN_IN(gpf3-3, DOWN, FAST_SR1);
1083 1084
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 1085 PIN_IN(gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 1086 PIN_IN(gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 1087 PIN_IN(gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 1088 PIN_IN(gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 1089 PIN_IN(gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 1090 PIN_IN(gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 1091 PIN_IN(gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 1092 PIN_IN(gpf4-7, DOWN, FAST_SR1);
1092 1093
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 1094 PIN_IN(gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 1095 PIN_IN(gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 1096 PIN_IN(gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 1097 PIN_IN(gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 1098 PIN_OT(gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 1099 PIN_IN(gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 1100 PIN_IN(gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 1101 PIN_IN(gpf5-7, DOWN, FAST_SR1);
1101 }; 1102 };
1102 1103
1103 te_irq: te-irq-pins { 1104 te_irq: te-irq-pins {
1104 samsung,pins = "gpf1-3"; 1105 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO !! 1106 samsung,pin-function = <0xf>;
1106 }; 1107 };
1107 }; 1108 };
1108 1109
1109 &pinctrl_cpif { 1110 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1111 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1112 pinctrl-0 = <&initial_cpif>;
1112 1113
1113 initial_cpif: initial-state { 1114 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 1115 PIN_IN(gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 1116 PIN_IN(gpv6-1, DOWN, FAST_SR1);
1116 }; 1117 };
1117 }; 1118 };
1118 1119
1119 &pinctrl_ese { 1120 &pinctrl_ese {
1120 pinctrl-names = "default"; 1121 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1122 pinctrl-0 = <&initial_ese>;
1122 1123
1123 pcie_wlanen: pcie-wlanen-pins { 1124 pcie_wlanen: pcie-wlanen-pins {
1124 samsung,pins = "gpj2-0"; 1125 samsung,pins = "gpj2-0";
1125 samsung,pin-function = <EXYNO 1126 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1126 samsung,pin-pud = <EXYNOS_PIN 1127 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1127 samsung,pin-drv = <EXYNOS5433 1128 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
1128 }; 1129 };
1129 1130
1130 initial_ese: initial-state { 1131 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 1132 PIN_IN(gpj2-1, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 1133 PIN_IN(gpj2-2, DOWN, FAST_SR1);
1133 }; 1134 };
1134 }; 1135 };
1135 1136
1136 &pinctrl_fsys { 1137 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1138 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1139 pinctrl-0 = <&initial_fsys>;
1139 1140
1140 initial_fsys: initial-state { 1141 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 1142 PIN_IN(gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 1143 PIN_IN(gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 1144 PIN_IN(gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 1145 PIN_IN(gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 1146 PIN_IN(gpr3-7, NONE, FAST_SR1);
1146 }; 1147 };
1147 }; 1148 };
1148 1149
1149 &pinctrl_imem { 1150 &pinctrl_imem {
1150 pinctrl-names = "default"; 1151 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1152 pinctrl-0 = <&initial_imem>;
1152 1153
1153 initial_imem: initial-state { 1154 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); 1155 PIN_IN(gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); 1156 PIN_IN(gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 1157 PIN_IN(gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); 1158 PIN_IN(gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 1159 PIN_IN(gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 1160 PIN_IN(gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 1161 PIN_IN(gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); 1162 PIN_IN(gpf0-7, UP, FAST_SR1);
1162 }; 1163 };
1163 }; 1164 };
1164 1165
1165 &pinctrl_nfc { 1166 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1167 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1168 pinctrl-0 = <&initial_nfc>;
1168 1169
1169 initial_nfc: initial-state { 1170 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 1171 PIN_IN(gpj0-2, DOWN, FAST_SR1);
1171 }; 1172 };
1172 }; 1173 };
1173 1174
1174 &pinctrl_peric { 1175 &pinctrl_peric {
1175 pinctrl-names = "default"; 1176 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1177 pinctrl-0 = <&initial_peric>;
1177 1178
1178 initial_peric: initial-state { 1179 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 1180 PIN_IN(gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 1181 PIN_IN(gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 1182 PIN_IN(gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 1183 PIN_IN(gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 1184 PIN_IN(gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 1185 PIN_IN(gpv7-5, DOWN, FAST_SR1);
1185 1186
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 1187 PIN_IN(gpb0-4, DOWN, FAST_SR1);
1187 1188
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 1189 PIN_IN(gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 1190 PIN_IN(gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 1191 PIN_IN(gpc0-7, DOWN, FAST_SR1);
1191 1192
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 1193 PIN_IN(gpc1-1, DOWN, FAST_SR1);
1193 1194
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 1195 PIN_IN(gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 1196 PIN_IN(gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 1197 PIN_IN(gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 1198 PIN_IN(gpc3-7, NONE, FAST_SR1);
1198 1199
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 1200 PIN_OT(gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 1201 PIN_F2(gpg0-1, DOWN, FAST_SR1);
1201 1202
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 1203 PIN_IN(gpd2-5, DOWN, FAST_SR1);
1203 1204
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 1205 PIN_IN(gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 1206 PIN_IN(gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 1207 PIN_IN(gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 1208 PIN_IN(gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 1209 PIN_IN(gpd4-4, DOWN, FAST_SR1);
1209 1210
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 1211 PIN_IN(gpd6-3, DOWN, FAST_SR1);
1211 1212
1212 PIN_IN(gpd8-1, UP, FAST_SR1); 1213 PIN_IN(gpd8-1, UP, FAST_SR1);
1213 1214
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 1215 PIN_IN(gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 1216 PIN_IN(gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 1217 PIN_IN(gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 1218 PIN_IN(gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 1219 PIN_IN(gpg1-4, DOWN, FAST_SR1);
1219 1220
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 1221 PIN_IN(gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 1222 PIN_IN(gpg2-1, DOWN, FAST_SR1);
1222 1223
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 1224 PIN_IN(gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 1225 PIN_IN(gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 1226 PIN_IN(gpg3-5, DOWN, FAST_SR1);
1226 }; 1227 };
1227 }; 1228 };
1228 1229
1229 &pinctrl_touch { 1230 &pinctrl_touch {
1230 pinctrl-names = "default"; 1231 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1232 pinctrl-0 = <&initial_touch>;
1232 1233
1233 initial_touch: initial-state { 1234 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 1235 PIN_IN(gpj1-2, DOWN, FAST_SR1);
1235 }; 1236 };
1236 }; 1237 };
1237 1238
1238 &pwm { 1239 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1240 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1241 pinctrl-names = "default";
1241 status = "okay"; 1242 status = "okay";
1242 }; 1243 };
1243 1244
1244 &mic { 1245 &mic {
1245 status = "okay"; 1246 status = "okay";
1246 }; 1247 };
1247 1248
1248 &pmu_system_controller { 1249 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1250 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1251 assigned-clock-parents = <&xxti>;
1251 }; 1252 };
1252 1253
1253 &serial_1 { 1254 &serial_1 {
1254 status = "okay"; 1255 status = "okay";
1255 }; 1256 };
1256 1257
1257 &serial_3 { 1258 &serial_3 {
1258 status = "okay"; 1259 status = "okay";
1259 1260
1260 bluetooth { 1261 bluetooth {
1261 compatible = "brcm,bcm43438-b 1262 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1263 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1264 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1265 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1266 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1267 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1268 clock-names = "extclk";
1268 }; 1269 };
1269 }; 1270 };
1270 1271
1271 &spi_1 { 1272 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1273 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1274 status = "okay";
1274 1275
1275 wm5110: audio-codec@0 { 1276 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110"; 1277 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1278 reg = <0x0>;
1278 spi-max-frequency = <20000000 1279 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1280 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1281 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1282 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1283 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1284 clock-names = "mclk1", "mclk2";
1284 1285
1285 gpio-controller; 1286 gpio-controller;
1286 #gpio-cells = <2>; 1287 #gpio-cells = <2>;
1287 interrupt-controller; 1288 interrupt-controller;
1288 #interrupt-cells = <2>; 1289 #interrupt-cells = <2>;
1289 1290
1290 wlf,micd-detect-debounce = <3 1291 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1292 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1293 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; 1294 wlf,micd-dbtime = <0x2>;
1294 wlf,micd-force-micbias; 1295 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1296 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1297 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1298 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1299 wlf,inmode = <2 0 2 0>;
1299 1300
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1301 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1302 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1303
1303 /* core supplies */ 1304 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1305 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1306 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1307 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1308 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1309 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re 1310 SPKVDDL-supply = <&vph_pwr_regulator>;
1310 SPKVDDR-supply = <&vph_pwr_re 1311 SPKVDDR-supply = <&vph_pwr_regulator>;
1311 1312
1312 controller-data { 1313 controller-data {
1313 samsung,spi-feedback- 1314 samsung,spi-feedback-delay = <0>;
1314 }; 1315 };
1315 }; 1316 };
1316 }; 1317 };
1317 1318
1318 &spi_3 { 1319 &spi_3 {
1319 status = "okay"; 1320 status = "okay";
1320 no-cs-readback; 1321 no-cs-readback;
1321 1322
1322 irled@0 { 1323 irled@0 {
1323 compatible = "ir-spi-led"; 1324 compatible = "ir-spi-led";
1324 reg = <0x0>; 1325 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1326 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1327 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; 1328 duty-cycle = /bits/ 8 <60>;
1328 led-active-low; 1329 led-active-low;
1329 1330
1330 controller-data { 1331 controller-data {
1331 samsung,spi-feedback- 1332 samsung,spi-feedback-delay = <0>;
1332 }; 1333 };
1333 }; 1334 };
1334 }; 1335 };
1335 1336
1336 &timer { 1337 &timer {
1337 clock-frequency = <24000000>; 1338 clock-frequency = <24000000>;
1338 }; 1339 };
1339 1340
1340 &tmu_atlas0 { 1341 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1342 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1343 status = "okay";
1343 }; 1344 };
1344 1345
1345 &tmu_apollo { 1346 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1347 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1348 status = "okay";
1348 }; 1349 };
1349 1350
1350 &tmu_g3d { 1351 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1352 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1353 status = "okay";
1353 }; 1354 };
1354 1355
1355 &usbdrd30 { 1356 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1357 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1358 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1359 status = "okay";
1359 }; 1360 };
1360 1361
1361 &usbdrd_dwc3 { 1362 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1363 dr_mode = "otg";
1363 }; 1364 };
1364 1365
1365 &usbdrd30_phy { 1366 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1367 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1368 status = "okay";
1368 1369
1369 port { 1370 port {
1370 usb_to_muic: endpoint { 1371 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1372 remote-endpoint = <&muic_to_usb>;
1372 }; 1373 };
1373 }; 1374 };
1374 }; 1375 };
1375 1376
1376 &xxti { 1377 &xxti {
1377 clock-frequency = <24000000>; 1378 clock-frequency = <24000000>;
1378 }; 1379 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.