1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung Exynos5433 TM2 board device tree so 3 * Samsung Exynos5433 TM2 board device tree source
4 * 4 *
5 * Copyright (c) 2016 Samsung Electronics Co., 5 * Copyright (c) 2016 Samsung Electronics Co., Ltd.
6 * 6 *
7 * Common device tree source file for Samsung' 7 * Common device tree source file for Samsung's TM2 and TM2E boards
8 * which are based on Samsung Exynos5433 SoC. 8 * which are based on Samsung Exynos5433 SoC.
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "exynos5433.dtsi" 12 #include "exynos5433.dtsi"
13 #include <dt-bindings/clock/samsung,s2mps11.h> 13 #include <dt-bindings/clock/samsung,s2mps11.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h> 15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/interrupt-controller/irq 16 #include <dt-bindings/interrupt-controller/irq.h>
17 #include <dt-bindings/sound/samsung-i2s.h> 17 #include <dt-bindings/sound/samsung-i2s.h>
18 18
19 / { 19 / {
20 aliases { 20 aliases {
21 gsc0 = &gsc_0; 21 gsc0 = &gsc_0;
22 gsc1 = &gsc_1; 22 gsc1 = &gsc_1;
23 gsc2 = &gsc_2; 23 gsc2 = &gsc_2;
24 mmc0 = &mshc_0; 24 mmc0 = &mshc_0;
25 mmc2 = &mshc_2; 25 mmc2 = &mshc_2;
26 pinctrl0 = &pinctrl_alive; 26 pinctrl0 = &pinctrl_alive;
27 pinctrl1 = &pinctrl_aud; 27 pinctrl1 = &pinctrl_aud;
28 pinctrl2 = &pinctrl_cpif; 28 pinctrl2 = &pinctrl_cpif;
29 pinctrl3 = &pinctrl_ese; 29 pinctrl3 = &pinctrl_ese;
30 pinctrl4 = &pinctrl_finger; 30 pinctrl4 = &pinctrl_finger;
31 pinctrl5 = &pinctrl_fsys; 31 pinctrl5 = &pinctrl_fsys;
32 pinctrl6 = &pinctrl_imem; 32 pinctrl6 = &pinctrl_imem;
33 pinctrl7 = &pinctrl_nfc; 33 pinctrl7 = &pinctrl_nfc;
34 pinctrl8 = &pinctrl_peric; 34 pinctrl8 = &pinctrl_peric;
35 pinctrl9 = &pinctrl_touch; 35 pinctrl9 = &pinctrl_touch;
36 serial0 = &serial_0; 36 serial0 = &serial_0;
37 serial1 = &serial_1; 37 serial1 = &serial_1;
38 serial2 = &serial_2; 38 serial2 = &serial_2;
39 serial3 = &serial_3; 39 serial3 = &serial_3;
40 spi0 = &spi_0; 40 spi0 = &spi_0;
41 spi1 = &spi_1; 41 spi1 = &spi_1;
42 spi2 = &spi_2; 42 spi2 = &spi_2;
43 spi3 = &spi_3; 43 spi3 = &spi_3;
44 spi4 = &spi_4; 44 spi4 = &spi_4;
45 }; 45 };
46 46
47 chosen { 47 chosen {
48 stdout-path = &serial_1; 48 stdout-path = &serial_1;
49 }; 49 };
50 50
51 memory@20000000 { 51 memory@20000000 {
52 device_type = "memory"; 52 device_type = "memory";
53 reg = <0x0 0x20000000 0x0 0xc0 53 reg = <0x0 0x20000000 0x0 0xc0000000>;
54 }; 54 };
55 55
56 gpio-keys { 56 gpio-keys {
57 compatible = "gpio-keys"; 57 compatible = "gpio-keys";
58 58
59 power-key { 59 power-key {
60 gpios = <&gpa2 7 GPIO_ 60 gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
61 linux,code = <KEY_POWE 61 linux,code = <KEY_POWER>;
62 label = "power key"; 62 label = "power key";
63 debounce-interval = <1 63 debounce-interval = <10>;
64 }; 64 };
65 65
66 volume-up-key { 66 volume-up-key {
67 gpios = <&gpa2 0 GPIO_ 67 gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
68 linux,code = <KEY_VOLU 68 linux,code = <KEY_VOLUMEUP>;
69 label = "volume-up key 69 label = "volume-up key";
70 debounce-interval = <1 70 debounce-interval = <10>;
71 }; 71 };
72 72
73 volume-down-key { 73 volume-down-key {
74 gpios = <&gpa2 1 GPIO_ 74 gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
75 linux,code = <KEY_VOLU 75 linux,code = <KEY_VOLUMEDOWN>;
76 label = "volume-down k 76 label = "volume-down key";
77 debounce-interval = <1 77 debounce-interval = <10>;
78 }; 78 };
79 79
80 homepage-key { 80 homepage-key {
81 gpios = <&gpa0 3 GPIO_ 81 gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
82 linux,code = <KEY_MENU 82 linux,code = <KEY_MENU>;
83 label = "homepage key" 83 label = "homepage key";
84 debounce-interval = <1 84 debounce-interval = <10>;
85 }; 85 };
86 }; 86 };
87 87
88 i2c_max98504: i2c-gpio-0 { 88 i2c_max98504: i2c-gpio-0 {
89 compatible = "i2c-gpio"; 89 compatible = "i2c-gpio";
90 sda-gpios = <&gpd0 1 GPIO_ACTI 90 sda-gpios = <&gpd0 1 GPIO_ACTIVE_HIGH>;
91 scl-gpios = <&gpd0 0 GPIO_ACTI 91 scl-gpios = <&gpd0 0 GPIO_ACTIVE_HIGH>;
92 i2c-gpio,delay-us = <2>; 92 i2c-gpio,delay-us = <2>;
93 #address-cells = <1>; 93 #address-cells = <1>;
94 #size-cells = <0>; 94 #size-cells = <0>;
95 95
96 max98504: amplifier@31 { 96 max98504: amplifier@31 {
97 compatible = "maxim,ma 97 compatible = "maxim,max98504";
98 reg = <0x31>; 98 reg = <0x31>;
99 99
100 DIOVDD-supply = <&ldo3 100 DIOVDD-supply = <&ldo3_reg>;
101 DVDD-supply = <&ldo3_r 101 DVDD-supply = <&ldo3_reg>;
102 PVDD-supply = <&vph_pw 102 PVDD-supply = <&vph_pwr_regulator>;
103 }; 103 };
104 }; 104 };
105 105
106 vph_pwr_regulator: regulator-vph-pwr { 106 vph_pwr_regulator: regulator-vph-pwr {
107 compatible = "regulator-fixed" 107 compatible = "regulator-fixed";
108 regulator-name = "VPH_PWR"; 108 regulator-name = "VPH_PWR";
109 regulator-min-microvolt = <420 109 regulator-min-microvolt = <4200000>;
110 regulator-max-microvolt = <420 110 regulator-max-microvolt = <4200000>;
111 }; 111 };
112 112
113 irda_regulator: regulator-irda { 113 irda_regulator: regulator-irda {
114 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
115 enable-active-high; 115 enable-active-high;
116 gpio = <&gpr3 3 GPIO_ACTIVE_HI 116 gpio = <&gpr3 3 GPIO_ACTIVE_HIGH>;
117 regulator-name = "irda_regulat 117 regulator-name = "irda_regulator";
118 }; 118 };
119 119
120 sound { 120 sound {
121 compatible = "samsung,tm2-audi 121 compatible = "samsung,tm2-audio";
122 audio-codec = <&wm5110>, <&hdm 122 audio-codec = <&wm5110>, <&hdmi>;
123 i2s-controller = <&i2s0 0>, <& 123 i2s-controller = <&i2s0 0>, <&i2s1 0>;
124 audio-amplifier = <&max98504>; 124 audio-amplifier = <&max98504>;
125 mic-bias-gpios = <&gpr3 2 GPIO 125 mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
126 model = "wm5110"; 126 model = "wm5110";
127 audio-routing = /* Headphone * 127 audio-routing = /* Headphone */
128 "HP", "HPOUT1L 128 "HP", "HPOUT1L",
129 "HP", "HPOUT1R 129 "HP", "HPOUT1R",
130 130
131 /* Speaker */ 131 /* Speaker */
132 "SPK", "SPKOUT 132 "SPK", "SPKOUT",
133 "SPKOUT", "HPO 133 "SPKOUT", "HPOUT2L",
134 "SPKOUT", "HPO 134 "SPKOUT", "HPOUT2R",
135 135
136 /* Receiver */ 136 /* Receiver */
137 "RCV", "HPOUT3 137 "RCV", "HPOUT3L",
138 "RCV", "HPOUT3 138 "RCV", "HPOUT3R";
139 }; 139 };
140 }; 140 };
141 141
142 &adc { 142 &adc {
143 vdd-supply = <&ldo3_reg>; 143 vdd-supply = <&ldo3_reg>;
144 status = "okay"; 144 status = "okay";
145 145
146 thermistor-ap { 146 thermistor-ap {
147 compatible = "murata,ncp03wf10 147 compatible = "murata,ncp03wf104";
148 pullup-uv = <1800000>; 148 pullup-uv = <1800000>;
149 pullup-ohm = <100000>; 149 pullup-ohm = <100000>;
150 pulldown-ohm = <0>; 150 pulldown-ohm = <0>;
151 io-channels = <&adc 0>; 151 io-channels = <&adc 0>;
152 }; 152 };
153 153
154 thermistor-battery { 154 thermistor-battery {
155 compatible = "murata,ncp03wf10 155 compatible = "murata,ncp03wf104";
156 pullup-uv = <1800000>; 156 pullup-uv = <1800000>;
157 pullup-ohm = <100000>; 157 pullup-ohm = <100000>;
158 pulldown-ohm = <0>; 158 pulldown-ohm = <0>;
159 io-channels = <&adc 1>; 159 io-channels = <&adc 1>;
160 #thermal-sensor-cells = <0>; 160 #thermal-sensor-cells = <0>;
161 }; 161 };
162 162
163 thermistor-charger { 163 thermistor-charger {
164 compatible = "murata,ncp03wf10 164 compatible = "murata,ncp03wf104";
165 pullup-uv = <1800000>; 165 pullup-uv = <1800000>;
166 pullup-ohm = <100000>; 166 pullup-ohm = <100000>;
167 pulldown-ohm = <0>; 167 pulldown-ohm = <0>;
168 io-channels = <&adc 2>; 168 io-channels = <&adc 2>;
169 }; 169 };
170 }; 170 };
171 171
172 &bus_g2d_400 { 172 &bus_g2d_400 {
173 devfreq-events = <&ppmu_event0_d0_gene 173 devfreq-events = <&ppmu_event0_d0_general>, <&ppmu_event0_d1_general>;
174 vdd-supply = <&buck4_reg>; 174 vdd-supply = <&buck4_reg>;
175 exynos,saturation-ratio = <10>; 175 exynos,saturation-ratio = <10>;
176 status = "okay"; 176 status = "okay";
177 }; 177 };
178 178
179 &bus_g2d_266 { 179 &bus_g2d_266 {
180 devfreq = <&bus_g2d_400>; 180 devfreq = <&bus_g2d_400>;
181 status = "okay"; 181 status = "okay";
182 }; 182 };
183 183
184 &bus_gscl { 184 &bus_gscl {
185 devfreq = <&bus_g2d_400>; 185 devfreq = <&bus_g2d_400>;
186 status = "okay"; 186 status = "okay";
187 }; 187 };
188 188
189 &bus_hevc { 189 &bus_hevc {
190 devfreq = <&bus_g2d_400>; 190 devfreq = <&bus_g2d_400>;
191 status = "okay"; 191 status = "okay";
192 }; 192 };
193 193
194 &bus_jpeg { 194 &bus_jpeg {
195 devfreq = <&bus_g2d_400>; 195 devfreq = <&bus_g2d_400>;
196 status = "okay"; 196 status = "okay";
197 }; 197 };
198 198
199 &bus_mfc { 199 &bus_mfc {
200 devfreq = <&bus_g2d_400>; 200 devfreq = <&bus_g2d_400>;
201 status = "okay"; 201 status = "okay";
202 }; 202 };
203 203
204 &bus_mscl { 204 &bus_mscl {
205 devfreq = <&bus_g2d_400>; 205 devfreq = <&bus_g2d_400>;
206 status = "okay"; 206 status = "okay";
207 }; 207 };
208 208
209 &bus_noc0 { 209 &bus_noc0 {
210 devfreq = <&bus_g2d_400>; 210 devfreq = <&bus_g2d_400>;
211 status = "okay"; 211 status = "okay";
212 }; 212 };
213 213
214 &bus_noc1 { 214 &bus_noc1 {
215 devfreq = <&bus_g2d_400>; 215 devfreq = <&bus_g2d_400>;
216 status = "okay"; 216 status = "okay";
217 }; 217 };
218 218
219 &bus_noc2 { 219 &bus_noc2 {
220 devfreq = <&bus_g2d_400>; 220 devfreq = <&bus_g2d_400>;
221 status = "okay"; 221 status = "okay";
222 }; 222 };
223 223
224 &cmu_aud { 224 &cmu_aud {
225 assigned-clocks = <&cmu_aud CLK_MOUT_A 225 assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2 226 <&cmu_aud CLK_MOUT_SCLK_AUD_I2S>,
227 <&cmu_aud CLK_MOUT_SCLK_AUD_PC 227 <&cmu_aud CLK_MOUT_SCLK_AUD_PCM>,
228 <&cmu_top CLK_MOUT_AUD_PLL>, 228 <&cmu_top CLK_MOUT_AUD_PLL>,
229 <&cmu_top CLK_MOUT_AUD_PLL_USE 229 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
230 <&cmu_top CLK_MOUT_SCLK_AUDIO0 230 <&cmu_top CLK_MOUT_SCLK_AUDIO0>,
231 <&cmu_top CLK_MOUT_SCLK_AUDIO1 231 <&cmu_top CLK_MOUT_SCLK_AUDIO1>,
232 <&cmu_top CLK_MOUT_SCLK_SPDIF> 232 <&cmu_top CLK_MOUT_SCLK_SPDIF>,
233 233
234 <&cmu_aud CLK_DIV_AUD_CA5>, 234 <&cmu_aud CLK_DIV_AUD_CA5>,
235 <&cmu_aud CLK_DIV_ACLK_AUD>, 235 <&cmu_aud CLK_DIV_ACLK_AUD>,
236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD 236 <&cmu_aud CLK_DIV_PCLK_DBG_AUD>,
237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S 237 <&cmu_aud CLK_DIV_SCLK_AUD_I2S>,
238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM 238 <&cmu_aud CLK_DIV_SCLK_AUD_PCM>,
239 <&cmu_aud CLK_DIV_SCLK_AUD_SLI 239 <&cmu_aud CLK_DIV_SCLK_AUD_SLIMBUS>,
240 <&cmu_aud CLK_DIV_SCLK_AUD_UAR 240 <&cmu_aud CLK_DIV_SCLK_AUD_UART>,
241 <&cmu_top CLK_DIV_SCLK_AUDIO0> 241 <&cmu_top CLK_DIV_SCLK_AUDIO0>,
242 <&cmu_top CLK_DIV_SCLK_AUDIO1> 242 <&cmu_top CLK_DIV_SCLK_AUDIO1>,
243 <&cmu_top CLK_DIV_SCLK_PCM1>, 243 <&cmu_top CLK_DIV_SCLK_PCM1>,
244 <&cmu_top CLK_DIV_SCLK_I2S1>; 244 <&cmu_top CLK_DIV_SCLK_I2S1>;
245 245
246 assigned-clock-parents = <&cmu_top CLK 246 assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>,
247 <&cmu_aud CLK_MOUT_AUD_PLL_USE 247 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
248 <&cmu_aud CLK_MOUT_AUD_PLL_USE 248 <&cmu_aud CLK_MOUT_AUD_PLL_USER>,
249 <&cmu_top CLK_FOUT_AUD_PLL>, 249 <&cmu_top CLK_FOUT_AUD_PLL>,
250 <&cmu_top CLK_MOUT_AUD_PLL>, 250 <&cmu_top CLK_MOUT_AUD_PLL>,
251 <&cmu_top CLK_MOUT_AUD_PLL_USE 251 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
252 <&cmu_top CLK_MOUT_AUD_PLL_USE 252 <&cmu_top CLK_MOUT_AUD_PLL_USER_T>,
253 <&cmu_top CLK_SCLK_AUDIO0>; 253 <&cmu_top CLK_SCLK_AUDIO0>;
254 254
255 assigned-clock-rates = <0>, <0>, <0>, 255 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
256 <196608001>, <65536001>, <3276 256 <196608001>, <65536001>, <32768001>, <49152001>,
257 <2048001>, <24576001>, <196608 257 <2048001>, <24576001>, <196608001>,
258 <24576001>, <98304001>, <20480 258 <24576001>, <98304001>, <2048001>, <49152001>;
259 }; 259 };
260 260
261 &cmu_fsys { 261 &cmu_fsys {
262 assigned-clocks = <&cmu_top CLK_MOUT_S 262 assigned-clocks = <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
263 <&cmu_top CLK_MOUT_SCLK_USBHOS 263 <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
264 <&cmu_fsys CLK_MOUT_SCLK_USBDR 264 <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
265 <&cmu_fsys CLK_MOUT_SCLK_USBHO 265 <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
266 <&cmu_fsys CLK_MOUT_PHYCLK_USB 266 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
267 <&cmu_fsys CLK_MOUT_PHYCLK_USB 267 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
268 <&cmu_fsys CLK_MOUT_PHYCLK_USB 268 <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>,
269 <&cmu_fsys CLK_MOUT_PHYCLK_USB 269 <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>,
270 <&cmu_top CLK_DIV_SCLK_USBDRD3 270 <&cmu_top CLK_DIV_SCLK_USBDRD30>,
271 <&cmu_top CLK_DIV_SCLK_USBHOST 271 <&cmu_top CLK_DIV_SCLK_USBHOST30>;
272 assigned-clock-parents = <&cmu_top CLK 272 assigned-clock-parents = <&cmu_top CLK_MOUT_BUS_PLL_USER>,
273 <&cmu_top CLK_MOUT_BUS_PLL_USE 273 <&cmu_top CLK_MOUT_BUS_PLL_USER>,
274 <&cmu_top CLK_SCLK_USBDRD30_FS 274 <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
275 <&cmu_top CLK_SCLK_USBHOST30_F 275 <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
276 <&cmu_fsys CLK_PHYCLK_USBDRD30 276 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
277 <&cmu_fsys CLK_PHYCLK_USBHOST3 277 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
278 <&cmu_fsys CLK_PHYCLK_USBDRD30 278 <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>,
279 <&cmu_fsys CLK_PHYCLK_USBHOST3 279 <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
280 assigned-clock-rates = <0>, <0>, <0>, 280 assigned-clock-rates = <0>, <0>, <0>, <0>, <0>, <0>, <0>, <0>,
281 <66700000>, <66 281 <66700000>, <66700000>;
282 }; 282 };
283 283
284 &cmu_gscl { 284 &cmu_gscl {
285 assigned-clocks = <&cmu_gscl CLK_MOUT_ 285 assigned-clocks = <&cmu_gscl CLK_MOUT_ACLK_GSCL_111_USER>,
286 <&cmu_gscl CLK_MOUT_ 286 <&cmu_gscl CLK_MOUT_ACLK_GSCL_333_USER>;
287 assigned-clock-parents = <&cmu_top CLK 287 assigned-clock-parents = <&cmu_top CLK_ACLK_GSCL_111>,
288 <&cmu_top CLK 288 <&cmu_top CLK_ACLK_GSCL_333>;
289 }; 289 };
290 290
291 &cmu_mfc { 291 &cmu_mfc {
292 assigned-clocks = <&cmu_mfc CLK_MOUT_A 292 assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
293 assigned-clock-parents = <&cmu_top CLK 293 assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
294 }; 294 };
295 295
296 &cmu_mif { 296 &cmu_mif {
297 assigned-clocks = <&cmu_mif CLK_MOUT_S 297 assigned-clocks = <&cmu_mif CLK_MOUT_SCLK_DSD_A>, <&cmu_mif CLK_DIV_SCLK_DSD>;
298 assigned-clock-parents = <&cmu_mif CLK 298 assigned-clock-parents = <&cmu_mif CLK_MOUT_MFC_PLL_DIV2>;
299 assigned-clock-rates = <0>, <333000000 299 assigned-clock-rates = <0>, <333000000>;
300 }; 300 };
301 301
302 &cmu_mscl { 302 &cmu_mscl {
303 assigned-clocks = <&cmu_mscl CLK_MOUT_ 303 assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
304 <&cmu_mscl CLK_MOUT_ 304 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
305 <&cmu_mscl CLK_MOUT_ 305 <&cmu_mscl CLK_MOUT_SCLK_JPEG>,
306 <&cmu_top CLK_MOUT_S 306 <&cmu_top CLK_MOUT_SCLK_JPEG_A>;
307 assigned-clock-parents = <&cmu_top CLK 307 assigned-clock-parents = <&cmu_top CLK_ACLK_MSCL_400>,
308 <&cmu_top CLK 308 <&cmu_top CLK_SCLK_JPEG_MSCL>,
309 <&cmu_mscl CL 309 <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
310 <&cmu_top CLK 310 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
311 }; 311 };
312 312
313 &cmu_top { 313 &cmu_top {
314 assigned-clocks = <&cmu_top CLK_FOUT_A 314 assigned-clocks = <&cmu_top CLK_FOUT_AUD_PLL>;
315 assigned-clock-rates = <196608001>; 315 assigned-clock-rates = <196608001>;
316 }; 316 };
317 317
318 &cpu0 { 318 &cpu0 {
319 cpu-supply = <&buck3_reg>; 319 cpu-supply = <&buck3_reg>;
320 }; 320 };
321 321
322 &cpu4 { 322 &cpu4 {
323 cpu-supply = <&buck2_reg>; 323 cpu-supply = <&buck2_reg>;
324 }; 324 };
325 325
326 &decon { 326 &decon {
327 status = "okay"; 327 status = "okay";
328 }; 328 };
329 329
330 &decon_tv { 330 &decon_tv {
331 status = "okay"; 331 status = "okay";
332 332
333 ports { 333 ports {
334 #address-cells = <1>; 334 #address-cells = <1>;
335 #size-cells = <0>; 335 #size-cells = <0>;
336 336
337 port@0 { 337 port@0 {
338 reg = <0>; 338 reg = <0>;
339 tv_to_hdmi: endpoint { 339 tv_to_hdmi: endpoint {
340 remote-endpoin 340 remote-endpoint = <&hdmi_to_tv>;
341 }; 341 };
342 }; 342 };
343 }; 343 };
344 }; 344 };
345 345
346 &dsi { 346 &dsi {
347 status = "okay"; 347 status = "okay";
348 vddcore-supply = <&ldo6_reg>; 348 vddcore-supply = <&ldo6_reg>;
349 vddio-supply = <&ldo7_reg>; 349 vddio-supply = <&ldo7_reg>;
350 samsung,burst-clock-frequency = <51200 350 samsung,burst-clock-frequency = <512000000>;
351 samsung,esc-clock-frequency = <1600000 351 samsung,esc-clock-frequency = <16000000>;
352 samsung,pll-clock-frequency = <2400000 352 samsung,pll-clock-frequency = <24000000>;
353 pinctrl-names = "default"; 353 pinctrl-names = "default";
354 pinctrl-0 = <&te_irq>; 354 pinctrl-0 = <&te_irq>;
355 }; 355 };
356 356
357 &gpu { 357 &gpu {
358 mali-supply = <&buck6_reg>; 358 mali-supply = <&buck6_reg>;
359 status = "okay"; 359 status = "okay";
360 }; 360 };
361 361
362 &hdmi { 362 &hdmi {
363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH> 363 hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
364 status = "okay"; 364 status = "okay";
365 vdd-supply = <&ldo6_reg>; 365 vdd-supply = <&ldo6_reg>;
366 vdd_osc-supply = <&ldo7_reg>; 366 vdd_osc-supply = <&ldo7_reg>;
367 vdd_pll-supply = <&ldo6_reg>; 367 vdd_pll-supply = <&ldo6_reg>;
368 368
369 ports { 369 ports {
370 #address-cells = <1>; 370 #address-cells = <1>;
371 #size-cells = <0>; 371 #size-cells = <0>;
372 372
373 port@0 { 373 port@0 {
374 reg = <0>; 374 reg = <0>;
375 hdmi_to_tv: endpoint { 375 hdmi_to_tv: endpoint {
376 remote-endpoin 376 remote-endpoint = <&tv_to_hdmi>;
377 }; 377 };
378 }; 378 };
379 379
380 port@1 { 380 port@1 {
381 reg = <1>; 381 reg = <1>;
382 hdmi_to_mhl: endpoint 382 hdmi_to_mhl: endpoint {
383 remote-endpoin 383 remote-endpoint = <&mhl_to_hdmi>;
384 }; 384 };
385 }; 385 };
386 }; 386 };
387 }; 387 };
388 388
389 &hsi2c_0 { 389 &hsi2c_0 {
390 status = "okay"; 390 status = "okay";
391 clock-frequency = <2500000>; 391 clock-frequency = <2500000>;
392 392
393 pmic@66 { 393 pmic@66 {
394 compatible = "samsung,s2mps13- 394 compatible = "samsung,s2mps13-pmic";
395 interrupt-parent = <&gpa0>; 395 interrupt-parent = <&gpa0>;
396 interrupts = <7 IRQ_TYPE_LEVEL 396 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
397 reg = <0x66>; 397 reg = <0x66>;
398 samsung,s2mps11-wrstbi-ground; 398 samsung,s2mps11-wrstbi-ground;
399 wakeup-source; 399 wakeup-source;
400 400
401 s2mps13_osc: clocks { 401 s2mps13_osc: clocks {
402 compatible = "samsung, 402 compatible = "samsung,s2mps13-clk";
403 #clock-cells = <1>; 403 #clock-cells = <1>;
404 clock-output-names = " 404 clock-output-names = "s2mps13_ap", "s2mps13_cp",
405 "s2mps13_bt"; 405 "s2mps13_bt";
406 }; 406 };
407 407
408 regulators { 408 regulators {
409 ldo1_reg: LDO1 { 409 ldo1_reg: LDO1 {
410 regulator-name 410 regulator-name = "VDD_ALIVE_0.9V_AP";
411 regulator-min- 411 regulator-min-microvolt = <900000>;
412 regulator-max- 412 regulator-max-microvolt = <900000>;
413 regulator-alwa 413 regulator-always-on;
414 }; 414 };
415 415
416 ldo2_reg: LDO2 { 416 ldo2_reg: LDO2 {
417 regulator-name 417 regulator-name = "VDDQ_MMC2_2.8V_AP";
418 regulator-min- 418 regulator-min-microvolt = <2800000>;
419 regulator-max- 419 regulator-max-microvolt = <2800000>;
420 regulator-alwa 420 regulator-always-on;
421 regulator-stat 421 regulator-state-mem {
422 regula 422 regulator-off-in-suspend;
423 }; 423 };
424 }; 424 };
425 425
426 ldo3_reg: LDO3 { 426 ldo3_reg: LDO3 {
427 regulator-name 427 regulator-name = "VDD1_E_1.8V_AP";
428 regulator-min- 428 regulator-min-microvolt = <1800000>;
429 regulator-max- 429 regulator-max-microvolt = <1800000>;
430 regulator-alwa 430 regulator-always-on;
431 }; 431 };
432 432
433 ldo4_reg: LDO4 { 433 ldo4_reg: LDO4 {
434 regulator-name 434 regulator-name = "VDD10_MIF_PLL_1.0V_AP";
435 regulator-min- 435 regulator-min-microvolt = <1300000>;
436 regulator-max- 436 regulator-max-microvolt = <1300000>;
437 regulator-alwa 437 regulator-always-on;
438 regulator-stat 438 regulator-state-mem {
439 regula 439 regulator-off-in-suspend;
440 }; 440 };
441 }; 441 };
442 442
443 ldo5_reg: LDO5 { 443 ldo5_reg: LDO5 {
444 regulator-name 444 regulator-name = "VDD10_DPLL_1.0V_AP";
445 regulator-min- 445 regulator-min-microvolt = <1000000>;
446 regulator-max- 446 regulator-max-microvolt = <1000000>;
447 regulator-alwa 447 regulator-always-on;
448 regulator-stat 448 regulator-state-mem {
449 regula 449 regulator-off-in-suspend;
450 }; 450 };
451 }; 451 };
452 452
453 ldo6_reg: LDO6 { 453 ldo6_reg: LDO6 {
454 regulator-name 454 regulator-name = "VDD10_MIPI2L_1.0V_AP";
455 regulator-min- 455 regulator-min-microvolt = <1000000>;
456 regulator-max- 456 regulator-max-microvolt = <1000000>;
457 regulator-stat 457 regulator-state-mem {
458 regula 458 regulator-off-in-suspend;
459 }; 459 };
460 }; 460 };
461 461
462 ldo7_reg: LDO7 { 462 ldo7_reg: LDO7 {
463 regulator-name 463 regulator-name = "VDD18_MIPI2L_1.8V_AP";
464 regulator-min- 464 regulator-min-microvolt = <1800000>;
465 regulator-max- 465 regulator-max-microvolt = <1800000>;
466 regulator-alwa 466 regulator-always-on;
467 regulator-stat 467 regulator-state-mem {
468 regula 468 regulator-off-in-suspend;
469 }; 469 };
470 }; 470 };
471 471
472 ldo8_reg: LDO8 { 472 ldo8_reg: LDO8 {
473 regulator-name 473 regulator-name = "VDD18_LLI_1.8V_AP";
474 regulator-min- 474 regulator-min-microvolt = <1800000>;
475 regulator-max- 475 regulator-max-microvolt = <1800000>;
476 regulator-alwa 476 regulator-always-on;
477 regulator-stat 477 regulator-state-mem {
478 regula 478 regulator-off-in-suspend;
479 }; 479 };
480 }; 480 };
481 481
482 ldo9_reg: LDO9 { 482 ldo9_reg: LDO9 {
483 regulator-name 483 regulator-name = "VDD18_ABB_ETC_1.8V_AP";
484 regulator-min- 484 regulator-min-microvolt = <1800000>;
485 regulator-max- 485 regulator-max-microvolt = <1800000>;
486 regulator-alwa 486 regulator-always-on;
487 regulator-stat 487 regulator-state-mem {
488 regula 488 regulator-off-in-suspend;
489 }; 489 };
490 }; 490 };
491 491
492 ldo10_reg: LDO10 { 492 ldo10_reg: LDO10 {
493 regulator-name 493 regulator-name = "VDD33_USB30_3.0V_AP";
494 regulator-min- 494 regulator-min-microvolt = <3000000>;
495 regulator-max- 495 regulator-max-microvolt = <3000000>;
496 regulator-stat 496 regulator-state-mem {
497 regula 497 regulator-off-in-suspend;
498 }; 498 };
499 }; 499 };
500 500
501 ldo11_reg: LDO11 { 501 ldo11_reg: LDO11 {
502 regulator-name 502 regulator-name = "VDD_INT_M_1.0V_AP";
503 regulator-min- 503 regulator-min-microvolt = <1000000>;
504 regulator-max- 504 regulator-max-microvolt = <1000000>;
505 regulator-alwa 505 regulator-always-on;
506 regulator-stat 506 regulator-state-mem {
507 regula 507 regulator-off-in-suspend;
508 }; 508 };
509 }; 509 };
510 510
511 ldo12_reg: LDO12 { 511 ldo12_reg: LDO12 {
512 regulator-name 512 regulator-name = "VDD_KFC_M_1.1V_AP";
513 regulator-min- 513 regulator-min-microvolt = <800000>;
514 regulator-max- 514 regulator-max-microvolt = <1350000>;
515 regulator-alwa 515 regulator-always-on;
516 }; 516 };
517 517
518 ldo13_reg: LDO13 { 518 ldo13_reg: LDO13 {
519 regulator-name 519 regulator-name = "VDD_G3D_M_0.95V_AP";
520 regulator-min- 520 regulator-min-microvolt = <950000>;
521 regulator-max- 521 regulator-max-microvolt = <950000>;
522 regulator-alwa 522 regulator-always-on;
523 regulator-stat 523 regulator-state-mem {
524 regula 524 regulator-off-in-suspend;
525 }; 525 };
526 }; 526 };
527 527
528 ldo14_reg: LDO14 { 528 ldo14_reg: LDO14 {
529 regulator-name 529 regulator-name = "VDDQ_M1_LDO_1.2V_AP";
530 regulator-min- 530 regulator-min-microvolt = <1200000>;
531 regulator-max- 531 regulator-max-microvolt = <1200000>;
532 regulator-alwa 532 regulator-always-on;
533 regulator-stat 533 regulator-state-mem {
534 regula 534 regulator-off-in-suspend;
535 }; 535 };
536 }; 536 };
537 537
538 ldo15_reg: LDO15 { 538 ldo15_reg: LDO15 {
539 regulator-name 539 regulator-name = "VDDQ_M2_LDO_1.2V_AP";
540 regulator-min- 540 regulator-min-microvolt = <1200000>;
541 regulator-max- 541 regulator-max-microvolt = <1200000>;
542 regulator-alwa 542 regulator-always-on;
543 regulator-stat 543 regulator-state-mem {
544 regula 544 regulator-off-in-suspend;
545 }; 545 };
546 }; 546 };
547 547
548 ldo16_reg: LDO16 { 548 ldo16_reg: LDO16 {
549 regulator-name 549 regulator-name = "VDDQ_EFUSE";
550 regulator-min- 550 regulator-min-microvolt = <1400000>;
551 regulator-max- 551 regulator-max-microvolt = <3400000>;
552 regulator-alwa 552 regulator-always-on;
553 }; 553 };
554 554
555 ldo17_reg: LDO17 { 555 ldo17_reg: LDO17 {
556 regulator-name 556 regulator-name = "V_TFLASH_2.8V_AP";
557 regulator-min- 557 regulator-min-microvolt = <2800000>;
558 regulator-max- 558 regulator-max-microvolt = <2800000>;
559 }; 559 };
560 560
561 ldo18_reg: LDO18 { 561 ldo18_reg: LDO18 {
562 regulator-name 562 regulator-name = "V_CODEC_1.8V_AP";
563 regulator-min- 563 regulator-min-microvolt = <1800000>;
564 regulator-max- 564 regulator-max-microvolt = <1800000>;
565 }; 565 };
566 566
567 ldo19_reg: LDO19 { 567 ldo19_reg: LDO19 {
568 regulator-name 568 regulator-name = "VDDA_1.8V_COMP";
569 regulator-min- 569 regulator-min-microvolt = <1800000>;
570 regulator-max- 570 regulator-max-microvolt = <1800000>;
571 regulator-alwa 571 regulator-always-on;
572 }; 572 };
573 573
574 ldo20_reg: LDO20 { 574 ldo20_reg: LDO20 {
575 regulator-name 575 regulator-name = "VCC_2.8V_AP";
576 regulator-min- 576 regulator-min-microvolt = <2800000>;
577 regulator-max- 577 regulator-max-microvolt = <2800000>;
578 regulator-alwa 578 regulator-always-on;
579 }; 579 };
580 580
581 ldo21_reg: LDO21 { 581 ldo21_reg: LDO21 {
582 regulator-name 582 regulator-name = "VT_CAM_1.8V";
583 regulator-min- 583 regulator-min-microvolt = <1800000>;
584 regulator-max- 584 regulator-max-microvolt = <1800000>;
585 }; 585 };
586 586
587 ldo22_reg: LDO22 { 587 ldo22_reg: LDO22 {
588 regulator-name 588 regulator-name = "CAM_IO_1.8V_AP";
589 regulator-min- 589 regulator-min-microvolt = <1800000>;
590 regulator-max- 590 regulator-max-microvolt = <1800000>;
591 }; 591 };
592 592
593 ldo23_reg: LDO23 { 593 ldo23_reg: LDO23 {
594 regulator-name 594 regulator-name = "CAM_SEN_CORE_1.05V_AP";
595 regulator-min- 595 regulator-min-microvolt = <1050000>;
596 regulator-max- 596 regulator-max-microvolt = <1050000>;
597 }; 597 };
598 598
599 ldo24_reg: LDO24 { 599 ldo24_reg: LDO24 {
600 regulator-name 600 regulator-name = "VT_CAM_1.2V";
601 regulator-min- 601 regulator-min-microvolt = <1200000>;
602 regulator-max- 602 regulator-max-microvolt = <1200000>;
603 }; 603 };
604 604
605 ldo25_reg: LDO25 { 605 ldo25_reg: LDO25 {
606 regulator-name 606 regulator-name = "UNUSED_LDO25";
607 regulator-min- 607 regulator-min-microvolt = <2800000>;
608 regulator-max- 608 regulator-max-microvolt = <2800000>;
609 }; 609 };
610 610
611 ldo26_reg: LDO26 { 611 ldo26_reg: LDO26 {
612 regulator-name 612 regulator-name = "CAM_AF_2.8V_AP";
613 regulator-min- 613 regulator-min-microvolt = <2800000>;
614 regulator-max- 614 regulator-max-microvolt = <2800000>;
615 }; 615 };
616 616
617 ldo27_reg: LDO27 { 617 ldo27_reg: LDO27 {
618 regulator-name 618 regulator-name = "VCC_3.0V_LCD_AP";
619 regulator-min- 619 regulator-min-microvolt = <3000000>;
620 regulator-max- 620 regulator-max-microvolt = <3000000>;
621 }; 621 };
622 622
623 ldo28_reg: LDO28 { 623 ldo28_reg: LDO28 {
624 regulator-name 624 regulator-name = "VCC_1.8V_LCD_AP";
625 regulator-min- 625 regulator-min-microvolt = <1800000>;
626 regulator-max- 626 regulator-max-microvolt = <1800000>;
627 }; 627 };
628 628
629 ldo29_reg: LDO29 { 629 ldo29_reg: LDO29 {
630 regulator-name 630 regulator-name = "VT_CAM_2.8V";
631 regulator-min- 631 regulator-min-microvolt = <3000000>;
632 regulator-max- 632 regulator-max-microvolt = <3000000>;
633 }; 633 };
634 634
635 ldo30_reg: LDO30 { 635 ldo30_reg: LDO30 {
636 regulator-name 636 regulator-name = "TSP_AVDD_3.3V_AP";
637 regulator-min- 637 regulator-min-microvolt = <3300000>;
638 regulator-max- 638 regulator-max-microvolt = <3300000>;
639 }; 639 };
640 640
641 ldo31_reg: LDO31 { 641 ldo31_reg: LDO31 {
642 /* 642 /*
643 * LDO31 diffe 643 * LDO31 differs from target to target,
644 * its definit 644 * its definition is in the .dts
645 */ 645 */
646 }; 646 };
647 647
648 ldo32_reg: LDO32 { 648 ldo32_reg: LDO32 {
649 regulator-name 649 regulator-name = "VTOUCH_1.8V_AP";
650 regulator-min- 650 regulator-min-microvolt = <1800000>;
651 regulator-max- 651 regulator-max-microvolt = <1800000>;
652 }; 652 };
653 653
654 ldo33_reg: LDO33 { 654 ldo33_reg: LDO33 {
655 regulator-name 655 regulator-name = "VTOUCH_LED_3.3V";
656 regulator-min- 656 regulator-min-microvolt = <2500000>;
657 regulator-max- 657 regulator-max-microvolt = <3300000>;
658 regulator-ramp 658 regulator-ramp-delay = <12500>;
659 }; 659 };
660 660
661 ldo34_reg: LDO34 { 661 ldo34_reg: LDO34 {
662 regulator-name 662 regulator-name = "VCC_1.8V_MHL_AP";
663 regulator-min- 663 regulator-min-microvolt = <1000000>;
664 regulator-max- 664 regulator-max-microvolt = <2100000>;
665 }; 665 };
666 666
667 ldo35_reg: LDO35 { 667 ldo35_reg: LDO35 {
668 regulator-name 668 regulator-name = "OIS_VM_2.8V";
669 regulator-min- 669 regulator-min-microvolt = <1800000>;
670 regulator-max- 670 regulator-max-microvolt = <2800000>;
671 }; 671 };
672 672
673 ldo36_reg: LDO36 { 673 ldo36_reg: LDO36 {
674 regulator-name 674 regulator-name = "VSIL_1.0V";
675 regulator-min- 675 regulator-min-microvolt = <1000000>;
676 regulator-max- 676 regulator-max-microvolt = <1000000>;
677 }; 677 };
678 678
679 ldo37_reg: LDO37 { 679 ldo37_reg: LDO37 {
680 regulator-name 680 regulator-name = "VF_1.8V";
681 regulator-min- 681 regulator-min-microvolt = <1800000>;
682 regulator-max- 682 regulator-max-microvolt = <1800000>;
683 }; 683 };
684 684
685 ldo38_reg: LDO38 { 685 ldo38_reg: LDO38 {
686 /* 686 /*
687 * LDO38 diffe 687 * LDO38 differs from target to target,
688 * its definit 688 * its definition is in the .dts
689 */ 689 */
690 }; 690 };
691 691
692 ldo39_reg: LDO39 { 692 ldo39_reg: LDO39 {
693 regulator-name 693 regulator-name = "V_HRM_1.8V";
694 regulator-min- 694 regulator-min-microvolt = <1800000>;
695 regulator-max- 695 regulator-max-microvolt = <1800000>;
696 }; 696 };
697 697
698 ldo40_reg: LDO40 { 698 ldo40_reg: LDO40 {
699 regulator-name 699 regulator-name = "V_HRM_3.3V";
700 regulator-min- 700 regulator-min-microvolt = <3300000>;
701 regulator-max- 701 regulator-max-microvolt = <3300000>;
702 }; 702 };
703 703
704 buck1_reg: BUCK1 { 704 buck1_reg: BUCK1 {
705 regulator-name 705 regulator-name = "VDD_MIF_0.9V_AP";
706 regulator-min- 706 regulator-min-microvolt = <600000>;
707 regulator-max- 707 regulator-max-microvolt = <1500000>;
708 regulator-alwa 708 regulator-always-on;
709 regulator-stat 709 regulator-state-mem {
710 regula 710 regulator-off-in-suspend;
711 }; 711 };
712 }; 712 };
713 713
714 buck2_reg: BUCK2 { 714 buck2_reg: BUCK2 {
715 regulator-name 715 regulator-name = "VDD_EGL_1.0V_AP";
716 regulator-min- 716 regulator-min-microvolt = <900000>;
717 regulator-max- 717 regulator-max-microvolt = <1300000>;
718 regulator-alwa 718 regulator-always-on;
719 regulator-stat 719 regulator-state-mem {
720 regula 720 regulator-off-in-suspend;
721 }; 721 };
722 }; 722 };
723 723
724 buck3_reg: BUCK3 { 724 buck3_reg: BUCK3 {
725 regulator-name 725 regulator-name = "VDD_KFC_1.0V_AP";
726 regulator-min- 726 regulator-min-microvolt = <800000>;
727 regulator-max- 727 regulator-max-microvolt = <1200000>;
728 regulator-alwa 728 regulator-always-on;
729 regulator-stat 729 regulator-state-mem {
730 regula 730 regulator-off-in-suspend;
731 }; 731 };
732 }; 732 };
733 733
734 buck4_reg: BUCK4 { 734 buck4_reg: BUCK4 {
735 regulator-name 735 regulator-name = "VDD_INT_0.95V_AP";
736 regulator-min- 736 regulator-min-microvolt = <600000>;
737 regulator-max- 737 regulator-max-microvolt = <1500000>;
738 regulator-alwa 738 regulator-always-on;
739 regulator-stat 739 regulator-state-mem {
740 regula 740 regulator-off-in-suspend;
741 }; 741 };
742 }; 742 };
743 743
744 buck5_reg: BUCK5 { 744 buck5_reg: BUCK5 {
745 regulator-name 745 regulator-name = "VDD_DISP_CAM0_0.9V_AP";
746 regulator-min- 746 regulator-min-microvolt = <600000>;
747 regulator-max- 747 regulator-max-microvolt = <1500000>;
748 regulator-alwa 748 regulator-always-on;
749 regulator-stat 749 regulator-state-mem {
750 regula 750 regulator-off-in-suspend;
751 }; 751 };
752 }; 752 };
753 753
754 buck6_reg: BUCK6 { 754 buck6_reg: BUCK6 {
755 regulator-name 755 regulator-name = "VDD_G3D_0.9V_AP";
756 regulator-min- 756 regulator-min-microvolt = <600000>;
757 regulator-max- 757 regulator-max-microvolt = <1500000>;
758 regulator-alwa 758 regulator-always-on;
759 regulator-stat 759 regulator-state-mem {
760 regula 760 regulator-off-in-suspend;
761 }; 761 };
762 }; 762 };
763 763
764 buck7_reg: BUCK7 { 764 buck7_reg: BUCK7 {
765 regulator-name 765 regulator-name = "VDD_MEM1_1.2V_AP";
766 regulator-min- 766 regulator-min-microvolt = <1200000>;
767 regulator-max- 767 regulator-max-microvolt = <1200000>;
768 regulator-alwa 768 regulator-always-on;
769 }; 769 };
770 770
771 buck8_reg: BUCK8 { 771 buck8_reg: BUCK8 {
772 regulator-name 772 regulator-name = "VDD_LLDO_1.35V_AP";
773 regulator-min- 773 regulator-min-microvolt = <1350000>;
774 regulator-max- 774 regulator-max-microvolt = <3300000>;
775 regulator-alwa 775 regulator-always-on;
776 }; 776 };
777 777
778 buck9_reg: BUCK9 { 778 buck9_reg: BUCK9 {
779 regulator-name 779 regulator-name = "VDD_MLDO_2.0V_AP";
780 regulator-min- 780 regulator-min-microvolt = <1350000>;
781 regulator-max- 781 regulator-max-microvolt = <3300000>;
782 regulator-alwa 782 regulator-always-on;
783 }; 783 };
784 784
785 buck10_reg: BUCK10 { 785 buck10_reg: BUCK10 {
786 regulator-name 786 regulator-name = "vdd_mem2";
787 regulator-min- 787 regulator-min-microvolt = <550000>;
788 regulator-max- 788 regulator-max-microvolt = <1500000>;
789 regulator-alwa 789 regulator-always-on;
790 }; 790 };
791 }; 791 };
792 }; 792 };
793 }; 793 };
794 794
795 &hsi2c_4 { 795 &hsi2c_4 {
796 status = "okay"; 796 status = "okay";
797 797
798 s3fwrn5: nfc@27 { 798 s3fwrn5: nfc@27 {
799 compatible = "samsung,s3fwrn5- 799 compatible = "samsung,s3fwrn5-i2c";
800 reg = <0x27>; 800 reg = <0x27>;
801 interrupt-parent = <&gpa1>; 801 interrupt-parent = <&gpa1>;
802 interrupts = <3 IRQ_TYPE_EDGE_ 802 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
803 en-gpios = <&gpf1 4 GPIO_ACTIV 803 en-gpios = <&gpf1 4 GPIO_ACTIVE_LOW>;
804 wake-gpios = <&gpj0 2 GPIO_ACT 804 wake-gpios = <&gpj0 2 GPIO_ACTIVE_HIGH>;
805 }; 805 };
806 }; 806 };
807 807
808 &hsi2c_5 { 808 &hsi2c_5 {
809 status = "okay"; 809 status = "okay";
810 810
811 stmfts: touchscreen@49 { 811 stmfts: touchscreen@49 {
812 compatible = "st,stmfts"; 812 compatible = "st,stmfts";
813 reg = <0x49>; 813 reg = <0x49>;
814 interrupt-parent = <&gpa1>; 814 interrupt-parent = <&gpa1>;
815 interrupts = <1 IRQ_TYPE_LEVEL 815 interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
816 avdd-supply = <&ldo30_reg>; 816 avdd-supply = <&ldo30_reg>;
817 vdd-supply = <&ldo31_reg>; 817 vdd-supply = <&ldo31_reg>;
818 }; 818 };
819 }; 819 };
820 820
821 &hsi2c_7 { 821 &hsi2c_7 {
822 status = "okay"; 822 status = "okay";
823 clock-frequency = <1000000>; 823 clock-frequency = <1000000>;
824 824
825 bridge@39 { 825 bridge@39 {
826 reg = <0x39>; 826 reg = <0x39>;
827 compatible = "sil,sii8620"; 827 compatible = "sil,sii8620";
828 cvcc10-supply = <&ldo36_reg>; 828 cvcc10-supply = <&ldo36_reg>;
829 iovcc18-supply = <&ldo34_reg>; 829 iovcc18-supply = <&ldo34_reg>;
830 interrupt-parent = <&gpf0>; 830 interrupt-parent = <&gpf0>;
831 interrupts = <2 IRQ_TYPE_LEVEL 831 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
832 reset-gpios = <&gpv7 0 GPIO_AC 832 reset-gpios = <&gpv7 0 GPIO_ACTIVE_LOW>;
833 clocks = <&pmu_system_controll 833 clocks = <&pmu_system_controller 0>;
834 clock-names = "xtal"; 834 clock-names = "xtal";
835 835
836 ports { 836 ports {
837 #address-cells = <1>; 837 #address-cells = <1>;
838 #size-cells = <0>; 838 #size-cells = <0>;
839 839
840 port@0 { 840 port@0 {
841 reg = <0>; 841 reg = <0>;
842 mhl_to_hdmi: e 842 mhl_to_hdmi: endpoint {
843 remote 843 remote-endpoint = <&hdmi_to_mhl>;
844 }; 844 };
845 }; 845 };
846 846
847 port@1 { 847 port@1 {
848 reg = <1>; 848 reg = <1>;
849 mhl_to_musb_co 849 mhl_to_musb_con: endpoint {
850 remote 850 remote-endpoint = <&musb_con_to_mhl>;
851 }; 851 };
852 }; 852 };
853 }; 853 };
854 }; 854 };
855 }; 855 };
856 856
857 &hsi2c_8 { 857 &hsi2c_8 {
858 status = "okay"; 858 status = "okay";
859 859
860 pmic@66 { 860 pmic@66 {
861 compatible = "maxim,max77843"; 861 compatible = "maxim,max77843";
862 interrupt-parent = <&gpa1>; 862 interrupt-parent = <&gpa1>;
863 interrupts = <5 IRQ_TYPE_EDGE_ 863 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
864 reg = <0x66>; 864 reg = <0x66>;
865 865
866 muic: extcon { 866 muic: extcon {
867 compatible = "maxim,ma 867 compatible = "maxim,max77843-muic";
868 868
869 musb_con: connector { 869 musb_con: connector {
870 compatible = " 870 compatible = "samsung,usb-connector-11pin",
871 " 871 "usb-b-connector";
872 label = "micro 872 label = "micro-USB";
873 type = "micro" 873 type = "micro";
874 874
875 ports { 875 ports {
876 #addre 876 #address-cells = <1>;
877 #size- 877 #size-cells = <0>;
878 878
879 port@0 879 port@0 {
880 880 /*
881 881 * TODO: The DTS this is based on does not have
882 882 * port@0 which is a required property. The ports
883 883 * look incomplete and need fixing.
884 884 * Add a disabled port just to satisfy dtschema.
885 885 */
886 886 reg = <0>;
887 887 status = "disabled";
888 }; 888 };
889 889
890 port@3 890 port@3 {
891 891 reg = <3>;
892 892 musb_con_to_mhl: endpoint {
893 893 remote-endpoint = <&mhl_to_musb_con>;
894 894 };
895 }; 895 };
896 }; 896 };
897 }; 897 };
898 898
899 ports { 899 ports {
900 port { 900 port {
901 muic_t 901 muic_to_usb: endpoint {
902 902 remote-endpoint = <&usb_to_muic>;
903 }; 903 };
904 }; 904 };
905 }; 905 };
906 }; 906 };
907 907
908 regulators { 908 regulators {
909 compatible = "maxim,ma 909 compatible = "maxim,max77843-regulator";
910 safeout1_reg: SAFEOUT1 910 safeout1_reg: SAFEOUT1 {
911 regulator-name 911 regulator-name = "SAFEOUT1";
912 regulator-min- 912 regulator-min-microvolt = <3300000>;
913 regulator-max- 913 regulator-max-microvolt = <4950000>;
914 }; 914 };
915 915
916 safeout2_reg: SAFEOUT2 916 safeout2_reg: SAFEOUT2 {
917 regulator-name 917 regulator-name = "SAFEOUT2";
918 regulator-min- 918 regulator-min-microvolt = <3300000>;
919 regulator-max- 919 regulator-max-microvolt = <4950000>;
920 }; 920 };
921 921
922 charger_reg: CHARGER { 922 charger_reg: CHARGER {
923 regulator-name 923 regulator-name = "CHARGER";
924 regulator-min- 924 regulator-min-microamp = <100000>;
925 regulator-max- 925 regulator-max-microamp = <3150000>;
926 }; 926 };
927 }; 927 };
928 928
929 haptic: motor-driver { 929 haptic: motor-driver {
930 compatible = "maxim,ma 930 compatible = "maxim,max77843-haptic";
931 haptic-supply = <&ldo3 931 haptic-supply = <&ldo38_reg>;
932 pwms = <&pwm 0 33670 0 932 pwms = <&pwm 0 33670 0>;
933 }; 933 };
934 }; 934 };
935 }; 935 };
936 936
937 &hsi2c_11 { 937 &hsi2c_11 {
938 status = "okay"; 938 status = "okay";
939 }; 939 };
940 940
941 &i2s0 { 941 &i2s0 {
942 status = "okay"; 942 status = "okay";
943 }; 943 };
944 944
945 &i2s1 { 945 &i2s1 {
946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_ 946 assigned-clocks = <&i2s1 CLK_I2S_RCLK_SRC>;
947 assigned-clock-parents = <&cmu_peric C 947 assigned-clock-parents = <&cmu_peric CLK_SCLK_I2S1>;
948 status = "okay"; 948 status = "okay";
949 }; 949 };
950 950
951 &mshc_0 { 951 &mshc_0 {
952 status = "okay"; 952 status = "okay";
953 mmc-ddr-1_8v; 953 mmc-ddr-1_8v;
954 mmc-hs200-1_8v; 954 mmc-hs200-1_8v;
955 mmc-hs400-1_8v; 955 mmc-hs400-1_8v;
956 cap-mmc-highspeed; 956 cap-mmc-highspeed;
957 non-removable; 957 non-removable;
958 card-detect-delay = <200>; 958 card-detect-delay = <200>;
959 samsung,dw-mshc-ciu-div = <3>; 959 samsung,dw-mshc-ciu-div = <3>;
960 samsung,dw-mshc-sdr-timing = <0 4>; 960 samsung,dw-mshc-sdr-timing = <0 4>;
961 samsung,dw-mshc-ddr-timing = <0 2>; 961 samsung,dw-mshc-ddr-timing = <0 2>;
962 samsung,dw-mshc-hs400-timing = <0 3>; 962 samsung,dw-mshc-hs400-timing = <0 3>;
963 samsung,read-strobe-delay = <90>; 963 samsung,read-strobe-delay = <90>;
964 fifo-depth = <0x80>; 964 fifo-depth = <0x80>;
965 pinctrl-names = "default"; 965 pinctrl-names = "default";
966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qr 966 pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
967 &sd0_bus8 &sd0_rdqs>; 967 &sd0_bus8 &sd0_rdqs>;
968 bus-width = <8>; 968 bus-width = <8>;
969 assigned-clocks = <&cmu_top CLK_SCLK_M 969 assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
970 assigned-clock-rates = <800000000>; 970 assigned-clock-rates = <800000000>;
971 }; 971 };
972 972
973 &mshc_2 { 973 &mshc_2 {
974 status = "okay"; 974 status = "okay";
975 cap-sd-highspeed; 975 cap-sd-highspeed;
976 disable-wp; 976 disable-wp;
977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>; 977 cd-gpios = <&gpa2 4 GPIO_ACTIVE_LOW>;
978 card-detect-delay = <200>; 978 card-detect-delay = <200>;
979 samsung,dw-mshc-ciu-div = <3>; 979 samsung,dw-mshc-ciu-div = <3>;
980 samsung,dw-mshc-sdr-timing = <0 4>; 980 samsung,dw-mshc-sdr-timing = <0 4>;
981 samsung,dw-mshc-ddr-timing = <0 2>; 981 samsung,dw-mshc-ddr-timing = <0 2>;
982 fifo-depth = <0x80>; 982 fifo-depth = <0x80>;
983 pinctrl-names = "default"; 983 pinctrl-names = "default";
984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bu 984 pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus1 &sd2_bus4>;
985 bus-width = <4>; 985 bus-width = <4>;
986 }; 986 };
987 987
988 &pcie { 988 &pcie {
989 status = "okay"; 989 status = "okay";
990 pinctrl-names = "default"; 990 pinctrl-names = "default";
991 pinctrl-0 = <&pcie_bus &pcie_wlanen>; 991 pinctrl-0 = <&pcie_bus &pcie_wlanen>;
992 vdd10-supply = <&ldo6_reg>; 992 vdd10-supply = <&ldo6_reg>;
993 vdd18-supply = <&ldo7_reg>; 993 vdd18-supply = <&ldo7_reg>;
994 assigned-clocks = <&cmu_fsys CLK_MOUT_ 994 assigned-clocks = <&cmu_fsys CLK_MOUT_SCLK_PCIE_100_USER>,
995 <&cmu_top CLK_MOUT_S 995 <&cmu_top CLK_MOUT_SCLK_PCIE_100>;
996 assigned-clock-parents = <&cmu_top CLK 996 assigned-clock-parents = <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
997 <&cmu_top CLK 997 <&cmu_top CLK_MOUT_BUS_PLL_USER>;
998 assigned-clock-rates = <0>, <100000000 998 assigned-clock-rates = <0>, <100000000>;
999 interrupt-map-mask = <0 0 0 0>; 999 interrupt-map-mask = <0 0 0 0>;
1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 1000 interrupt-map = <0 0 0 0 &gic GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
1001 }; 1001 };
1002 1002
1003 &pcie_phy { 1003 &pcie_phy {
1004 status = "okay"; 1004 status = "okay";
1005 }; 1005 };
1006 1006
1007 &ppmu_d0_general { 1007 &ppmu_d0_general {
1008 status = "okay"; 1008 status = "okay";
1009 events { 1009 events {
1010 ppmu_event0_d0_general: ppmu- 1010 ppmu_event0_d0_general: ppmu-event0-d0-general {
1011 event-name = "ppmu-ev 1011 event-name = "ppmu-event0-d0-general";
1012 }; 1012 };
1013 }; 1013 };
1014 }; 1014 };
1015 1015
1016 &ppmu_d1_general { 1016 &ppmu_d1_general {
1017 status = "okay"; 1017 status = "okay";
1018 events { 1018 events {
1019 ppmu_event0_d1_general: ppmu- 1019 ppmu_event0_d1_general: ppmu-event0-d1-general {
1020 event-name = "ppmu-eve 1020 event-name = "ppmu-event0-d1-general";
1021 }; 1021 };
1022 }; 1022 };
1023 }; 1023 };
1024 1024
1025 &pinctrl_alive { 1025 &pinctrl_alive {
1026 pinctrl-names = "default"; 1026 pinctrl-names = "default";
1027 pinctrl-0 = <&initial_alive>; 1027 pinctrl-0 = <&initial_alive>;
1028 1028
1029 initial_alive: initial-state { 1029 initial_alive: initial-state {
1030 PIN_IN(gpa0-0, DOWN, FAST_SR1 1030 PIN_IN(gpa0-0, DOWN, FAST_SR1);
1031 PIN_IN(gpa0-1, NONE, FAST_SR1 1031 PIN_IN(gpa0-1, NONE, FAST_SR1);
1032 PIN_IN(gpa0-2, DOWN, FAST_SR1 1032 PIN_IN(gpa0-2, DOWN, FAST_SR1);
1033 PIN_IN(gpa0-3, NONE, FAST_SR1 1033 PIN_IN(gpa0-3, NONE, FAST_SR1);
1034 PIN_IN(gpa0-4, NONE, FAST_SR1 1034 PIN_IN(gpa0-4, NONE, FAST_SR1);
1035 PIN_IN(gpa0-5, DOWN, FAST_SR1 1035 PIN_IN(gpa0-5, DOWN, FAST_SR1);
1036 PIN_IN(gpa0-6, NONE, FAST_SR1 1036 PIN_IN(gpa0-6, NONE, FAST_SR1);
1037 PIN_IN(gpa0-7, NONE, FAST_SR1 1037 PIN_IN(gpa0-7, NONE, FAST_SR1);
1038 1038
1039 PIN_IN(gpa1-0, UP, FAST_SR1); 1039 PIN_IN(gpa1-0, UP, FAST_SR1);
1040 PIN_IN(gpa1-1, UP, FAST_SR1); 1040 PIN_IN(gpa1-1, UP, FAST_SR1);
1041 PIN_IN(gpa1-2, NONE, FAST_SR1 1041 PIN_IN(gpa1-2, NONE, FAST_SR1);
1042 PIN_IN(gpa1-3, DOWN, FAST_SR1 1042 PIN_IN(gpa1-3, DOWN, FAST_SR1);
1043 PIN_IN(gpa1-4, DOWN, FAST_SR1 1043 PIN_IN(gpa1-4, DOWN, FAST_SR1);
1044 PIN_IN(gpa1-5, NONE, FAST_SR1 1044 PIN_IN(gpa1-5, NONE, FAST_SR1);
1045 PIN_IN(gpa1-6, NONE, FAST_SR1 1045 PIN_IN(gpa1-6, NONE, FAST_SR1);
1046 PIN_IN(gpa1-7, NONE, FAST_SR1 1046 PIN_IN(gpa1-7, NONE, FAST_SR1);
1047 1047
1048 PIN_IN(gpa2-0, NONE, FAST_SR1 1048 PIN_IN(gpa2-0, NONE, FAST_SR1);
1049 PIN_IN(gpa2-1, NONE, FAST_SR1 1049 PIN_IN(gpa2-1, NONE, FAST_SR1);
1050 PIN_IN(gpa2-2, NONE, FAST_SR1 1050 PIN_IN(gpa2-2, NONE, FAST_SR1);
1051 PIN_IN(gpa2-3, DOWN, FAST_SR1 1051 PIN_IN(gpa2-3, DOWN, FAST_SR1);
1052 PIN_IN(gpa2-4, NONE, FAST_SR1 1052 PIN_IN(gpa2-4, NONE, FAST_SR1);
1053 PIN_IN(gpa2-5, DOWN, FAST_SR1 1053 PIN_IN(gpa2-5, DOWN, FAST_SR1);
1054 PIN_IN(gpa2-6, DOWN, FAST_SR1 1054 PIN_IN(gpa2-6, DOWN, FAST_SR1);
1055 PIN_IN(gpa2-7, NONE, FAST_SR1 1055 PIN_IN(gpa2-7, NONE, FAST_SR1);
1056 1056
1057 PIN_IN(gpa3-0, DOWN, FAST_SR1 1057 PIN_IN(gpa3-0, DOWN, FAST_SR1);
1058 PIN_IN(gpa3-1, DOWN, FAST_SR1 1058 PIN_IN(gpa3-1, DOWN, FAST_SR1);
1059 PIN_IN(gpa3-2, NONE, FAST_SR1 1059 PIN_IN(gpa3-2, NONE, FAST_SR1);
1060 PIN_IN(gpa3-3, DOWN, FAST_SR1 1060 PIN_IN(gpa3-3, DOWN, FAST_SR1);
1061 PIN_IN(gpa3-4, NONE, FAST_SR1 1061 PIN_IN(gpa3-4, NONE, FAST_SR1);
1062 PIN_IN(gpa3-5, DOWN, FAST_SR1 1062 PIN_IN(gpa3-5, DOWN, FAST_SR1);
1063 PIN_IN(gpa3-6, DOWN, FAST_SR1 1063 PIN_IN(gpa3-6, DOWN, FAST_SR1);
1064 PIN_IN(gpa3-7, DOWN, FAST_SR1 1064 PIN_IN(gpa3-7, DOWN, FAST_SR1);
1065 1065
1066 PIN_IN(gpf1-0, NONE, FAST_SR1 1066 PIN_IN(gpf1-0, NONE, FAST_SR1);
1067 PIN_IN(gpf1-1, NONE, FAST_SR1 1067 PIN_IN(gpf1-1, NONE, FAST_SR1);
1068 PIN_IN(gpf1-2, DOWN, FAST_SR1 1068 PIN_IN(gpf1-2, DOWN, FAST_SR1);
1069 PIN_IN(gpf1-4, UP, FAST_SR1); 1069 PIN_IN(gpf1-4, UP, FAST_SR1);
1070 PIN_OT(gpf1-5, NONE, FAST_SR1 1070 PIN_OT(gpf1-5, NONE, FAST_SR1);
1071 PIN_IN(gpf1-6, DOWN, FAST_SR1 1071 PIN_IN(gpf1-6, DOWN, FAST_SR1);
1072 PIN_IN(gpf1-7, DOWN, FAST_SR1 1072 PIN_IN(gpf1-7, DOWN, FAST_SR1);
1073 1073
1074 PIN_IN(gpf2-0, DOWN, FAST_SR1 1074 PIN_IN(gpf2-0, DOWN, FAST_SR1);
1075 PIN_IN(gpf2-1, DOWN, FAST_SR1 1075 PIN_IN(gpf2-1, DOWN, FAST_SR1);
1076 PIN_IN(gpf2-2, DOWN, FAST_SR1 1076 PIN_IN(gpf2-2, DOWN, FAST_SR1);
1077 PIN_IN(gpf2-3, DOWN, FAST_SR1 1077 PIN_IN(gpf2-3, DOWN, FAST_SR1);
1078 1078
1079 PIN_IN(gpf3-0, DOWN, FAST_SR1 1079 PIN_IN(gpf3-0, DOWN, FAST_SR1);
1080 PIN_IN(gpf3-1, DOWN, FAST_SR1 1080 PIN_IN(gpf3-1, DOWN, FAST_SR1);
1081 PIN_IN(gpf3-2, NONE, FAST_SR1 1081 PIN_IN(gpf3-2, NONE, FAST_SR1);
1082 PIN_IN(gpf3-3, DOWN, FAST_SR1 1082 PIN_IN(gpf3-3, DOWN, FAST_SR1);
1083 1083
1084 PIN_IN(gpf4-0, DOWN, FAST_SR1 1084 PIN_IN(gpf4-0, DOWN, FAST_SR1);
1085 PIN_IN(gpf4-1, DOWN, FAST_SR1 1085 PIN_IN(gpf4-1, DOWN, FAST_SR1);
1086 PIN_IN(gpf4-2, DOWN, FAST_SR1 1086 PIN_IN(gpf4-2, DOWN, FAST_SR1);
1087 PIN_IN(gpf4-3, DOWN, FAST_SR1 1087 PIN_IN(gpf4-3, DOWN, FAST_SR1);
1088 PIN_IN(gpf4-4, DOWN, FAST_SR1 1088 PIN_IN(gpf4-4, DOWN, FAST_SR1);
1089 PIN_IN(gpf4-5, DOWN, FAST_SR1 1089 PIN_IN(gpf4-5, DOWN, FAST_SR1);
1090 PIN_IN(gpf4-6, DOWN, FAST_SR1 1090 PIN_IN(gpf4-6, DOWN, FAST_SR1);
1091 PIN_IN(gpf4-7, DOWN, FAST_SR1 1091 PIN_IN(gpf4-7, DOWN, FAST_SR1);
1092 1092
1093 PIN_IN(gpf5-0, DOWN, FAST_SR1 1093 PIN_IN(gpf5-0, DOWN, FAST_SR1);
1094 PIN_IN(gpf5-1, DOWN, FAST_SR1 1094 PIN_IN(gpf5-1, DOWN, FAST_SR1);
1095 PIN_IN(gpf5-2, DOWN, FAST_SR1 1095 PIN_IN(gpf5-2, DOWN, FAST_SR1);
1096 PIN_IN(gpf5-3, DOWN, FAST_SR1 1096 PIN_IN(gpf5-3, DOWN, FAST_SR1);
1097 PIN_OT(gpf5-4, NONE, FAST_SR1 1097 PIN_OT(gpf5-4, NONE, FAST_SR1);
1098 PIN_IN(gpf5-5, DOWN, FAST_SR1 1098 PIN_IN(gpf5-5, DOWN, FAST_SR1);
1099 PIN_IN(gpf5-6, DOWN, FAST_SR1 1099 PIN_IN(gpf5-6, DOWN, FAST_SR1);
1100 PIN_IN(gpf5-7, DOWN, FAST_SR1 1100 PIN_IN(gpf5-7, DOWN, FAST_SR1);
1101 }; 1101 };
1102 1102
1103 te_irq: te-irq-pins { 1103 te_irq: te-irq-pins {
1104 samsung,pins = "gpf1-3"; 1104 samsung,pins = "gpf1-3";
1105 samsung,pin-function = <EXYNO 1105 samsung,pin-function = <EXYNOS_PIN_FUNC_EINT>;
1106 }; 1106 };
1107 }; 1107 };
1108 1108
1109 &pinctrl_cpif { 1109 &pinctrl_cpif {
1110 pinctrl-names = "default"; 1110 pinctrl-names = "default";
1111 pinctrl-0 = <&initial_cpif>; 1111 pinctrl-0 = <&initial_cpif>;
1112 1112
1113 initial_cpif: initial-state { 1113 initial_cpif: initial-state {
1114 PIN_IN(gpv6-0, DOWN, FAST_SR1 1114 PIN_IN(gpv6-0, DOWN, FAST_SR1);
1115 PIN_IN(gpv6-1, DOWN, FAST_SR1 1115 PIN_IN(gpv6-1, DOWN, FAST_SR1);
1116 }; 1116 };
1117 }; 1117 };
1118 1118
1119 &pinctrl_ese { 1119 &pinctrl_ese {
1120 pinctrl-names = "default"; 1120 pinctrl-names = "default";
1121 pinctrl-0 = <&initial_ese>; 1121 pinctrl-0 = <&initial_ese>;
1122 1122
1123 pcie_wlanen: pcie-wlanen-pins { 1123 pcie_wlanen: pcie-wlanen-pins {
1124 samsung,pins = "gpj2-0"; 1124 samsung,pins = "gpj2-0";
1125 samsung,pin-function = <EXYNO 1125 samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
1126 samsung,pin-pud = <EXYNOS_PIN 1126 samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
1127 samsung,pin-drv = <EXYNOS5433 1127 samsung,pin-drv = <EXYNOS5433_PIN_DRV_FAST_SR4>;
1128 }; 1128 };
1129 1129
1130 initial_ese: initial-state { 1130 initial_ese: initial-state {
1131 PIN_IN(gpj2-1, DOWN, FAST_SR1 1131 PIN_IN(gpj2-1, DOWN, FAST_SR1);
1132 PIN_IN(gpj2-2, DOWN, FAST_SR1 1132 PIN_IN(gpj2-2, DOWN, FAST_SR1);
1133 }; 1133 };
1134 }; 1134 };
1135 1135
1136 &pinctrl_fsys { 1136 &pinctrl_fsys {
1137 pinctrl-names = "default"; 1137 pinctrl-names = "default";
1138 pinctrl-0 = <&initial_fsys>; 1138 pinctrl-0 = <&initial_fsys>;
1139 1139
1140 initial_fsys: initial-state { 1140 initial_fsys: initial-state {
1141 PIN_IN(gpr3-0, NONE, FAST_SR1 1141 PIN_IN(gpr3-0, NONE, FAST_SR1);
1142 PIN_IN(gpr3-1, DOWN, FAST_SR1 1142 PIN_IN(gpr3-1, DOWN, FAST_SR1);
1143 PIN_IN(gpr3-2, DOWN, FAST_SR1 1143 PIN_IN(gpr3-2, DOWN, FAST_SR1);
1144 PIN_IN(gpr3-3, DOWN, FAST_SR1 1144 PIN_IN(gpr3-3, DOWN, FAST_SR1);
1145 PIN_IN(gpr3-7, NONE, FAST_SR1 1145 PIN_IN(gpr3-7, NONE, FAST_SR1);
1146 }; 1146 };
1147 }; 1147 };
1148 1148
1149 &pinctrl_imem { 1149 &pinctrl_imem {
1150 pinctrl-names = "default"; 1150 pinctrl-names = "default";
1151 pinctrl-0 = <&initial_imem>; 1151 pinctrl-0 = <&initial_imem>;
1152 1152
1153 initial_imem: initial-state { 1153 initial_imem: initial-state {
1154 PIN_IN(gpf0-0, UP, FAST_SR1); 1154 PIN_IN(gpf0-0, UP, FAST_SR1);
1155 PIN_IN(gpf0-1, UP, FAST_SR1); 1155 PIN_IN(gpf0-1, UP, FAST_SR1);
1156 PIN_IN(gpf0-2, DOWN, FAST_SR1 1156 PIN_IN(gpf0-2, DOWN, FAST_SR1);
1157 PIN_IN(gpf0-3, UP, FAST_SR1); 1157 PIN_IN(gpf0-3, UP, FAST_SR1);
1158 PIN_IN(gpf0-4, DOWN, FAST_SR1 1158 PIN_IN(gpf0-4, DOWN, FAST_SR1);
1159 PIN_IN(gpf0-5, NONE, FAST_SR1 1159 PIN_IN(gpf0-5, NONE, FAST_SR1);
1160 PIN_IN(gpf0-6, DOWN, FAST_SR1 1160 PIN_IN(gpf0-6, DOWN, FAST_SR1);
1161 PIN_IN(gpf0-7, UP, FAST_SR1); 1161 PIN_IN(gpf0-7, UP, FAST_SR1);
1162 }; 1162 };
1163 }; 1163 };
1164 1164
1165 &pinctrl_nfc { 1165 &pinctrl_nfc {
1166 pinctrl-names = "default"; 1166 pinctrl-names = "default";
1167 pinctrl-0 = <&initial_nfc>; 1167 pinctrl-0 = <&initial_nfc>;
1168 1168
1169 initial_nfc: initial-state { 1169 initial_nfc: initial-state {
1170 PIN_IN(gpj0-2, DOWN, FAST_SR1 1170 PIN_IN(gpj0-2, DOWN, FAST_SR1);
1171 }; 1171 };
1172 }; 1172 };
1173 1173
1174 &pinctrl_peric { 1174 &pinctrl_peric {
1175 pinctrl-names = "default"; 1175 pinctrl-names = "default";
1176 pinctrl-0 = <&initial_peric>; 1176 pinctrl-0 = <&initial_peric>;
1177 1177
1178 initial_peric: initial-state { 1178 initial_peric: initial-state {
1179 PIN_IN(gpv7-0, DOWN, FAST_SR1 1179 PIN_IN(gpv7-0, DOWN, FAST_SR1);
1180 PIN_IN(gpv7-1, DOWN, FAST_SR1 1180 PIN_IN(gpv7-1, DOWN, FAST_SR1);
1181 PIN_IN(gpv7-2, NONE, FAST_SR1 1181 PIN_IN(gpv7-2, NONE, FAST_SR1);
1182 PIN_IN(gpv7-3, DOWN, FAST_SR1 1182 PIN_IN(gpv7-3, DOWN, FAST_SR1);
1183 PIN_IN(gpv7-4, DOWN, FAST_SR1 1183 PIN_IN(gpv7-4, DOWN, FAST_SR1);
1184 PIN_IN(gpv7-5, DOWN, FAST_SR1 1184 PIN_IN(gpv7-5, DOWN, FAST_SR1);
1185 1185
1186 PIN_IN(gpb0-4, DOWN, FAST_SR1 1186 PIN_IN(gpb0-4, DOWN, FAST_SR1);
1187 1187
1188 PIN_IN(gpc0-2, DOWN, FAST_SR1 1188 PIN_IN(gpc0-2, DOWN, FAST_SR1);
1189 PIN_IN(gpc0-5, DOWN, FAST_SR1 1189 PIN_IN(gpc0-5, DOWN, FAST_SR1);
1190 PIN_IN(gpc0-7, DOWN, FAST_SR1 1190 PIN_IN(gpc0-7, DOWN, FAST_SR1);
1191 1191
1192 PIN_IN(gpc1-1, DOWN, FAST_SR1 1192 PIN_IN(gpc1-1, DOWN, FAST_SR1);
1193 1193
1194 PIN_IN(gpc3-4, NONE, FAST_SR1 1194 PIN_IN(gpc3-4, NONE, FAST_SR1);
1195 PIN_IN(gpc3-5, NONE, FAST_SR1 1195 PIN_IN(gpc3-5, NONE, FAST_SR1);
1196 PIN_IN(gpc3-6, NONE, FAST_SR1 1196 PIN_IN(gpc3-6, NONE, FAST_SR1);
1197 PIN_IN(gpc3-7, NONE, FAST_SR1 1197 PIN_IN(gpc3-7, NONE, FAST_SR1);
1198 1198
1199 PIN_OT(gpg0-0, NONE, FAST_SR1 1199 PIN_OT(gpg0-0, NONE, FAST_SR1);
1200 PIN_F2(gpg0-1, DOWN, FAST_SR1 1200 PIN_F2(gpg0-1, DOWN, FAST_SR1);
1201 1201
1202 PIN_IN(gpd2-5, DOWN, FAST_SR1 1202 PIN_IN(gpd2-5, DOWN, FAST_SR1);
1203 1203
1204 PIN_IN(gpd4-0, NONE, FAST_SR1 1204 PIN_IN(gpd4-0, NONE, FAST_SR1);
1205 PIN_IN(gpd4-1, DOWN, FAST_SR1 1205 PIN_IN(gpd4-1, DOWN, FAST_SR1);
1206 PIN_IN(gpd4-2, DOWN, FAST_SR1 1206 PIN_IN(gpd4-2, DOWN, FAST_SR1);
1207 PIN_IN(gpd4-3, DOWN, FAST_SR1 1207 PIN_IN(gpd4-3, DOWN, FAST_SR1);
1208 PIN_IN(gpd4-4, DOWN, FAST_SR1 1208 PIN_IN(gpd4-4, DOWN, FAST_SR1);
1209 1209
1210 PIN_IN(gpd6-3, DOWN, FAST_SR1 1210 PIN_IN(gpd6-3, DOWN, FAST_SR1);
1211 1211
1212 PIN_IN(gpd8-1, UP, FAST_SR1); 1212 PIN_IN(gpd8-1, UP, FAST_SR1);
1213 1213
1214 PIN_IN(gpg1-0, DOWN, FAST_SR1 1214 PIN_IN(gpg1-0, DOWN, FAST_SR1);
1215 PIN_IN(gpg1-1, DOWN, FAST_SR1 1215 PIN_IN(gpg1-1, DOWN, FAST_SR1);
1216 PIN_IN(gpg1-2, DOWN, FAST_SR1 1216 PIN_IN(gpg1-2, DOWN, FAST_SR1);
1217 PIN_IN(gpg1-3, DOWN, FAST_SR1 1217 PIN_IN(gpg1-3, DOWN, FAST_SR1);
1218 PIN_IN(gpg1-4, DOWN, FAST_SR1 1218 PIN_IN(gpg1-4, DOWN, FAST_SR1);
1219 1219
1220 PIN_IN(gpg2-0, DOWN, FAST_SR1 1220 PIN_IN(gpg2-0, DOWN, FAST_SR1);
1221 PIN_IN(gpg2-1, DOWN, FAST_SR1 1221 PIN_IN(gpg2-1, DOWN, FAST_SR1);
1222 1222
1223 PIN_IN(gpg3-0, DOWN, FAST_SR1 1223 PIN_IN(gpg3-0, DOWN, FAST_SR1);
1224 PIN_IN(gpg3-1, DOWN, FAST_SR1 1224 PIN_IN(gpg3-1, DOWN, FAST_SR1);
1225 PIN_IN(gpg3-5, DOWN, FAST_SR1 1225 PIN_IN(gpg3-5, DOWN, FAST_SR1);
1226 }; 1226 };
1227 }; 1227 };
1228 1228
1229 &pinctrl_touch { 1229 &pinctrl_touch {
1230 pinctrl-names = "default"; 1230 pinctrl-names = "default";
1231 pinctrl-0 = <&initial_touch>; 1231 pinctrl-0 = <&initial_touch>;
1232 1232
1233 initial_touch: initial-state { 1233 initial_touch: initial-state {
1234 PIN_IN(gpj1-2, DOWN, FAST_SR1 1234 PIN_IN(gpj1-2, DOWN, FAST_SR1);
1235 }; 1235 };
1236 }; 1236 };
1237 1237
1238 &pwm { 1238 &pwm {
1239 pinctrl-0 = <&pwm0_out>; 1239 pinctrl-0 = <&pwm0_out>;
1240 pinctrl-names = "default"; 1240 pinctrl-names = "default";
1241 status = "okay"; 1241 status = "okay";
1242 }; 1242 };
1243 1243
1244 &mic { 1244 &mic {
1245 status = "okay"; 1245 status = "okay";
1246 }; 1246 };
1247 1247
1248 &pmu_system_controller { 1248 &pmu_system_controller {
1249 assigned-clocks = <&pmu_system_contro 1249 assigned-clocks = <&pmu_system_controller 0>;
1250 assigned-clock-parents = <&xxti>; 1250 assigned-clock-parents = <&xxti>;
1251 }; 1251 };
1252 1252
1253 &serial_1 { 1253 &serial_1 {
1254 status = "okay"; 1254 status = "okay";
1255 }; 1255 };
1256 1256
1257 &serial_3 { 1257 &serial_3 {
1258 status = "okay"; 1258 status = "okay";
1259 1259
1260 bluetooth { 1260 bluetooth {
1261 compatible = "brcm,bcm43438-b 1261 compatible = "brcm,bcm43438-bt";
1262 max-speed = <3000000>; 1262 max-speed = <3000000>;
1263 shutdown-gpios = <&gpd4 0 GPI 1263 shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
1264 device-wakeup-gpios = <&gpr3 1264 device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
1265 host-wakeup-gpios = <&gpa2 2 1265 host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
1266 clocks = <&s2mps13_osc S2MPS1 1266 clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
1267 clock-names = "extclk"; 1267 clock-names = "extclk";
1268 }; 1268 };
1269 }; 1269 };
1270 1270
1271 &spi_1 { 1271 &spi_1 {
1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH> 1272 cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
1273 status = "okay"; 1273 status = "okay";
1274 1274
1275 wm5110: audio-codec@0 { 1275 wm5110: audio-codec@0 {
1276 compatible = "wlf,wm5110"; 1276 compatible = "wlf,wm5110";
1277 reg = <0x0>; 1277 reg = <0x0>;
1278 spi-max-frequency = <20000000 1278 spi-max-frequency = <20000000>;
1279 interrupt-parent = <&gpa0>; 1279 interrupt-parent = <&gpa0>;
1280 interrupts = <4 IRQ_TYPE_NONE 1280 interrupts = <4 IRQ_TYPE_NONE>;
1281 clocks = <&pmu_system_control 1281 clocks = <&pmu_system_controller 0>,
1282 <&s2mps13_osc S2MPS11 1282 <&s2mps13_osc S2MPS11_CLK_BT>;
1283 clock-names = "mclk1", "mclk2 1283 clock-names = "mclk1", "mclk2";
1284 1284
1285 gpio-controller; 1285 gpio-controller;
1286 #gpio-cells = <2>; 1286 #gpio-cells = <2>;
1287 interrupt-controller; 1287 interrupt-controller;
1288 #interrupt-cells = <2>; 1288 #interrupt-cells = <2>;
1289 1289
1290 wlf,micd-detect-debounce = <3 1290 wlf,micd-detect-debounce = <300>;
1291 wlf,micd-bias-start-time = <0 1291 wlf,micd-bias-start-time = <0x1>;
1292 wlf,micd-rate = <0x7>; 1292 wlf,micd-rate = <0x7>;
1293 wlf,micd-dbtime = <0x2>; 1293 wlf,micd-dbtime = <0x2>;
1294 wlf,micd-force-micbias; 1294 wlf,micd-force-micbias;
1295 wlf,micd-configs = <0x0 1 0>; 1295 wlf,micd-configs = <0x0 1 0>;
1296 wlf,hpdet-channel = <1>; 1296 wlf,hpdet-channel = <1>;
1297 wlf,gpsw = <0x1>; 1297 wlf,gpsw = <0x1>;
1298 wlf,inmode = <2 0 2 0>; 1298 wlf,inmode = <2 0 2 0>;
1299 1299
1300 wlf,reset = <&gpc0 7 GPIO_ACT 1300 wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
1301 wlf,ldoena = <&gpf0 0 GPIO_AC 1301 wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
1302 1302
1303 /* core supplies */ 1303 /* core supplies */
1304 AVDD-supply = <&ldo18_reg>; 1304 AVDD-supply = <&ldo18_reg>;
1305 DBVDD1-supply = <&ldo18_reg>; 1305 DBVDD1-supply = <&ldo18_reg>;
1306 CPVDD-supply = <&ldo18_reg>; 1306 CPVDD-supply = <&ldo18_reg>;
1307 DBVDD2-supply = <&ldo18_reg>; 1307 DBVDD2-supply = <&ldo18_reg>;
1308 DBVDD3-supply = <&ldo18_reg>; 1308 DBVDD3-supply = <&ldo18_reg>;
1309 SPKVDDL-supply = <&vph_pwr_re 1309 SPKVDDL-supply = <&vph_pwr_regulator>;
1310 SPKVDDR-supply = <&vph_pwr_re 1310 SPKVDDR-supply = <&vph_pwr_regulator>;
1311 1311
1312 controller-data { 1312 controller-data {
1313 samsung,spi-feedback- 1313 samsung,spi-feedback-delay = <0>;
1314 }; 1314 };
1315 }; 1315 };
1316 }; 1316 };
1317 1317
1318 &spi_3 { 1318 &spi_3 {
1319 status = "okay"; 1319 status = "okay";
1320 no-cs-readback; 1320 no-cs-readback;
1321 1321
1322 irled@0 { 1322 irled@0 {
1323 compatible = "ir-spi-led"; 1323 compatible = "ir-spi-led";
1324 reg = <0x0>; 1324 reg = <0x0>;
1325 spi-max-frequency = <5000000> 1325 spi-max-frequency = <5000000>;
1326 power-supply = <&irda_regulat 1326 power-supply = <&irda_regulator>;
1327 duty-cycle = /bits/ 8 <60>; 1327 duty-cycle = /bits/ 8 <60>;
1328 led-active-low; 1328 led-active-low;
1329 1329
1330 controller-data { 1330 controller-data {
1331 samsung,spi-feedback- 1331 samsung,spi-feedback-delay = <0>;
1332 }; 1332 };
1333 }; 1333 };
1334 }; 1334 };
1335 1335
1336 &timer { 1336 &timer {
1337 clock-frequency = <24000000>; 1337 clock-frequency = <24000000>;
1338 }; 1338 };
1339 1339
1340 &tmu_atlas0 { 1340 &tmu_atlas0 {
1341 vtmu-supply = <&ldo3_reg>; 1341 vtmu-supply = <&ldo3_reg>;
1342 status = "okay"; 1342 status = "okay";
1343 }; 1343 };
1344 1344
1345 &tmu_apollo { 1345 &tmu_apollo {
1346 vtmu-supply = <&ldo3_reg>; 1346 vtmu-supply = <&ldo3_reg>;
1347 status = "okay"; 1347 status = "okay";
1348 }; 1348 };
1349 1349
1350 &tmu_g3d { 1350 &tmu_g3d {
1351 vtmu-supply = <&ldo3_reg>; 1351 vtmu-supply = <&ldo3_reg>;
1352 status = "okay"; 1352 status = "okay";
1353 }; 1353 };
1354 1354
1355 &usbdrd30 { 1355 &usbdrd30 {
1356 vdd33-supply = <&ldo10_reg>; 1356 vdd33-supply = <&ldo10_reg>;
1357 vdd10-supply = <&ldo6_reg>; 1357 vdd10-supply = <&ldo6_reg>;
1358 status = "okay"; 1358 status = "okay";
1359 }; 1359 };
1360 1360
1361 &usbdrd_dwc3 { 1361 &usbdrd_dwc3 {
1362 dr_mode = "otg"; 1362 dr_mode = "otg";
1363 }; 1363 };
1364 1364
1365 &usbdrd30_phy { 1365 &usbdrd30_phy {
1366 vbus-supply = <&safeout1_reg>; 1366 vbus-supply = <&safeout1_reg>;
1367 status = "okay"; 1367 status = "okay";
1368 1368
1369 port { 1369 port {
1370 usb_to_muic: endpoint { 1370 usb_to_muic: endpoint {
1371 remote-endpoint = <&m 1371 remote-endpoint = <&muic_to_usb>;
1372 }; 1372 };
1373 }; 1373 };
1374 }; 1374 };
1375 1375
1376 &xxti { 1376 &xxti {
1377 clock-frequency = <24000000>; 1377 clock-frequency = <24000000>;
1378 }; 1378 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.