1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's ExynosAutov920 SoC device tree so 3 * Samsung's ExynosAutov920 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Samsung Electronics Co., 5 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/samsung,exynosauto 9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h 11 #include <dt-bindings/soc/samsung,exynos-usi.h>
12 12
13 / { 13 / {
14 compatible = "samsung,exynosautov920"; 14 compatible = "samsung,exynosautov920";
15 #address-cells = <2>; 15 #address-cells = <2>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 17
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 19
20 aliases { 20 aliases {
21 pinctrl0 = &pinctrl_alive; 21 pinctrl0 = &pinctrl_alive;
22 pinctrl1 = &pinctrl_aud; 22 pinctrl1 = &pinctrl_aud;
23 pinctrl2 = &pinctrl_hsi0; 23 pinctrl2 = &pinctrl_hsi0;
24 pinctrl3 = &pinctrl_hsi1; 24 pinctrl3 = &pinctrl_hsi1;
25 pinctrl4 = &pinctrl_hsi2; 25 pinctrl4 = &pinctrl_hsi2;
26 pinctrl5 = &pinctrl_hsi2ufs; 26 pinctrl5 = &pinctrl_hsi2ufs;
27 pinctrl6 = &pinctrl_peric0; 27 pinctrl6 = &pinctrl_peric0;
28 pinctrl7 = &pinctrl_peric1; 28 pinctrl7 = &pinctrl_peric1;
29 }; 29 };
30 30
31 arm-pmu { 31 arm-pmu {
32 compatible = "arm,cortex-a78-p 32 compatible = "arm,cortex-a78-pmu";
33 interrupts = <GIC_PPI 7 IRQ_TY 33 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
34 }; 34 };
35 35
36 xtcxo: clock { 36 xtcxo: clock {
37 compatible = "fixed-clock"; 37 compatible = "fixed-clock";
38 #clock-cells = <0>; 38 #clock-cells = <0>;
39 clock-output-names = "oscclk"; 39 clock-output-names = "oscclk";
40 }; 40 };
41 41
42 cpus: cpus { 42 cpus: cpus {
43 #address-cells = <2>; 43 #address-cells = <2>;
44 #size-cells = <0>; 44 #size-cells = <0>;
45 45
46 cpu-map { 46 cpu-map {
47 cluster0 { 47 cluster0 {
48 core0 { 48 core0 {
49 cpu = 49 cpu = <&cpu0>;
50 }; 50 };
51 core1 { 51 core1 {
52 cpu = 52 cpu = <&cpu1>;
53 }; 53 };
54 core2 { 54 core2 {
55 cpu = 55 cpu = <&cpu2>;
56 }; 56 };
57 core3 { 57 core3 {
58 cpu = 58 cpu = <&cpu3>;
59 }; 59 };
60 }; 60 };
61 61
62 cluster1 { 62 cluster1 {
63 core0 { 63 core0 {
64 cpu = 64 cpu = <&cpu4>;
65 }; 65 };
66 core1 { 66 core1 {
67 cpu = 67 cpu = <&cpu5>;
68 }; 68 };
69 core2 { 69 core2 {
70 cpu = 70 cpu = <&cpu6>;
71 }; 71 };
72 core3 { 72 core3 {
73 cpu = 73 cpu = <&cpu7>;
74 }; 74 };
75 }; 75 };
76 76
77 cluster2 { 77 cluster2 {
78 core0 { 78 core0 {
79 cpu = 79 cpu = <&cpu8>;
80 }; 80 };
81 core1 { 81 core1 {
82 cpu = 82 cpu = <&cpu9>;
83 }; 83 };
84 }; 84 };
85 }; 85 };
86 86
87 cpu0: cpu@0 { 87 cpu0: cpu@0 {
88 device_type = "cpu"; 88 device_type = "cpu";
89 compatible = "arm,cort 89 compatible = "arm,cortex-a78ae";
90 reg = <0x0 0x0>; 90 reg = <0x0 0x0>;
91 enable-method = "psci" 91 enable-method = "psci";
92 }; 92 };
93 93
94 cpu1: cpu@100 { 94 cpu1: cpu@100 {
95 device_type = "cpu"; 95 device_type = "cpu";
96 compatible = "arm,cort 96 compatible = "arm,cortex-a78ae";
97 reg = <0x0 0x100>; 97 reg = <0x0 0x100>;
98 enable-method = "psci" 98 enable-method = "psci";
99 }; 99 };
100 100
101 cpu2: cpu@200 { 101 cpu2: cpu@200 {
102 device_type = "cpu"; 102 device_type = "cpu";
103 compatible = "arm,cort 103 compatible = "arm,cortex-a78ae";
104 reg = <0x0 0x200>; 104 reg = <0x0 0x200>;
105 enable-method = "psci" 105 enable-method = "psci";
106 }; 106 };
107 107
108 cpu3: cpu@300 { 108 cpu3: cpu@300 {
109 device_type = "cpu"; 109 device_type = "cpu";
110 compatible = "arm,cort 110 compatible = "arm,cortex-a78ae";
111 reg = <0x0 0x300>; 111 reg = <0x0 0x300>;
112 enable-method = "psci" 112 enable-method = "psci";
113 }; 113 };
114 114
115 cpu4: cpu@10000 { 115 cpu4: cpu@10000 {
116 device_type = "cpu"; 116 device_type = "cpu";
117 compatible = "arm,cort 117 compatible = "arm,cortex-a78ae";
118 reg = <0x0 0x10000>; 118 reg = <0x0 0x10000>;
119 enable-method = "psci" 119 enable-method = "psci";
120 }; 120 };
121 121
122 cpu5: cpu@10100 { 122 cpu5: cpu@10100 {
123 device_type = "cpu"; 123 device_type = "cpu";
124 compatible = "arm,cort 124 compatible = "arm,cortex-a78ae";
125 reg = <0x0 0x10100>; 125 reg = <0x0 0x10100>;
126 enable-method = "psci" 126 enable-method = "psci";
127 }; 127 };
128 128
129 cpu6: cpu@10200 { 129 cpu6: cpu@10200 {
130 device_type = "cpu"; 130 device_type = "cpu";
131 compatible = "arm,cort 131 compatible = "arm,cortex-a78ae";
132 reg = <0x0 0x10200>; 132 reg = <0x0 0x10200>;
133 enable-method = "psci" 133 enable-method = "psci";
134 }; 134 };
135 135
136 cpu7: cpu@10300 { 136 cpu7: cpu@10300 {
137 device_type = "cpu"; 137 device_type = "cpu";
138 compatible = "arm,cort 138 compatible = "arm,cortex-a78ae";
139 reg = <0x0 0x10300>; 139 reg = <0x0 0x10300>;
140 enable-method = "psci" 140 enable-method = "psci";
141 }; 141 };
142 142
143 cpu8: cpu@20000 { 143 cpu8: cpu@20000 {
144 device_type = "cpu"; 144 device_type = "cpu";
145 compatible = "arm,cort 145 compatible = "arm,cortex-a78ae";
146 reg = <0x0 0x20000>; 146 reg = <0x0 0x20000>;
147 enable-method = "psci" 147 enable-method = "psci";
148 }; 148 };
149 149
150 cpu9: cpu@20100 { 150 cpu9: cpu@20100 {
151 device_type = "cpu"; 151 device_type = "cpu";
152 compatible = "arm,cort 152 compatible = "arm,cortex-a78ae";
153 reg = <0x0 0x20100>; 153 reg = <0x0 0x20100>;
154 enable-method = "psci" 154 enable-method = "psci";
155 }; 155 };
156 }; 156 };
157 157
158 psci { 158 psci {
159 compatible = "arm,psci-1.0"; 159 compatible = "arm,psci-1.0";
160 method = "smc"; 160 method = "smc";
161 }; 161 };
162 162
163 soc: soc@0 { 163 soc: soc@0 {
164 compatible = "simple-bus"; 164 compatible = "simple-bus";
165 #address-cells = <1>; 165 #address-cells = <1>;
166 #size-cells = <1>; 166 #size-cells = <1>;
167 ranges = <0x0 0x0 0x0 0x200000 167 ranges = <0x0 0x0 0x0 0x20000000>;
168 168
169 chipid@10000000 { 169 chipid@10000000 {
170 compatible = "samsung, 170 compatible = "samsung,exynosautov920-chipid",
171 "samsung, 171 "samsung,exynos850-chipid";
172 reg = <0x10000000 0x24 172 reg = <0x10000000 0x24>;
173 }; 173 };
174 174
175 gic: interrupt-controller@1040 175 gic: interrupt-controller@10400000 {
176 compatible = "arm,gic- 176 compatible = "arm,gic-v3";
177 #interrupt-cells = <3> 177 #interrupt-cells = <3>;
178 #address-cells = <0>; 178 #address-cells = <0>;
179 interrupt-controller; 179 interrupt-controller;
180 reg = <0x10400000 0x10 180 reg = <0x10400000 0x10000>,
181 <0x10460000 0x14 181 <0x10460000 0x140000>;
182 interrupts = <GIC_PPI 182 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
183 }; 183 };
184 184
185 cmu_peric0: clock-controller@1 185 cmu_peric0: clock-controller@10800000 {
186 compatible = "samsung, 186 compatible = "samsung,exynosautov920-cmu-peric0";
187 reg = <0x10800000 0x80 187 reg = <0x10800000 0x8000>;
188 #clock-cells = <1>; 188 #clock-cells = <1>;
189 189
190 clocks = <&xtcxo>, 190 clocks = <&xtcxo>,
191 <&cmu_top DOU 191 <&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
192 <&cmu_top DOU 192 <&cmu_top DOUT_CLKCMU_PERIC0_IP>;
193 clock-names = "oscclk" 193 clock-names = "oscclk",
194 "noc", 194 "noc",
195 "ip"; 195 "ip";
196 }; 196 };
197 197
198 syscon_peric0: syscon@10820000 198 syscon_peric0: syscon@10820000 {
199 compatible = "samsung, 199 compatible = "samsung,exynosautov920-peric0-sysreg",
200 "syscon"; 200 "syscon";
201 reg = <0x10820000 0x20 201 reg = <0x10820000 0x2000>;
202 }; 202 };
203 203
204 pinctrl_peric0: pinctrl@108300 204 pinctrl_peric0: pinctrl@10830000 {
205 compatible = "samsung, 205 compatible = "samsung,exynosautov920-pinctrl";
206 reg = <0x10830000 0x10 206 reg = <0x10830000 0x10000>;
207 interrupts = <GIC_SPI 207 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
208 }; 208 };
209 209
210 usi_0: usi@108800c0 { 210 usi_0: usi@108800c0 {
211 compatible = "samsung, 211 compatible = "samsung,exynosautov920-usi",
212 "samsung, 212 "samsung,exynos850-usi";
213 reg = <0x108800c0 0x20 213 reg = <0x108800c0 0x20>;
214 samsung,sysreg = <&sys 214 samsung,sysreg = <&syscon_peric0 0x1000>;
215 samsung,mode = <USI_V2 215 samsung,mode = <USI_V2_UART>;
216 #address-cells = <1>; 216 #address-cells = <1>;
217 #size-cells = <1>; 217 #size-cells = <1>;
218 ranges; 218 ranges;
219 clocks = <&cmu_peric0 219 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
220 <&cmu_peric0 220 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
221 clock-names = "pclk", 221 clock-names = "pclk", "ipclk";
222 status = "disabled"; 222 status = "disabled";
223 223
224 serial_0: serial@10880 224 serial_0: serial@10880000 {
225 compatible = " 225 compatible = "samsung,exynosautov920-uart",
226 " 226 "samsung,exynos850-uart";
227 reg = <0x10880 227 reg = <0x10880000 0xc0>;
228 interrupts = < 228 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
229 pinctrl-names 229 pinctrl-names = "default";
230 pinctrl-0 = <& 230 pinctrl-0 = <&uart0_bus>;
231 clocks = <&cmu 231 clocks = <&cmu_peric0 CLK_MOUT_PERIC0_NOC_USER>,
232 <&cmu 232 <&cmu_peric0 CLK_DOUT_PERIC0_USI00_USI>;
233 clock-names = 233 clock-names = "uart", "clk_uart_baud0";
234 samsung,uart-f 234 samsung,uart-fifosize = <256>;
235 status = "disa 235 status = "disabled";
236 }; 236 };
237 }; 237 };
238 238
239 pwm: pwm@109b0000 { 239 pwm: pwm@109b0000 {
240 compatible = "samsung, 240 compatible = "samsung,exynosautov920-pwm",
241 "samsung, 241 "samsung,exynos4210-pwm";
242 reg = <0x109b0000 0x10 242 reg = <0x109b0000 0x100>;
243 samsung,pwm-outputs = 243 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
244 #pwm-cells = <3>; 244 #pwm-cells = <3>;
245 clocks = <&xtcxo>; 245 clocks = <&xtcxo>;
246 clock-names = "timers" 246 clock-names = "timers";
247 status = "disabled"; 247 status = "disabled";
248 }; 248 };
249 249
250 syscon_peric1: syscon@10c20000 250 syscon_peric1: syscon@10c20000 {
251 compatible = "samsung, 251 compatible = "samsung,exynosautov920-peric1-sysreg",
252 "syscon"; 252 "syscon";
253 reg = <0x10c20000 0x20 253 reg = <0x10c20000 0x2000>;
254 }; 254 };
255 255
256 pinctrl_peric1: pinctrl@10c300 256 pinctrl_peric1: pinctrl@10c30000 {
257 compatible = "samsung, 257 compatible = "samsung,exynosautov920-pinctrl";
258 reg = <0x10c30000 0x10 258 reg = <0x10c30000 0x10000>;
259 interrupts = <GIC_SPI 259 interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
260 }; 260 };
261 261
262 cmu_top: clock-controller@1100 262 cmu_top: clock-controller@11000000 {
263 compatible = "samsung, 263 compatible = "samsung,exynosautov920-cmu-top";
264 reg = <0x11000000 0x80 264 reg = <0x11000000 0x8000>;
265 #clock-cells = <1>; 265 #clock-cells = <1>;
266 266
267 clocks = <&xtcxo>; 267 clocks = <&xtcxo>;
268 clock-names = "oscclk" 268 clock-names = "oscclk";
269 }; 269 };
270 270
271 pinctrl_alive: pinctrl@1185000 271 pinctrl_alive: pinctrl@11850000 {
272 compatible = "samsung, 272 compatible = "samsung,exynosautov920-pinctrl";
273 reg = <0x11850000 0x10 273 reg = <0x11850000 0x10000>;
274 274
275 wakeup-interrupt-contr 275 wakeup-interrupt-controller {
276 compatible = " 276 compatible = "samsung,exynosautov920-wakeup-eint";
277 }; 277 };
278 }; 278 };
279 279
280 pmu_system_controller: system- 280 pmu_system_controller: system-controller@11860000 {
281 compatible = "samsung, 281 compatible = "samsung,exynosautov920-pmu",
282 "samsung, 282 "samsung,exynos7-pmu","syscon";
283 reg = <0x11860000 0x10 283 reg = <0x11860000 0x10000>;
284 }; 284 };
285 285
286 pinctrl_hsi0: pinctrl@16040000 286 pinctrl_hsi0: pinctrl@16040000 {
287 compatible = "samsung, 287 compatible = "samsung,exynosautov920-pinctrl";
288 reg = <0x16040000 0x10 288 reg = <0x16040000 0x10000>;
289 interrupts = <GIC_SPI 289 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
290 }; 290 };
291 291
292 pinctrl_hsi1: pinctrl@16450000 292 pinctrl_hsi1: pinctrl@16450000 {
293 compatible = "samsung, 293 compatible = "samsung,exynosautov920-pinctrl";
294 reg = <0x16450000 0x10 294 reg = <0x16450000 0x10000>;
295 interrupts = <GIC_SPI 295 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
296 }; 296 };
297 297
298 pinctrl_hsi2: pinctrl@16c10000 298 pinctrl_hsi2: pinctrl@16c10000 {
299 compatible = "samsung, 299 compatible = "samsung,exynosautov920-pinctrl";
300 reg = <0x16c10000 0x10 300 reg = <0x16c10000 0x10000>;
301 interrupts = <GIC_SPI 301 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
302 }; 302 };
303 303
304 pinctrl_hsi2ufs: pinctrl@16d20 304 pinctrl_hsi2ufs: pinctrl@16d20000 {
305 compatible = "samsung, 305 compatible = "samsung,exynosautov920-pinctrl";
306 reg = <0x16d20000 0x10 306 reg = <0x16d20000 0x10000>;
307 interrupts = <GIC_SPI 307 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
308 }; 308 };
309 309
310 pinctrl_aud: pinctrl@1a460000 310 pinctrl_aud: pinctrl@1a460000 {
311 compatible = "samsung, 311 compatible = "samsung,exynosautov920-pinctrl";
312 reg = <0x1a460000 0x10 312 reg = <0x1a460000 0x10000>;
313 }; 313 };
314 }; 314 };
315 315
316 timer { 316 timer {
317 compatible = "arm,armv8-timer" 317 compatible = "arm,armv8-timer";
318 interrupts = <GIC_PPI 13 IRQ_T 318 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
319 <GIC_PPI 14 IRQ_T 319 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
320 <GIC_PPI 11 IRQ_T 320 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
321 <GIC_PPI 10 IRQ_T 321 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
322 <GIC_PPI 12 IRQ_T 322 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
323 }; 323 };
324 }; 324 };
325 325
326 #include "exynosautov920-pinctrl.dtsi" 326 #include "exynosautov920-pinctrl.dtsi"
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