1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Samsung's ExynosAutov920 SoC device tree so 3 * Samsung's ExynosAutov920 SoC device tree source
4 * 4 *
5 * Copyright (c) 2023 Samsung Electronics Co., 5 * Copyright (c) 2023 Samsung Electronics Co., Ltd.
6 * 6 *
7 */ 7 */
8 8
9 #include <dt-bindings/clock/samsung,exynosauto <<
10 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h 10 #include <dt-bindings/soc/samsung,exynos-usi.h>
12 11
13 / { 12 / {
14 compatible = "samsung,exynosautov920"; 13 compatible = "samsung,exynosautov920";
15 #address-cells = <2>; 14 #address-cells = <2>;
16 #size-cells = <1>; 15 #size-cells = <1>;
17 16
18 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
19 18
20 aliases { 19 aliases {
21 pinctrl0 = &pinctrl_alive; 20 pinctrl0 = &pinctrl_alive;
22 pinctrl1 = &pinctrl_aud; 21 pinctrl1 = &pinctrl_aud;
23 pinctrl2 = &pinctrl_hsi0; 22 pinctrl2 = &pinctrl_hsi0;
24 pinctrl3 = &pinctrl_hsi1; 23 pinctrl3 = &pinctrl_hsi1;
25 pinctrl4 = &pinctrl_hsi2; 24 pinctrl4 = &pinctrl_hsi2;
26 pinctrl5 = &pinctrl_hsi2ufs; 25 pinctrl5 = &pinctrl_hsi2ufs;
27 pinctrl6 = &pinctrl_peric0; 26 pinctrl6 = &pinctrl_peric0;
28 pinctrl7 = &pinctrl_peric1; 27 pinctrl7 = &pinctrl_peric1;
29 }; 28 };
30 29
31 arm-pmu { 30 arm-pmu {
32 compatible = "arm,cortex-a78-p 31 compatible = "arm,cortex-a78-pmu";
33 interrupts = <GIC_PPI 7 IRQ_TY 32 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
34 }; 33 };
35 34
36 xtcxo: clock { 35 xtcxo: clock {
37 compatible = "fixed-clock"; 36 compatible = "fixed-clock";
38 #clock-cells = <0>; 37 #clock-cells = <0>;
39 clock-output-names = "oscclk"; 38 clock-output-names = "oscclk";
40 }; 39 };
41 40
>> 41 /*
>> 42 * FIXME: Keep the stub clock for serial driver, until proper clock
>> 43 * driver is implemented.
>> 44 */
>> 45 clock_usi: clock-usi {
>> 46 compatible = "fixed-clock";
>> 47 #clock-cells = <0>;
>> 48 clock-frequency = <200000000>;
>> 49 clock-output-names = "usi";
>> 50 };
>> 51
42 cpus: cpus { 52 cpus: cpus {
43 #address-cells = <2>; 53 #address-cells = <2>;
44 #size-cells = <0>; 54 #size-cells = <0>;
45 55
46 cpu-map { 56 cpu-map {
47 cluster0 { 57 cluster0 {
48 core0 { 58 core0 {
49 cpu = 59 cpu = <&cpu0>;
50 }; 60 };
51 core1 { 61 core1 {
52 cpu = 62 cpu = <&cpu1>;
53 }; 63 };
54 core2 { 64 core2 {
55 cpu = 65 cpu = <&cpu2>;
56 }; 66 };
57 core3 { 67 core3 {
58 cpu = 68 cpu = <&cpu3>;
59 }; 69 };
60 }; 70 };
61 71
62 cluster1 { 72 cluster1 {
63 core0 { 73 core0 {
64 cpu = 74 cpu = <&cpu4>;
65 }; 75 };
66 core1 { 76 core1 {
67 cpu = 77 cpu = <&cpu5>;
68 }; 78 };
69 core2 { 79 core2 {
70 cpu = 80 cpu = <&cpu6>;
71 }; 81 };
72 core3 { 82 core3 {
73 cpu = 83 cpu = <&cpu7>;
74 }; 84 };
75 }; 85 };
76 86
77 cluster2 { 87 cluster2 {
78 core0 { 88 core0 {
79 cpu = 89 cpu = <&cpu8>;
80 }; 90 };
81 core1 { 91 core1 {
82 cpu = 92 cpu = <&cpu9>;
83 }; 93 };
84 }; 94 };
85 }; 95 };
86 96
87 cpu0: cpu@0 { 97 cpu0: cpu@0 {
88 device_type = "cpu"; 98 device_type = "cpu";
89 compatible = "arm,cort 99 compatible = "arm,cortex-a78ae";
90 reg = <0x0 0x0>; 100 reg = <0x0 0x0>;
91 enable-method = "psci" 101 enable-method = "psci";
92 }; 102 };
93 103
94 cpu1: cpu@100 { 104 cpu1: cpu@100 {
95 device_type = "cpu"; 105 device_type = "cpu";
96 compatible = "arm,cort 106 compatible = "arm,cortex-a78ae";
97 reg = <0x0 0x100>; 107 reg = <0x0 0x100>;
98 enable-method = "psci" 108 enable-method = "psci";
99 }; 109 };
100 110
101 cpu2: cpu@200 { 111 cpu2: cpu@200 {
102 device_type = "cpu"; 112 device_type = "cpu";
103 compatible = "arm,cort 113 compatible = "arm,cortex-a78ae";
104 reg = <0x0 0x200>; 114 reg = <0x0 0x200>;
105 enable-method = "psci" 115 enable-method = "psci";
106 }; 116 };
107 117
108 cpu3: cpu@300 { 118 cpu3: cpu@300 {
109 device_type = "cpu"; 119 device_type = "cpu";
110 compatible = "arm,cort 120 compatible = "arm,cortex-a78ae";
111 reg = <0x0 0x300>; 121 reg = <0x0 0x300>;
112 enable-method = "psci" 122 enable-method = "psci";
113 }; 123 };
114 124
115 cpu4: cpu@10000 { 125 cpu4: cpu@10000 {
116 device_type = "cpu"; 126 device_type = "cpu";
117 compatible = "arm,cort 127 compatible = "arm,cortex-a78ae";
118 reg = <0x0 0x10000>; 128 reg = <0x0 0x10000>;
119 enable-method = "psci" 129 enable-method = "psci";
120 }; 130 };
121 131
122 cpu5: cpu@10100 { 132 cpu5: cpu@10100 {
123 device_type = "cpu"; 133 device_type = "cpu";
124 compatible = "arm,cort 134 compatible = "arm,cortex-a78ae";
125 reg = <0x0 0x10100>; 135 reg = <0x0 0x10100>;
126 enable-method = "psci" 136 enable-method = "psci";
127 }; 137 };
128 138
129 cpu6: cpu@10200 { 139 cpu6: cpu@10200 {
130 device_type = "cpu"; 140 device_type = "cpu";
131 compatible = "arm,cort 141 compatible = "arm,cortex-a78ae";
132 reg = <0x0 0x10200>; 142 reg = <0x0 0x10200>;
133 enable-method = "psci" 143 enable-method = "psci";
134 }; 144 };
135 145
136 cpu7: cpu@10300 { 146 cpu7: cpu@10300 {
137 device_type = "cpu"; 147 device_type = "cpu";
138 compatible = "arm,cort 148 compatible = "arm,cortex-a78ae";
139 reg = <0x0 0x10300>; 149 reg = <0x0 0x10300>;
140 enable-method = "psci" 150 enable-method = "psci";
141 }; 151 };
142 152
143 cpu8: cpu@20000 { 153 cpu8: cpu@20000 {
144 device_type = "cpu"; 154 device_type = "cpu";
145 compatible = "arm,cort 155 compatible = "arm,cortex-a78ae";
146 reg = <0x0 0x20000>; 156 reg = <0x0 0x20000>;
147 enable-method = "psci" 157 enable-method = "psci";
148 }; 158 };
149 159
150 cpu9: cpu@20100 { 160 cpu9: cpu@20100 {
151 device_type = "cpu"; 161 device_type = "cpu";
152 compatible = "arm,cort 162 compatible = "arm,cortex-a78ae";
153 reg = <0x0 0x20100>; 163 reg = <0x0 0x20100>;
154 enable-method = "psci" 164 enable-method = "psci";
155 }; 165 };
156 }; 166 };
157 167
158 psci { 168 psci {
159 compatible = "arm,psci-1.0"; 169 compatible = "arm,psci-1.0";
160 method = "smc"; 170 method = "smc";
161 }; 171 };
162 172
163 soc: soc@0 { 173 soc: soc@0 {
164 compatible = "simple-bus"; 174 compatible = "simple-bus";
165 #address-cells = <1>; 175 #address-cells = <1>;
166 #size-cells = <1>; 176 #size-cells = <1>;
167 ranges = <0x0 0x0 0x0 0x200000 177 ranges = <0x0 0x0 0x0 0x20000000>;
168 178
169 chipid@10000000 { 179 chipid@10000000 {
170 compatible = "samsung, 180 compatible = "samsung,exynosautov920-chipid",
171 "samsung, 181 "samsung,exynos850-chipid";
172 reg = <0x10000000 0x24 182 reg = <0x10000000 0x24>;
173 }; 183 };
174 184
175 gic: interrupt-controller@1040 185 gic: interrupt-controller@10400000 {
176 compatible = "arm,gic- 186 compatible = "arm,gic-v3";
177 #interrupt-cells = <3> 187 #interrupt-cells = <3>;
178 #address-cells = <0>; 188 #address-cells = <0>;
179 interrupt-controller; 189 interrupt-controller;
180 reg = <0x10400000 0x10 190 reg = <0x10400000 0x10000>,
181 <0x10460000 0x14 191 <0x10460000 0x140000>;
182 interrupts = <GIC_PPI 192 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
183 }; 193 };
184 194
185 cmu_peric0: clock-controller@1 <<
186 compatible = "samsung, <<
187 reg = <0x10800000 0x80 <<
188 #clock-cells = <1>; <<
189 <<
190 clocks = <&xtcxo>, <<
191 <&cmu_top DOU <<
192 <&cmu_top DOU <<
193 clock-names = "oscclk" <<
194 "noc", <<
195 "ip"; <<
196 }; <<
197 <<
198 syscon_peric0: syscon@10820000 195 syscon_peric0: syscon@10820000 {
199 compatible = "samsung, 196 compatible = "samsung,exynosautov920-peric0-sysreg",
200 "syscon"; 197 "syscon";
201 reg = <0x10820000 0x20 198 reg = <0x10820000 0x2000>;
202 }; 199 };
203 200
204 pinctrl_peric0: pinctrl@108300 201 pinctrl_peric0: pinctrl@10830000 {
205 compatible = "samsung, 202 compatible = "samsung,exynosautov920-pinctrl";
206 reg = <0x10830000 0x10 203 reg = <0x10830000 0x10000>;
207 interrupts = <GIC_SPI 204 interrupts = <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>;
208 }; 205 };
209 206
210 usi_0: usi@108800c0 { 207 usi_0: usi@108800c0 {
211 compatible = "samsung, 208 compatible = "samsung,exynosautov920-usi",
212 "samsung, 209 "samsung,exynos850-usi";
213 reg = <0x108800c0 0x20 210 reg = <0x108800c0 0x20>;
214 samsung,sysreg = <&sys 211 samsung,sysreg = <&syscon_peric0 0x1000>;
215 samsung,mode = <USI_V2 212 samsung,mode = <USI_V2_UART>;
216 #address-cells = <1>; 213 #address-cells = <1>;
217 #size-cells = <1>; 214 #size-cells = <1>;
218 ranges; 215 ranges;
219 clocks = <&cmu_peric0 !! 216 clocks = <&clock_usi>, <&clock_usi>;
220 <&cmu_peric0 <<
221 clock-names = "pclk", 217 clock-names = "pclk", "ipclk";
222 status = "disabled"; 218 status = "disabled";
223 219
224 serial_0: serial@10880 220 serial_0: serial@10880000 {
225 compatible = " 221 compatible = "samsung,exynosautov920-uart",
226 " 222 "samsung,exynos850-uart";
227 reg = <0x10880 223 reg = <0x10880000 0xc0>;
228 interrupts = < 224 interrupts = <GIC_SPI 764 IRQ_TYPE_LEVEL_HIGH>;
229 pinctrl-names 225 pinctrl-names = "default";
230 pinctrl-0 = <& 226 pinctrl-0 = <&uart0_bus>;
231 clocks = <&cmu !! 227 clocks = <&clock_usi>, <&clock_usi>;
232 <&cmu <<
233 clock-names = 228 clock-names = "uart", "clk_uart_baud0";
234 samsung,uart-f 229 samsung,uart-fifosize = <256>;
235 status = "disa 230 status = "disabled";
236 }; 231 };
237 }; 232 };
238 233
239 pwm: pwm@109b0000 { 234 pwm: pwm@109b0000 {
240 compatible = "samsung, 235 compatible = "samsung,exynosautov920-pwm",
241 "samsung, 236 "samsung,exynos4210-pwm";
242 reg = <0x109b0000 0x10 237 reg = <0x109b0000 0x100>;
243 samsung,pwm-outputs = 238 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
244 #pwm-cells = <3>; 239 #pwm-cells = <3>;
245 clocks = <&xtcxo>; 240 clocks = <&xtcxo>;
246 clock-names = "timers" 241 clock-names = "timers";
247 status = "disabled"; 242 status = "disabled";
248 }; 243 };
249 244
250 syscon_peric1: syscon@10c20000 245 syscon_peric1: syscon@10c20000 {
251 compatible = "samsung, 246 compatible = "samsung,exynosautov920-peric1-sysreg",
252 "syscon"; 247 "syscon";
253 reg = <0x10c20000 0x20 248 reg = <0x10c20000 0x2000>;
254 }; 249 };
255 250
256 pinctrl_peric1: pinctrl@10c300 251 pinctrl_peric1: pinctrl@10c30000 {
257 compatible = "samsung, 252 compatible = "samsung,exynosautov920-pinctrl";
258 reg = <0x10c30000 0x10 253 reg = <0x10c30000 0x10000>;
259 interrupts = <GIC_SPI 254 interrupts = <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>;
260 }; <<
261 <<
262 cmu_top: clock-controller@1100 <<
263 compatible = "samsung, <<
264 reg = <0x11000000 0x80 <<
265 #clock-cells = <1>; <<
266 <<
267 clocks = <&xtcxo>; <<
268 clock-names = "oscclk" <<
269 }; 255 };
270 256
271 pinctrl_alive: pinctrl@1185000 257 pinctrl_alive: pinctrl@11850000 {
272 compatible = "samsung, 258 compatible = "samsung,exynosautov920-pinctrl";
273 reg = <0x11850000 0x10 259 reg = <0x11850000 0x10000>;
274 260
275 wakeup-interrupt-contr 261 wakeup-interrupt-controller {
276 compatible = " 262 compatible = "samsung,exynosautov920-wakeup-eint";
277 }; 263 };
278 }; 264 };
279 265
280 pmu_system_controller: system- 266 pmu_system_controller: system-controller@11860000 {
281 compatible = "samsung, 267 compatible = "samsung,exynosautov920-pmu",
282 "samsung, 268 "samsung,exynos7-pmu","syscon";
283 reg = <0x11860000 0x10 269 reg = <0x11860000 0x10000>;
284 }; 270 };
285 271
286 pinctrl_hsi0: pinctrl@16040000 272 pinctrl_hsi0: pinctrl@16040000 {
287 compatible = "samsung, 273 compatible = "samsung,exynosautov920-pinctrl";
288 reg = <0x16040000 0x10 274 reg = <0x16040000 0x10000>;
289 interrupts = <GIC_SPI 275 interrupts = <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>;
290 }; 276 };
291 277
292 pinctrl_hsi1: pinctrl@16450000 278 pinctrl_hsi1: pinctrl@16450000 {
293 compatible = "samsung, 279 compatible = "samsung,exynosautov920-pinctrl";
294 reg = <0x16450000 0x10 280 reg = <0x16450000 0x10000>;
295 interrupts = <GIC_SPI 281 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>;
296 }; 282 };
297 283
298 pinctrl_hsi2: pinctrl@16c10000 284 pinctrl_hsi2: pinctrl@16c10000 {
299 compatible = "samsung, 285 compatible = "samsung,exynosautov920-pinctrl";
300 reg = <0x16c10000 0x10 286 reg = <0x16c10000 0x10000>;
301 interrupts = <GIC_SPI 287 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
302 }; 288 };
303 289
304 pinctrl_hsi2ufs: pinctrl@16d20 290 pinctrl_hsi2ufs: pinctrl@16d20000 {
305 compatible = "samsung, 291 compatible = "samsung,exynosautov920-pinctrl";
306 reg = <0x16d20000 0x10 292 reg = <0x16d20000 0x10000>;
307 interrupts = <GIC_SPI 293 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
308 }; 294 };
309 295
310 pinctrl_aud: pinctrl@1a460000 296 pinctrl_aud: pinctrl@1a460000 {
311 compatible = "samsung, 297 compatible = "samsung,exynosautov920-pinctrl";
312 reg = <0x1a460000 0x10 298 reg = <0x1a460000 0x10000>;
313 }; 299 };
314 }; 300 };
315 301
316 timer { 302 timer {
317 compatible = "arm,armv8-timer" 303 compatible = "arm,armv8-timer";
318 interrupts = <GIC_PPI 13 IRQ_T 304 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
319 <GIC_PPI 14 IRQ_T 305 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
320 <GIC_PPI 11 IRQ_T 306 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
321 <GIC_PPI 10 IRQ_T 307 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>,
322 <GIC_PPI 12 IRQ_T 308 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>;
323 }; 309 };
324 }; 310 };
325 311
326 #include "exynosautov920-pinctrl.dtsi" 312 #include "exynosautov920-pinctrl.dtsi"
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