1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for NXP LS1028A RDB Board. 3 * Device Tree file for NXP LS1028A RDB Board.
4 * 4 *
5 * Copyright 2018-2021 NXP 5 * Copyright 2018-2021 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi" 12 #include "fsl-ls1028a.dtsi"
13 13
14 / { 14 / {
15 model = "LS1028A RDB Board"; 15 model = "LS1028A RDB Board";
16 compatible = "fsl,ls1028a-rdb", "fsl,l 16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
17 17
18 aliases { 18 aliases {
19 crypto = &crypto; 19 crypto = &crypto;
20 serial0 = &duart0; 20 serial0 = &duart0;
21 serial1 = &duart1; 21 serial1 = &duart1;
22 mmc0 = &esdhc; 22 mmc0 = &esdhc;
23 mmc1 = &esdhc1; 23 mmc1 = &esdhc1;
24 rtc1 = &ftm_alarm1; 24 rtc1 = &ftm_alarm1;
25 spi0 = &fspi; 25 spi0 = &fspi;
26 ethernet0 = &enetc_port0; 26 ethernet0 = &enetc_port0;
27 ethernet1 = &enetc_port2; 27 ethernet1 = &enetc_port2;
28 ethernet2 = &mscc_felix_port0; 28 ethernet2 = &mscc_felix_port0;
29 ethernet3 = &mscc_felix_port1; 29 ethernet3 = &mscc_felix_port1;
30 ethernet4 = &mscc_felix_port2; 30 ethernet4 = &mscc_felix_port2;
31 ethernet5 = &mscc_felix_port3; 31 ethernet5 = &mscc_felix_port3;
32 ethernet6 = &mscc_felix_port4; <<
33 ethernet7 = &mscc_felix_port5; <<
34 ethernet8 = &enetc_port3; <<
35 }; 32 };
36 33
37 chosen { 34 chosen {
38 stdout-path = "serial0:115200n 35 stdout-path = "serial0:115200n8";
39 }; 36 };
40 37
41 memory@80000000 { 38 memory@80000000 {
42 device_type = "memory"; 39 device_type = "memory";
43 reg = <0x0 0x80000000 0x1 0x00 40 reg = <0x0 0x80000000 0x1 0x0000000>;
44 }; 41 };
45 42
46 sys_mclk: clock-mclk { 43 sys_mclk: clock-mclk {
47 compatible = "fixed-clock"; 44 compatible = "fixed-clock";
48 #clock-cells = <0>; 45 #clock-cells = <0>;
49 clock-frequency = <25000000>; 46 clock-frequency = <25000000>;
50 }; 47 };
51 48
52 reg_1p8v: regulator-1p8v { 49 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed" 50 compatible = "regulator-fixed";
54 regulator-name = "1P8V"; 51 regulator-name = "1P8V";
55 regulator-min-microvolt = <180 52 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <180 53 regulator-max-microvolt = <1800000>;
57 regulator-always-on; 54 regulator-always-on;
58 }; 55 };
59 56
60 sb_3v3: regulator-sb3v3 { 57 sb_3v3: regulator-sb3v3 {
61 compatible = "regulator-fixed" 58 compatible = "regulator-fixed";
62 regulator-name = "3v3_vbus"; 59 regulator-name = "3v3_vbus";
63 regulator-min-microvolt = <330 60 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <330 61 regulator-max-microvolt = <3300000>;
65 regulator-boot-on; 62 regulator-boot-on;
66 regulator-always-on; 63 regulator-always-on;
67 }; 64 };
68 65
69 sound { 66 sound {
70 compatible = "simple-audio-car 67 compatible = "simple-audio-card";
71 simple-audio-card,format = "i2 68 simple-audio-card,format = "i2s";
72 simple-audio-card,widgets = 69 simple-audio-card,widgets =
73 "Microphone", "Microph 70 "Microphone", "Microphone Jack",
74 "Headphone", "Headphon 71 "Headphone", "Headphone Jack",
75 "Speaker", "Speaker Ex 72 "Speaker", "Speaker Ext",
76 "Line", "Line In Jack" 73 "Line", "Line In Jack";
77 simple-audio-card,routing = 74 simple-audio-card,routing =
78 "MIC_IN", "Microphone 75 "MIC_IN", "Microphone Jack",
79 "Microphone Jack", "Mi 76 "Microphone Jack", "Mic Bias",
80 "LINE_IN", "Line In Ja 77 "LINE_IN", "Line In Jack",
81 "Headphone Jack", "HP_ 78 "Headphone Jack", "HP_OUT",
82 "Speaker Ext", "LINE_O 79 "Speaker Ext", "LINE_OUT";
83 80
84 simple-audio-card,cpu { 81 simple-audio-card,cpu {
85 sound-dai = <&sai4>; 82 sound-dai = <&sai4>;
86 frame-master; 83 frame-master;
87 bitclock-master; 84 bitclock-master;
88 }; 85 };
89 86
90 simple-audio-card,codec { 87 simple-audio-card,codec {
91 sound-dai = <&sgtl5000 88 sound-dai = <&sgtl5000>;
92 frame-master; 89 frame-master;
93 bitclock-master; 90 bitclock-master;
94 system-clock-frequency 91 system-clock-frequency = <25000000>;
95 }; 92 };
96 }; 93 };
97 }; 94 };
98 95
99 &can0 { 96 &can0 {
100 status = "okay"; 97 status = "okay";
101 98
102 can-transceiver { 99 can-transceiver {
103 max-bitrate = <5000000>; 100 max-bitrate = <5000000>;
104 }; 101 };
105 }; 102 };
106 103
107 &can1 { 104 &can1 {
108 status = "okay"; 105 status = "okay";
109 106
110 can-transceiver { 107 can-transceiver {
111 max-bitrate = <5000000>; 108 max-bitrate = <5000000>;
112 }; 109 };
113 }; 110 };
114 111
115 &duart0 { 112 &duart0 {
116 status = "okay"; 113 status = "okay";
117 }; 114 };
118 115
119 &duart1 { 116 &duart1 {
120 status = "okay"; 117 status = "okay";
121 }; 118 };
122 119
123 &enetc_mdio_pf3 { 120 &enetc_mdio_pf3 {
124 sgmii_phy0: ethernet-phy@2 { 121 sgmii_phy0: ethernet-phy@2 {
125 reg = <0x2>; 122 reg = <0x2>;
126 }; 123 };
127 124
128 /* VSC8514 QSGMII quad PHY */ 125 /* VSC8514 QSGMII quad PHY */
129 qsgmii_phy0: ethernet-phy@10 { 126 qsgmii_phy0: ethernet-phy@10 {
130 reg = <0x10>; 127 reg = <0x10>;
131 }; 128 };
132 129
133 qsgmii_phy1: ethernet-phy@11 { 130 qsgmii_phy1: ethernet-phy@11 {
134 reg = <0x11>; 131 reg = <0x11>;
135 }; 132 };
136 133
137 qsgmii_phy2: ethernet-phy@12 { 134 qsgmii_phy2: ethernet-phy@12 {
138 reg = <0x12>; 135 reg = <0x12>;
139 }; 136 };
140 137
141 qsgmii_phy3: ethernet-phy@13 { 138 qsgmii_phy3: ethernet-phy@13 {
142 reg = <0x13>; 139 reg = <0x13>;
143 }; 140 };
144 }; 141 };
145 142
146 &enetc_port0 { 143 &enetc_port0 {
147 phy-handle = <&sgmii_phy0>; 144 phy-handle = <&sgmii_phy0>;
148 phy-mode = "sgmii"; 145 phy-mode = "sgmii";
149 managed = "in-band-status"; 146 managed = "in-band-status";
150 status = "okay"; 147 status = "okay";
151 }; 148 };
152 149
153 &enetc_port2 { 150 &enetc_port2 {
154 status = "okay"; 151 status = "okay";
155 }; 152 };
156 153
157 &enetc_port3 { <<
158 status = "okay"; <<
159 }; <<
160 <<
161 &esdhc { 154 &esdhc {
162 sd-uhs-sdr104; 155 sd-uhs-sdr104;
163 sd-uhs-sdr50; 156 sd-uhs-sdr50;
164 sd-uhs-sdr25; 157 sd-uhs-sdr25;
165 sd-uhs-sdr12; 158 sd-uhs-sdr12;
166 status = "okay"; 159 status = "okay";
167 }; 160 };
168 161
169 &esdhc1 { 162 &esdhc1 {
170 mmc-hs200-1_8v; 163 mmc-hs200-1_8v;
171 mmc-hs400-1_8v; 164 mmc-hs400-1_8v;
172 bus-width = <8>; 165 bus-width = <8>;
173 status = "okay"; 166 status = "okay";
174 }; 167 };
175 168
176 &fspi { 169 &fspi {
177 status = "okay"; 170 status = "okay";
178 171
179 mt35xu02g0: flash@0 { 172 mt35xu02g0: flash@0 {
180 compatible = "jedec,spi-nor"; 173 compatible = "jedec,spi-nor";
181 #address-cells = <1>; 174 #address-cells = <1>;
182 #size-cells = <1>; 175 #size-cells = <1>;
183 spi-max-frequency = <50000000> 176 spi-max-frequency = <50000000>;
184 /* The following setting enabl 177 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
185 spi-rx-bus-width = <8>; /* 8 S 178 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
186 spi-tx-bus-width = <1>; /* 1 S 179 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
187 reg = <0>; 180 reg = <0>;
188 }; 181 };
189 }; 182 };
190 183
191 &ftm_alarm1 { 184 &ftm_alarm1 {
192 status = "okay"; 185 status = "okay";
193 }; 186 };
194 187
195 &i2c0 { 188 &i2c0 {
196 status = "okay"; 189 status = "okay";
197 190
198 i2c-mux@77 { 191 i2c-mux@77 {
199 compatible = "nxp,pca9847"; 192 compatible = "nxp,pca9847";
200 reg = <0x77>; 193 reg = <0x77>;
201 #address-cells = <1>; 194 #address-cells = <1>;
202 #size-cells = <0>; 195 #size-cells = <0>;
203 196
204 i2c@0 { <<
205 #address-cells = <1>; <<
206 #size-cells = <0>; <<
207 reg = <0x0>; <<
208 <<
209 /* Atmel AT24C512C-XHD <<
210 eeprom@50 { <<
211 compatible = " <<
212 reg = <0x50>; <<
213 #address-cells <<
214 #size-cells = <<
215 }; <<
216 <<
217 /* AT24C04C 512-byte D <<
218 /* Documentation says <<
219 eeprom@52 { <<
220 compatible = " <<
221 reg = <0x52>; <<
222 #address-cells <<
223 #size-cells = <<
224 }; <<
225 <<
226 /* Atmel AT24C02C-XHMÂ <<
227 eeprom@57 { <<
228 compatible = " <<
229 reg = <0x57>; <<
230 #address-cells <<
231 #size-cells = <<
232 }; <<
233 }; <<
234 <<
235 i2c@1 { 197 i2c@1 {
236 #address-cells = <1>; 198 #address-cells = <1>;
237 #size-cells = <0>; 199 #size-cells = <0>;
238 reg = <0x1>; 200 reg = <0x1>;
239 201
240 sgtl5000: audio-codec@ 202 sgtl5000: audio-codec@a {
241 #sound-dai-cel 203 #sound-dai-cells = <0>;
242 compatible = " 204 compatible = "fsl,sgtl5000";
243 reg = <0xa>; 205 reg = <0xa>;
244 VDDA-supply = 206 VDDA-supply = <®_1p8v>;
245 VDDIO-supply = 207 VDDIO-supply = <®_1p8v>;
246 clocks = <&sys 208 clocks = <&sys_mclk>;
247 sclk-strength 209 sclk-strength = <3>;
248 }; 210 };
249 }; 211 };
250 212
251 i2c@2 { 213 i2c@2 {
252 #address-cells = <1>; 214 #address-cells = <1>;
253 #size-cells = <0>; 215 #size-cells = <0>;
254 reg = <0x02>; 216 reg = <0x02>;
255 217
256 current-monitor@40 { 218 current-monitor@40 {
257 compatible = " 219 compatible = "ti,ina220";
258 reg = <0x40>; 220 reg = <0x40>;
259 shunt-resistor 221 shunt-resistor = <500>;
260 }; 222 };
261 }; 223 };
262 224
263 i2c@3 { 225 i2c@3 {
264 #address-cells = <1>; 226 #address-cells = <1>;
265 #size-cells = <0>; 227 #size-cells = <0>;
266 reg = <0x3>; 228 reg = <0x3>;
267 229
268 temperature-sensor@4c 230 temperature-sensor@4c {
269 compatible = " 231 compatible = "nxp,sa56004";
270 reg = <0x4c>; 232 reg = <0x4c>;
271 vcc-supply = < 233 vcc-supply = <&sb_3v3>;
272 }; 234 };
273 235
274 rtc@51 { 236 rtc@51 {
275 compatible = " 237 compatible = "nxp,pcf2129";
276 reg = <0x51>; 238 reg = <0x51>;
277 }; 239 };
278 }; 240 };
279 }; 241 };
280 }; 242 };
281 243
282 &mscc_felix { 244 &mscc_felix {
283 status = "okay"; 245 status = "okay";
284 }; 246 };
285 247
286 &mscc_felix_port0 { 248 &mscc_felix_port0 {
287 label = "swp0"; 249 label = "swp0";
288 managed = "in-band-status"; 250 managed = "in-band-status";
289 phy-handle = <&qsgmii_phy0>; 251 phy-handle = <&qsgmii_phy0>;
290 phy-mode = "qsgmii"; 252 phy-mode = "qsgmii";
291 status = "okay"; 253 status = "okay";
292 }; 254 };
293 255
294 &mscc_felix_port1 { 256 &mscc_felix_port1 {
295 label = "swp1"; 257 label = "swp1";
296 managed = "in-band-status"; 258 managed = "in-band-status";
297 phy-handle = <&qsgmii_phy1>; 259 phy-handle = <&qsgmii_phy1>;
298 phy-mode = "qsgmii"; 260 phy-mode = "qsgmii";
299 status = "okay"; 261 status = "okay";
300 }; 262 };
301 263
302 &mscc_felix_port2 { 264 &mscc_felix_port2 {
303 label = "swp2"; 265 label = "swp2";
304 managed = "in-band-status"; 266 managed = "in-band-status";
305 phy-handle = <&qsgmii_phy2>; 267 phy-handle = <&qsgmii_phy2>;
306 phy-mode = "qsgmii"; 268 phy-mode = "qsgmii";
307 status = "okay"; 269 status = "okay";
308 }; 270 };
309 271
310 &mscc_felix_port3 { 272 &mscc_felix_port3 {
311 label = "swp3"; 273 label = "swp3";
312 managed = "in-band-status"; 274 managed = "in-band-status";
313 phy-handle = <&qsgmii_phy3>; 275 phy-handle = <&qsgmii_phy3>;
314 phy-mode = "qsgmii"; 276 phy-mode = "qsgmii";
315 status = "okay"; 277 status = "okay";
316 }; 278 };
317 279
318 &mscc_felix_port4 { 280 &mscc_felix_port4 {
319 status = "okay"; !! 281 ethernet = <&enetc_port2>;
320 }; <<
321 <<
322 &mscc_felix_port5 { <<
323 status = "okay"; 282 status = "okay";
324 }; 283 };
325 284
326 &optee { 285 &optee {
327 status = "okay"; 286 status = "okay";
328 }; 287 };
329 288
330 &pwm0 { 289 &pwm0 {
331 status = "okay"; 290 status = "okay";
332 }; 291 };
333 292
334 &sai4 { 293 &sai4 {
335 status = "okay"; 294 status = "okay";
336 }; 295 };
337 296
338 &sata { 297 &sata {
339 status = "okay"; 298 status = "okay";
340 }; 299 };
341 300
342 &usb0 { 301 &usb0 {
343 dr_mode = "host"; 302 dr_mode = "host";
344 status = "okay"; 303 status = "okay";
345 }; 304 };
346 305
347 &usb1 { 306 &usb1 {
348 status = "okay"; 307 status = "okay";
349 }; 308 };
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