1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree file for NXP LS1028A RDB Board. 3 * Device Tree file for NXP LS1028A RDB Board.
4 * 4 *
5 * Copyright 2018-2021 NXP 5 * Copyright 2018-2021 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 10
11 /dts-v1/; 11 /dts-v1/;
12 #include "fsl-ls1028a.dtsi" 12 #include "fsl-ls1028a.dtsi"
13 13
14 / { 14 / {
15 model = "LS1028A RDB Board"; 15 model = "LS1028A RDB Board";
16 compatible = "fsl,ls1028a-rdb", "fsl,l 16 compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
17 17
18 aliases { 18 aliases {
19 crypto = &crypto; 19 crypto = &crypto;
20 serial0 = &duart0; 20 serial0 = &duart0;
21 serial1 = &duart1; 21 serial1 = &duart1;
22 mmc0 = &esdhc; 22 mmc0 = &esdhc;
23 mmc1 = &esdhc1; 23 mmc1 = &esdhc1;
24 rtc1 = &ftm_alarm1; 24 rtc1 = &ftm_alarm1;
25 spi0 = &fspi; 25 spi0 = &fspi;
26 ethernet0 = &enetc_port0; 26 ethernet0 = &enetc_port0;
27 ethernet1 = &enetc_port2; 27 ethernet1 = &enetc_port2;
28 ethernet2 = &mscc_felix_port0; 28 ethernet2 = &mscc_felix_port0;
29 ethernet3 = &mscc_felix_port1; 29 ethernet3 = &mscc_felix_port1;
30 ethernet4 = &mscc_felix_port2; 30 ethernet4 = &mscc_felix_port2;
31 ethernet5 = &mscc_felix_port3; 31 ethernet5 = &mscc_felix_port3;
32 ethernet6 = &mscc_felix_port4; 32 ethernet6 = &mscc_felix_port4;
33 ethernet7 = &mscc_felix_port5; 33 ethernet7 = &mscc_felix_port5;
34 ethernet8 = &enetc_port3; 34 ethernet8 = &enetc_port3;
35 }; 35 };
36 36
37 chosen { 37 chosen {
38 stdout-path = "serial0:115200n 38 stdout-path = "serial0:115200n8";
39 }; 39 };
40 40
41 memory@80000000 { 41 memory@80000000 {
42 device_type = "memory"; 42 device_type = "memory";
43 reg = <0x0 0x80000000 0x1 0x00 43 reg = <0x0 0x80000000 0x1 0x0000000>;
44 }; 44 };
45 45
46 sys_mclk: clock-mclk { 46 sys_mclk: clock-mclk {
47 compatible = "fixed-clock"; 47 compatible = "fixed-clock";
48 #clock-cells = <0>; 48 #clock-cells = <0>;
49 clock-frequency = <25000000>; 49 clock-frequency = <25000000>;
50 }; 50 };
51 51
52 reg_1p8v: regulator-1p8v { 52 reg_1p8v: regulator-1p8v {
53 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
54 regulator-name = "1P8V"; 54 regulator-name = "1P8V";
55 regulator-min-microvolt = <180 55 regulator-min-microvolt = <1800000>;
56 regulator-max-microvolt = <180 56 regulator-max-microvolt = <1800000>;
57 regulator-always-on; 57 regulator-always-on;
58 }; 58 };
59 59
60 sb_3v3: regulator-sb3v3 { 60 sb_3v3: regulator-sb3v3 {
61 compatible = "regulator-fixed" 61 compatible = "regulator-fixed";
62 regulator-name = "3v3_vbus"; 62 regulator-name = "3v3_vbus";
63 regulator-min-microvolt = <330 63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <330 64 regulator-max-microvolt = <3300000>;
65 regulator-boot-on; 65 regulator-boot-on;
66 regulator-always-on; 66 regulator-always-on;
67 }; 67 };
68 68
69 sound { 69 sound {
70 compatible = "simple-audio-car 70 compatible = "simple-audio-card";
71 simple-audio-card,format = "i2 71 simple-audio-card,format = "i2s";
72 simple-audio-card,widgets = 72 simple-audio-card,widgets =
73 "Microphone", "Microph 73 "Microphone", "Microphone Jack",
74 "Headphone", "Headphon 74 "Headphone", "Headphone Jack",
75 "Speaker", "Speaker Ex 75 "Speaker", "Speaker Ext",
76 "Line", "Line In Jack" 76 "Line", "Line In Jack";
77 simple-audio-card,routing = 77 simple-audio-card,routing =
78 "MIC_IN", "Microphone 78 "MIC_IN", "Microphone Jack",
79 "Microphone Jack", "Mi 79 "Microphone Jack", "Mic Bias",
80 "LINE_IN", "Line In Ja 80 "LINE_IN", "Line In Jack",
81 "Headphone Jack", "HP_ 81 "Headphone Jack", "HP_OUT",
82 "Speaker Ext", "LINE_O 82 "Speaker Ext", "LINE_OUT";
83 83
84 simple-audio-card,cpu { 84 simple-audio-card,cpu {
85 sound-dai = <&sai4>; 85 sound-dai = <&sai4>;
86 frame-master; 86 frame-master;
87 bitclock-master; 87 bitclock-master;
88 }; 88 };
89 89
90 simple-audio-card,codec { 90 simple-audio-card,codec {
91 sound-dai = <&sgtl5000 91 sound-dai = <&sgtl5000>;
92 frame-master; 92 frame-master;
93 bitclock-master; 93 bitclock-master;
94 system-clock-frequency 94 system-clock-frequency = <25000000>;
95 }; 95 };
96 }; 96 };
97 }; 97 };
98 98
99 &can0 { 99 &can0 {
100 status = "okay"; 100 status = "okay";
101 101
102 can-transceiver { 102 can-transceiver {
103 max-bitrate = <5000000>; 103 max-bitrate = <5000000>;
104 }; 104 };
105 }; 105 };
106 106
107 &can1 { 107 &can1 {
108 status = "okay"; 108 status = "okay";
109 109
110 can-transceiver { 110 can-transceiver {
111 max-bitrate = <5000000>; 111 max-bitrate = <5000000>;
112 }; 112 };
113 }; 113 };
114 114
115 &duart0 { 115 &duart0 {
116 status = "okay"; 116 status = "okay";
117 }; 117 };
118 118
119 &duart1 { 119 &duart1 {
120 status = "okay"; 120 status = "okay";
121 }; 121 };
122 122
123 &enetc_mdio_pf3 { 123 &enetc_mdio_pf3 {
124 sgmii_phy0: ethernet-phy@2 { 124 sgmii_phy0: ethernet-phy@2 {
125 reg = <0x2>; 125 reg = <0x2>;
126 }; 126 };
127 127
128 /* VSC8514 QSGMII quad PHY */ 128 /* VSC8514 QSGMII quad PHY */
129 qsgmii_phy0: ethernet-phy@10 { 129 qsgmii_phy0: ethernet-phy@10 {
130 reg = <0x10>; 130 reg = <0x10>;
131 }; 131 };
132 132
133 qsgmii_phy1: ethernet-phy@11 { 133 qsgmii_phy1: ethernet-phy@11 {
134 reg = <0x11>; 134 reg = <0x11>;
135 }; 135 };
136 136
137 qsgmii_phy2: ethernet-phy@12 { 137 qsgmii_phy2: ethernet-phy@12 {
138 reg = <0x12>; 138 reg = <0x12>;
139 }; 139 };
140 140
141 qsgmii_phy3: ethernet-phy@13 { 141 qsgmii_phy3: ethernet-phy@13 {
142 reg = <0x13>; 142 reg = <0x13>;
143 }; 143 };
144 }; 144 };
145 145
146 &enetc_port0 { 146 &enetc_port0 {
147 phy-handle = <&sgmii_phy0>; 147 phy-handle = <&sgmii_phy0>;
148 phy-mode = "sgmii"; 148 phy-mode = "sgmii";
149 managed = "in-band-status"; 149 managed = "in-band-status";
150 status = "okay"; 150 status = "okay";
151 }; 151 };
152 152
153 &enetc_port2 { 153 &enetc_port2 {
154 status = "okay"; 154 status = "okay";
155 }; 155 };
156 156
157 &enetc_port3 { 157 &enetc_port3 {
158 status = "okay"; 158 status = "okay";
159 }; 159 };
160 160
161 &esdhc { 161 &esdhc {
162 sd-uhs-sdr104; 162 sd-uhs-sdr104;
163 sd-uhs-sdr50; 163 sd-uhs-sdr50;
164 sd-uhs-sdr25; 164 sd-uhs-sdr25;
165 sd-uhs-sdr12; 165 sd-uhs-sdr12;
166 status = "okay"; 166 status = "okay";
167 }; 167 };
168 168
169 &esdhc1 { 169 &esdhc1 {
170 mmc-hs200-1_8v; 170 mmc-hs200-1_8v;
171 mmc-hs400-1_8v; 171 mmc-hs400-1_8v;
172 bus-width = <8>; 172 bus-width = <8>;
173 status = "okay"; 173 status = "okay";
174 }; 174 };
175 175
176 &fspi { 176 &fspi {
177 status = "okay"; 177 status = "okay";
178 178
179 mt35xu02g0: flash@0 { 179 mt35xu02g0: flash@0 {
180 compatible = "jedec,spi-nor"; 180 compatible = "jedec,spi-nor";
181 #address-cells = <1>; 181 #address-cells = <1>;
182 #size-cells = <1>; 182 #size-cells = <1>;
183 spi-max-frequency = <50000000> 183 spi-max-frequency = <50000000>;
184 /* The following setting enabl 184 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
185 spi-rx-bus-width = <8>; /* 8 S 185 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
186 spi-tx-bus-width = <1>; /* 1 S 186 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
187 reg = <0>; 187 reg = <0>;
188 }; 188 };
189 }; 189 };
190 190
191 &ftm_alarm1 { 191 &ftm_alarm1 {
192 status = "okay"; 192 status = "okay";
193 }; 193 };
194 194
195 &i2c0 { 195 &i2c0 {
196 status = "okay"; 196 status = "okay";
197 197
198 i2c-mux@77 { 198 i2c-mux@77 {
199 compatible = "nxp,pca9847"; 199 compatible = "nxp,pca9847";
200 reg = <0x77>; 200 reg = <0x77>;
201 #address-cells = <1>; 201 #address-cells = <1>;
202 #size-cells = <0>; 202 #size-cells = <0>;
203 203
204 i2c@0 { <<
205 #address-cells = <1>; <<
206 #size-cells = <0>; <<
207 reg = <0x0>; <<
208 <<
209 /* Atmel AT24C512C-XHD <<
210 eeprom@50 { <<
211 compatible = " <<
212 reg = <0x50>; <<
213 #address-cells <<
214 #size-cells = <<
215 }; <<
216 <<
217 /* AT24C04C 512-byte D <<
218 /* Documentation says <<
219 eeprom@52 { <<
220 compatible = " <<
221 reg = <0x52>; <<
222 #address-cells <<
223 #size-cells = <<
224 }; <<
225 <<
226 /* Atmel AT24C02C-XHMÂ <<
227 eeprom@57 { <<
228 compatible = " <<
229 reg = <0x57>; <<
230 #address-cells <<
231 #size-cells = <<
232 }; <<
233 }; <<
234 <<
235 i2c@1 { 204 i2c@1 {
236 #address-cells = <1>; 205 #address-cells = <1>;
237 #size-cells = <0>; 206 #size-cells = <0>;
238 reg = <0x1>; 207 reg = <0x1>;
239 208
240 sgtl5000: audio-codec@ 209 sgtl5000: audio-codec@a {
241 #sound-dai-cel 210 #sound-dai-cells = <0>;
242 compatible = " 211 compatible = "fsl,sgtl5000";
243 reg = <0xa>; 212 reg = <0xa>;
244 VDDA-supply = 213 VDDA-supply = <®_1p8v>;
245 VDDIO-supply = 214 VDDIO-supply = <®_1p8v>;
246 clocks = <&sys 215 clocks = <&sys_mclk>;
247 sclk-strength 216 sclk-strength = <3>;
248 }; 217 };
249 }; 218 };
250 219
251 i2c@2 { 220 i2c@2 {
252 #address-cells = <1>; 221 #address-cells = <1>;
253 #size-cells = <0>; 222 #size-cells = <0>;
254 reg = <0x02>; 223 reg = <0x02>;
255 224
256 current-monitor@40 { 225 current-monitor@40 {
257 compatible = " 226 compatible = "ti,ina220";
258 reg = <0x40>; 227 reg = <0x40>;
259 shunt-resistor 228 shunt-resistor = <500>;
260 }; 229 };
261 }; 230 };
262 231
263 i2c@3 { 232 i2c@3 {
264 #address-cells = <1>; 233 #address-cells = <1>;
265 #size-cells = <0>; 234 #size-cells = <0>;
266 reg = <0x3>; 235 reg = <0x3>;
267 236
268 temperature-sensor@4c 237 temperature-sensor@4c {
269 compatible = " 238 compatible = "nxp,sa56004";
270 reg = <0x4c>; 239 reg = <0x4c>;
271 vcc-supply = < 240 vcc-supply = <&sb_3v3>;
272 }; 241 };
273 242
274 rtc@51 { 243 rtc@51 {
275 compatible = " 244 compatible = "nxp,pcf2129";
276 reg = <0x51>; 245 reg = <0x51>;
277 }; 246 };
278 }; 247 };
279 }; 248 };
280 }; 249 };
281 250
282 &mscc_felix { 251 &mscc_felix {
283 status = "okay"; 252 status = "okay";
284 }; 253 };
285 254
286 &mscc_felix_port0 { 255 &mscc_felix_port0 {
287 label = "swp0"; 256 label = "swp0";
288 managed = "in-band-status"; 257 managed = "in-band-status";
289 phy-handle = <&qsgmii_phy0>; 258 phy-handle = <&qsgmii_phy0>;
290 phy-mode = "qsgmii"; 259 phy-mode = "qsgmii";
291 status = "okay"; 260 status = "okay";
292 }; 261 };
293 262
294 &mscc_felix_port1 { 263 &mscc_felix_port1 {
295 label = "swp1"; 264 label = "swp1";
296 managed = "in-band-status"; 265 managed = "in-band-status";
297 phy-handle = <&qsgmii_phy1>; 266 phy-handle = <&qsgmii_phy1>;
298 phy-mode = "qsgmii"; 267 phy-mode = "qsgmii";
299 status = "okay"; 268 status = "okay";
300 }; 269 };
301 270
302 &mscc_felix_port2 { 271 &mscc_felix_port2 {
303 label = "swp2"; 272 label = "swp2";
304 managed = "in-band-status"; 273 managed = "in-band-status";
305 phy-handle = <&qsgmii_phy2>; 274 phy-handle = <&qsgmii_phy2>;
306 phy-mode = "qsgmii"; 275 phy-mode = "qsgmii";
307 status = "okay"; 276 status = "okay";
308 }; 277 };
309 278
310 &mscc_felix_port3 { 279 &mscc_felix_port3 {
311 label = "swp3"; 280 label = "swp3";
312 managed = "in-band-status"; 281 managed = "in-band-status";
313 phy-handle = <&qsgmii_phy3>; 282 phy-handle = <&qsgmii_phy3>;
314 phy-mode = "qsgmii"; 283 phy-mode = "qsgmii";
315 status = "okay"; 284 status = "okay";
316 }; 285 };
317 286
318 &mscc_felix_port4 { 287 &mscc_felix_port4 {
319 status = "okay"; 288 status = "okay";
320 }; 289 };
321 290
322 &mscc_felix_port5 { 291 &mscc_felix_port5 {
323 status = "okay"; 292 status = "okay";
324 }; 293 };
325 294
326 &optee { 295 &optee {
327 status = "okay"; 296 status = "okay";
328 }; 297 };
329 298
330 &pwm0 { 299 &pwm0 {
331 status = "okay"; 300 status = "okay";
332 }; 301 };
333 302
334 &sai4 { 303 &sai4 {
335 status = "okay"; 304 status = "okay";
336 }; 305 };
337 306
338 &sata { 307 &sata {
339 status = "okay"; 308 status = "okay";
340 }; 309 };
341 310
342 &usb0 { 311 &usb0 {
343 dr_mode = "host"; 312 dr_mode = "host";
344 status = "okay"; 313 status = "okay";
345 }; 314 };
346 315
347 &usb1 { 316 &usb1 {
348 status = "okay"; 317 status = "okay";
349 }; 318 };
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