1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Device Tree Include file for Freescale Laye 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * 3 *
5 * Copyright 2014-2015 Freescale Semiconductor 4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP <<
7 * 5 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 6 * Mingkai Hu <Mingkai.hu@freescale.com>
>> 7 *
>> 8 * This file is dual-licensed: you can use it either under the terms
>> 9 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 10 * licensing only applies to this file, and not this project as a
>> 11 * whole.
>> 12 *
>> 13 * a) This library is free software; you can redistribute it and/or
>> 14 * modify it under the terms of the GNU General Public License as
>> 15 * published by the Free Software Foundation; either version 2 of the
>> 16 * License, or (at your option) any later version.
>> 17 *
>> 18 * This library is distributed in the hope that it will be useful,
>> 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 21 * GNU General Public License for more details.
>> 22 *
>> 23 * Or, alternatively,
>> 24 *
>> 25 * b) Permission is hereby granted, free of charge, to any person
>> 26 * obtaining a copy of this software and associated documentation
>> 27 * files (the "Software"), to deal in the Software without
>> 28 * restriction, including without limitation the rights to use,
>> 29 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 30 * sell copies of the Software, and to permit persons to whom the
>> 31 * Software is furnished to do so, subject to the following
>> 32 * conditions:
>> 33 *
>> 34 * The above copyright notice and this permission notice shall be
>> 35 * included in all copies or substantial portions of the Software.
>> 36 *
>> 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 44 * OTHER DEALINGS IN THE SOFTWARE.
9 */ 45 */
10 46
11 /dts-v1/; 47 /dts-v1/;
12 #include "fsl-ls1043a.dtsi" 48 #include "fsl-ls1043a.dtsi"
13 49
14 / { 50 / {
15 model = "LS1043A QDS Board"; 51 model = "LS1043A QDS Board";
16 compatible = "fsl,ls1043a-qds", "fsl,l 52 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
17 53
18 aliases { 54 aliases {
19 gpio0 = &gpio1; 55 gpio0 = &gpio1;
20 gpio1 = &gpio2; 56 gpio1 = &gpio2;
21 gpio2 = &gpio3; 57 gpio2 = &gpio3;
22 gpio3 = &gpio4; 58 gpio3 = &gpio4;
23 serial0 = &duart0; 59 serial0 = &duart0;
24 serial1 = &duart1; 60 serial1 = &duart1;
25 serial2 = &duart2; 61 serial2 = &duart2;
26 serial3 = &duart3; 62 serial3 = &duart3;
27 sgmii-riser-s1-p1 = &sgmii_phy <<
28 sgmii-riser-s2-p1 = &sgmii_phy <<
29 sgmii-riser-s3-p1 = &sgmii_phy <<
30 sgmii-riser-s4-p1 = &sgmii_phy <<
31 qsgmii-s1-p1 = &qsgmii_phy_s1_ <<
32 qsgmii-s1-p2 = &qsgmii_phy_s1_ <<
33 qsgmii-s1-p3 = &qsgmii_phy_s1_ <<
34 qsgmii-s1-p4 = &qsgmii_phy_s1_ <<
35 qsgmii-s2-p1 = &qsgmii_phy_s2_ <<
36 qsgmii-s2-p2 = &qsgmii_phy_s2_ <<
37 qsgmii-s2-p3 = &qsgmii_phy_s2_ <<
38 qsgmii-s2-p4 = &qsgmii_phy_s2_ <<
39 emi1-slot1 = &ls1043mdio_s1; <<
40 emi1-slot2 = &ls1043mdio_s2; <<
41 emi1-slot3 = &ls1043mdio_s3; <<
42 emi1-slot4 = &ls1043mdio_s4; <<
43 }; 63 };
44 64
45 chosen { 65 chosen {
46 stdout-path = "serial0:115200n 66 stdout-path = "serial0:115200n8";
47 }; 67 };
48 }; 68 };
49 69
50 &duart0 { 70 &duart0 {
51 status = "okay"; 71 status = "okay";
52 }; 72 };
53 73
54 &duart1 { 74 &duart1 {
55 status = "okay"; 75 status = "okay";
56 }; 76 };
57 77
58 &ifc { 78 &ifc {
59 #address-cells = <2>; 79 #address-cells = <2>;
60 #size-cells = <1>; 80 #size-cells = <1>;
61 /* NOR, NAND Flashes and FPGA on board 81 /* NOR, NAND Flashes and FPGA on board */
62 ranges = <0x0 0x0 0x0 0x60000000 0x080 82 ranges = <0x0 0x0 0x0 0x60000000 0x08000000
63 0x1 0x0 0x0 0x7e800000 0x000 83 0x1 0x0 0x0 0x7e800000 0x00010000
64 0x2 0x0 0x0 0x7fb00000 0x000 84 0x2 0x0 0x0 0x7fb00000 0x00000100>;
65 status = "okay"; 85 status = "okay";
66 86
67 flash@0,0 { !! 87 nor@0,0 {
68 compatible = "cfi-flash"; 88 compatible = "cfi-flash";
69 reg = <0x0 0x0 0x8000000>; 89 reg = <0x0 0x0 0x8000000>;
70 big-endian; <<
71 bank-width = <2>; 90 bank-width = <2>;
72 device-width = <1>; 91 device-width = <1>;
73 }; 92 };
74 93
75 nand@1,0 { 94 nand@1,0 {
76 compatible = "fsl,ifc-nand"; 95 compatible = "fsl,ifc-nand";
77 reg = <0x1 0x0 0x10000>; 96 reg = <0x1 0x0 0x10000>;
78 }; 97 };
79 98
80 fpga: board-control@2,0 { 99 fpga: board-control@2,0 {
81 compatible = "fsl,ls1043aqds-f !! 100 compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis";
82 reg = <0x2 0x0 0x0000100>; 101 reg = <0x2 0x0 0x0000100>;
83 #address-cells = <1>; <<
84 #size-cells = <1>; <<
85 ranges = <0 2 0 0x100>; <<
86 }; 102 };
87 }; 103 };
88 104
89 &i2c0 { 105 &i2c0 {
90 status = "okay"; 106 status = "okay";
91 107
92 i2c-mux@77 { !! 108 pca9547@77 {
93 compatible = "nxp,pca9547"; 109 compatible = "nxp,pca9547";
94 reg = <0x77>; 110 reg = <0x77>;
95 #address-cells = <1>; 111 #address-cells = <1>;
96 #size-cells = <0>; 112 #size-cells = <0>;
97 113
98 i2c@0 { 114 i2c@0 {
99 #address-cells = <1>; 115 #address-cells = <1>;
100 #size-cells = <0>; 116 #size-cells = <0>;
101 reg = <0x0>; 117 reg = <0x0>;
102 118
103 rtc@68 { 119 rtc@68 {
104 compatible = " 120 compatible = "dallas,ds3232";
105 reg = <0x68>; 121 reg = <0x68>;
106 /* IRQ10_B */ 122 /* IRQ10_B */
107 interrupts = < 123 interrupts = <0 150 0x4>;
108 }; 124 };
109 }; 125 };
110 126
111 i2c@2 { 127 i2c@2 {
112 #address-cells = <1>; 128 #address-cells = <1>;
113 #size-cells = <0>; 129 #size-cells = <0>;
114 reg = <0x2>; 130 reg = <0x2>;
115 131
116 ina220@40 { 132 ina220@40 {
117 compatible = " 133 compatible = "ti,ina220";
118 reg = <0x40>; 134 reg = <0x40>;
119 shunt-resistor 135 shunt-resistor = <1000>;
120 }; 136 };
121 137
122 ina220@41 { 138 ina220@41 {
123 compatible = " 139 compatible = "ti,ina220";
124 reg = <0x41>; 140 reg = <0x41>;
125 shunt-resistor 141 shunt-resistor = <1000>;
126 }; 142 };
127 }; 143 };
128 144
129 i2c@3 { 145 i2c@3 {
130 #address-cells = <1>; 146 #address-cells = <1>;
131 #size-cells = <0>; 147 #size-cells = <0>;
132 reg = <0x3>; 148 reg = <0x3>;
133 149
134 eeprom@56 { 150 eeprom@56 {
135 compatible = " 151 compatible = "atmel,24c512";
136 reg = <0x56>; 152 reg = <0x56>;
137 }; 153 };
138 154
139 eeprom@57 { 155 eeprom@57 {
140 compatible = " 156 compatible = "atmel,24c512";
141 reg = <0x57>; 157 reg = <0x57>;
142 }; 158 };
143 159
144 temp-sensor@4c { 160 temp-sensor@4c {
145 compatible = " 161 compatible = "adi,adt7461a";
146 reg = <0x4c>; 162 reg = <0x4c>;
147 }; 163 };
148 }; 164 };
149 }; 165 };
150 }; 166 };
151 167
152 &lpuart0 { 168 &lpuart0 {
153 status = "okay"; 169 status = "okay";
154 }; 170 };
155 171
156 &qspi { 172 &qspi {
>> 173 bus-num = <0>;
157 status = "okay"; 174 status = "okay";
158 175
159 qflash0: flash@0 { !! 176 qflash0: s25fl128s@0 {
160 compatible = "spansion,m25p80" 177 compatible = "spansion,m25p80";
161 #address-cells = <1>; 178 #address-cells = <1>;
162 #size-cells = <1>; 179 #size-cells = <1>;
163 spi-max-frequency = <20000000> 180 spi-max-frequency = <20000000>;
164 spi-rx-bus-width = <4>; <<
165 spi-tx-bus-width = <4>; <<
166 reg = <0>; 181 reg = <0>;
167 }; 182 };
168 }; 183 };
169 184
170 &usb0 { <<
171 status = "okay"; <<
172 }; <<
173 <<
174 #include "fsl-ls1043-post.dtsi" 185 #include "fsl-ls1043-post.dtsi"
175 <<
176 &fman0 { <<
177 ethernet@e0000 { <<
178 phy-handle = <&qsgmii_phy_s2_p <<
179 phy-connection-type = "sgmii"; <<
180 }; <<
181 <<
182 ethernet@e2000 { <<
183 phy-handle = <&qsgmii_phy_s2_p <<
184 phy-connection-type = "sgmii"; <<
185 }; <<
186 <<
187 ethernet@e4000 { <<
188 phy-handle = <&rgmii_phy1>; <<
189 phy-connection-type = "rgmii"; <<
190 }; <<
191 <<
192 ethernet@e6000 { <<
193 phy-handle = <&rgmii_phy2>; <<
194 phy-connection-type = "rgmii"; <<
195 }; <<
196 <<
197 ethernet@e8000 { <<
198 phy-handle = <&qsgmii_phy_s2_p <<
199 phy-connection-type = "sgmii"; <<
200 }; <<
201 <<
202 ethernet@ea000 { <<
203 phy-handle = <&qsgmii_phy_s2_p <<
204 phy-connection-type = "sgmii"; <<
205 }; <<
206 <<
207 ethernet@f0000 { /* DTSEC9/10GEC1 */ <<
208 fixed-link = <1 1 10000 0 0>; <<
209 phy-connection-type = "xgmii"; <<
210 }; <<
211 }; <<
212 <<
213 &fpga { <<
214 mdio-mux@54 { <<
215 compatible = "mdio-mux-mmioreg <<
216 mdio-parent-bus = <&mdio0>; <<
217 #address-cells = <1>; <<
218 #size-cells = <0>; <<
219 reg = <0x54 1>; /* BRDCFG4 <<
220 mux-mask = <0xe0>; /* EMI1 */ <<
221 <<
222 /* On-board RGMII1 PHY */ <<
223 ls1043mdio0: mdio@0 { <<
224 reg = <0>; <<
225 #address-cells = <1>; <<
226 #size-cells = <0>; <<
227 <<
228 rgmii_phy1: ethernet-p <<
229 reg = <0x1>; <<
230 }; <<
231 }; <<
232 <<
233 /* On-board RGMII2 PHY */ <<
234 ls1043mdio1: mdio@20 { <<
235 reg = <0x20>; <<
236 #address-cells = <1>; <<
237 #size-cells = <0>; <<
238 <<
239 rgmii_phy2: ethernet-p <<
240 reg = <0x2>; <<
241 }; <<
242 }; <<
243 <<
244 /* Slot 1 */ <<
245 ls1043mdio_s1: mdio@40 { <<
246 reg = <0x40>; <<
247 #address-cells = <1>; <<
248 #size-cells = <0>; <<
249 status = "disabled"; <<
250 <<
251 qsgmii_phy_s1_p1: ethe <<
252 reg = <0x4>; <<
253 }; <<
254 <<
255 qsgmii_phy_s1_p2: ethe <<
256 reg = <0x5>; <<
257 }; <<
258 <<
259 qsgmii_phy_s1_p3: ethe <<
260 reg = <0x6>; <<
261 }; <<
262 <<
263 qsgmii_phy_s1_p4: ethe <<
264 reg = <0x7>; <<
265 }; <<
266 <<
267 sgmii_phy_s1_p1: ether <<
268 reg = <0x1c>; <<
269 }; <<
270 }; <<
271 <<
272 /* Slot 2 */ <<
273 ls1043mdio_s2: mdio@60 { <<
274 reg = <0x60>; <<
275 #address-cells = <1>; <<
276 #size-cells = <0>; <<
277 status = "disabled"; <<
278 <<
279 qsgmii_phy_s2_p1: ethe <<
280 reg = <0x8>; <<
281 }; <<
282 <<
283 qsgmii_phy_s2_p2: ethe <<
284 reg = <0x9>; <<
285 }; <<
286 <<
287 qsgmii_phy_s2_p3: ethe <<
288 reg = <0xa>; <<
289 }; <<
290 <<
291 qsgmii_phy_s2_p4: ethe <<
292 reg = <0xb>; <<
293 }; <<
294 <<
295 sgmii_phy_s2_p1: ether <<
296 reg = <0x1c>; <<
297 }; <<
298 }; <<
299 <<
300 /* Slot 3 */ <<
301 ls1043mdio_s3: mdio@80 { <<
302 reg = <0x80>; <<
303 #address-cells = <1>; <<
304 #size-cells = <0>; <<
305 status = "disabled"; <<
306 <<
307 sgmii_phy_s3_p1: ether <<
308 reg = <0x1c>; <<
309 }; <<
310 }; <<
311 <<
312 /* Slot 4 */ <<
313 ls1043mdio_s4: mdio@a0 { <<
314 reg = <0xa0>; <<
315 #address-cells = <1>; <<
316 #size-cells = <0>; <<
317 status = "disabled"; <<
318 <<
319 sgmii_phy_s4_p1: ether <<
320 reg = <0x1c>; <<
321 }; <<
322 }; <<
323 }; <<
324 }; <<
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