Linux/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-qds.dts

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

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1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2 /* 2 /* 3 * Device Tree Include file for Freescale Laye 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC. 4 * 4 * 5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc. 6 * Copyright 2018-2021 NXP << 7 * 6 * 8 * Mingkai Hu <Mingkai.hu@freescale.com> 7 * Mingkai Hu <Mingkai.hu@freescale.com> 9 */ 8 */ 10 9 11 /dts-v1/; 10 /dts-v1/; 12 #include "fsl-ls1043a.dtsi" 11 #include "fsl-ls1043a.dtsi" 13 12 14 / { 13 / { 15 model = "LS1043A QDS Board"; 14 model = "LS1043A QDS Board"; 16 compatible = "fsl,ls1043a-qds", "fsl,l 15 compatible = "fsl,ls1043a-qds", "fsl,ls1043a"; 17 16 18 aliases { 17 aliases { 19 gpio0 = &gpio1; 18 gpio0 = &gpio1; 20 gpio1 = &gpio2; 19 gpio1 = &gpio2; 21 gpio2 = &gpio3; 20 gpio2 = &gpio3; 22 gpio3 = &gpio4; 21 gpio3 = &gpio4; 23 serial0 = &duart0; 22 serial0 = &duart0; 24 serial1 = &duart1; 23 serial1 = &duart1; 25 serial2 = &duart2; 24 serial2 = &duart2; 26 serial3 = &duart3; 25 serial3 = &duart3; 27 sgmii-riser-s1-p1 = &sgmii_phy << 28 sgmii-riser-s2-p1 = &sgmii_phy << 29 sgmii-riser-s3-p1 = &sgmii_phy << 30 sgmii-riser-s4-p1 = &sgmii_phy << 31 qsgmii-s1-p1 = &qsgmii_phy_s1_ << 32 qsgmii-s1-p2 = &qsgmii_phy_s1_ << 33 qsgmii-s1-p3 = &qsgmii_phy_s1_ << 34 qsgmii-s1-p4 = &qsgmii_phy_s1_ << 35 qsgmii-s2-p1 = &qsgmii_phy_s2_ << 36 qsgmii-s2-p2 = &qsgmii_phy_s2_ << 37 qsgmii-s2-p3 = &qsgmii_phy_s2_ << 38 qsgmii-s2-p4 = &qsgmii_phy_s2_ << 39 emi1-slot1 = &ls1043mdio_s1; << 40 emi1-slot2 = &ls1043mdio_s2; << 41 emi1-slot3 = &ls1043mdio_s3; << 42 emi1-slot4 = &ls1043mdio_s4; << 43 }; 26 }; 44 27 45 chosen { 28 chosen { 46 stdout-path = "serial0:115200n 29 stdout-path = "serial0:115200n8"; 47 }; 30 }; 48 }; 31 }; 49 32 50 &duart0 { 33 &duart0 { 51 status = "okay"; 34 status = "okay"; 52 }; 35 }; 53 36 54 &duart1 { 37 &duart1 { 55 status = "okay"; 38 status = "okay"; 56 }; 39 }; 57 40 58 &ifc { 41 &ifc { 59 #address-cells = <2>; 42 #address-cells = <2>; 60 #size-cells = <1>; 43 #size-cells = <1>; 61 /* NOR, NAND Flashes and FPGA on board 44 /* NOR, NAND Flashes and FPGA on board */ 62 ranges = <0x0 0x0 0x0 0x60000000 0x080 45 ranges = <0x0 0x0 0x0 0x60000000 0x08000000 63 0x1 0x0 0x0 0x7e800000 0x000 46 0x1 0x0 0x0 0x7e800000 0x00010000 64 0x2 0x0 0x0 0x7fb00000 0x000 47 0x2 0x0 0x0 0x7fb00000 0x00000100>; 65 status = "okay"; 48 status = "okay"; 66 49 67 flash@0,0 { !! 50 nor@0,0 { 68 compatible = "cfi-flash"; 51 compatible = "cfi-flash"; 69 reg = <0x0 0x0 0x8000000>; 52 reg = <0x0 0x0 0x8000000>; 70 big-endian; << 71 bank-width = <2>; 53 bank-width = <2>; 72 device-width = <1>; 54 device-width = <1>; 73 }; 55 }; 74 56 75 nand@1,0 { 57 nand@1,0 { 76 compatible = "fsl,ifc-nand"; 58 compatible = "fsl,ifc-nand"; 77 reg = <0x1 0x0 0x10000>; 59 reg = <0x1 0x0 0x10000>; 78 }; 60 }; 79 61 80 fpga: board-control@2,0 { 62 fpga: board-control@2,0 { 81 compatible = "fsl,ls1043aqds-f !! 63 compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; 82 reg = <0x2 0x0 0x0000100>; 64 reg = <0x2 0x0 0x0000100>; 83 #address-cells = <1>; << 84 #size-cells = <1>; << 85 ranges = <0 2 0 0x100>; << 86 }; 65 }; 87 }; 66 }; 88 67 89 &i2c0 { 68 &i2c0 { 90 status = "okay"; 69 status = "okay"; 91 70 92 i2c-mux@77 { !! 71 pca9547@77 { 93 compatible = "nxp,pca9547"; 72 compatible = "nxp,pca9547"; 94 reg = <0x77>; 73 reg = <0x77>; 95 #address-cells = <1>; 74 #address-cells = <1>; 96 #size-cells = <0>; 75 #size-cells = <0>; 97 76 98 i2c@0 { 77 i2c@0 { 99 #address-cells = <1>; 78 #address-cells = <1>; 100 #size-cells = <0>; 79 #size-cells = <0>; 101 reg = <0x0>; 80 reg = <0x0>; 102 81 103 rtc@68 { 82 rtc@68 { 104 compatible = " 83 compatible = "dallas,ds3232"; 105 reg = <0x68>; 84 reg = <0x68>; 106 /* IRQ10_B */ 85 /* IRQ10_B */ 107 interrupts = < 86 interrupts = <0 150 0x4>; 108 }; 87 }; 109 }; 88 }; 110 89 111 i2c@2 { 90 i2c@2 { 112 #address-cells = <1>; 91 #address-cells = <1>; 113 #size-cells = <0>; 92 #size-cells = <0>; 114 reg = <0x2>; 93 reg = <0x2>; 115 94 116 ina220@40 { 95 ina220@40 { 117 compatible = " 96 compatible = "ti,ina220"; 118 reg = <0x40>; 97 reg = <0x40>; 119 shunt-resistor 98 shunt-resistor = <1000>; 120 }; 99 }; 121 100 122 ina220@41 { 101 ina220@41 { 123 compatible = " 102 compatible = "ti,ina220"; 124 reg = <0x41>; 103 reg = <0x41>; 125 shunt-resistor 104 shunt-resistor = <1000>; 126 }; 105 }; 127 }; 106 }; 128 107 129 i2c@3 { 108 i2c@3 { 130 #address-cells = <1>; 109 #address-cells = <1>; 131 #size-cells = <0>; 110 #size-cells = <0>; 132 reg = <0x3>; 111 reg = <0x3>; 133 112 134 eeprom@56 { 113 eeprom@56 { 135 compatible = " 114 compatible = "atmel,24c512"; 136 reg = <0x56>; 115 reg = <0x56>; 137 }; 116 }; 138 117 139 eeprom@57 { 118 eeprom@57 { 140 compatible = " 119 compatible = "atmel,24c512"; 141 reg = <0x57>; 120 reg = <0x57>; 142 }; 121 }; 143 122 144 temp-sensor@4c { 123 temp-sensor@4c { 145 compatible = " 124 compatible = "adi,adt7461a"; 146 reg = <0x4c>; 125 reg = <0x4c>; 147 }; 126 }; 148 }; 127 }; 149 }; 128 }; 150 }; 129 }; 151 130 152 &lpuart0 { 131 &lpuart0 { 153 status = "okay"; 132 status = "okay"; 154 }; 133 }; 155 134 156 &qspi { 135 &qspi { >> 136 bus-num = <0>; 157 status = "okay"; 137 status = "okay"; 158 138 159 qflash0: flash@0 { !! 139 qflash0: s25fl128s@0 { 160 compatible = "spansion,m25p80" 140 compatible = "spansion,m25p80"; 161 #address-cells = <1>; 141 #address-cells = <1>; 162 #size-cells = <1>; 142 #size-cells = <1>; 163 spi-max-frequency = <20000000> 143 spi-max-frequency = <20000000>; 164 spi-rx-bus-width = <4>; << 165 spi-tx-bus-width = <4>; << 166 reg = <0>; 144 reg = <0>; 167 }; 145 }; 168 }; 146 }; 169 147 170 &usb0 { << 171 status = "okay"; << 172 }; << 173 << 174 #include "fsl-ls1043-post.dtsi" 148 #include "fsl-ls1043-post.dtsi" 175 << 176 &fman0 { << 177 ethernet@e0000 { << 178 phy-handle = <&qsgmii_phy_s2_p << 179 phy-connection-type = "sgmii"; << 180 }; << 181 << 182 ethernet@e2000 { << 183 phy-handle = <&qsgmii_phy_s2_p << 184 phy-connection-type = "sgmii"; << 185 }; << 186 << 187 ethernet@e4000 { << 188 phy-handle = <&rgmii_phy1>; << 189 phy-connection-type = "rgmii"; << 190 }; << 191 << 192 ethernet@e6000 { << 193 phy-handle = <&rgmii_phy2>; << 194 phy-connection-type = "rgmii"; << 195 }; << 196 << 197 ethernet@e8000 { << 198 phy-handle = <&qsgmii_phy_s2_p << 199 phy-connection-type = "sgmii"; << 200 }; << 201 << 202 ethernet@ea000 { << 203 phy-handle = <&qsgmii_phy_s2_p << 204 phy-connection-type = "sgmii"; << 205 }; << 206 << 207 ethernet@f0000 { /* DTSEC9/10GEC1 */ << 208 fixed-link = <1 1 10000 0 0>; << 209 phy-connection-type = "xgmii"; << 210 }; << 211 }; << 212 << 213 &fpga { << 214 mdio-mux@54 { << 215 compatible = "mdio-mux-mmioreg << 216 mdio-parent-bus = <&mdio0>; << 217 #address-cells = <1>; << 218 #size-cells = <0>; << 219 reg = <0x54 1>; /* BRDCFG4 << 220 mux-mask = <0xe0>; /* EMI1 */ << 221 << 222 /* On-board RGMII1 PHY */ << 223 ls1043mdio0: mdio@0 { << 224 reg = <0>; << 225 #address-cells = <1>; << 226 #size-cells = <0>; << 227 << 228 rgmii_phy1: ethernet-p << 229 reg = <0x1>; << 230 }; << 231 }; << 232 << 233 /* On-board RGMII2 PHY */ << 234 ls1043mdio1: mdio@20 { << 235 reg = <0x20>; << 236 #address-cells = <1>; << 237 #size-cells = <0>; << 238 << 239 rgmii_phy2: ethernet-p << 240 reg = <0x2>; << 241 }; << 242 }; << 243 << 244 /* Slot 1 */ << 245 ls1043mdio_s1: mdio@40 { << 246 reg = <0x40>; << 247 #address-cells = <1>; << 248 #size-cells = <0>; << 249 status = "disabled"; << 250 << 251 qsgmii_phy_s1_p1: ethe << 252 reg = <0x4>; << 253 }; << 254 << 255 qsgmii_phy_s1_p2: ethe << 256 reg = <0x5>; << 257 }; << 258 << 259 qsgmii_phy_s1_p3: ethe << 260 reg = <0x6>; << 261 }; << 262 << 263 qsgmii_phy_s1_p4: ethe << 264 reg = <0x7>; << 265 }; << 266 << 267 sgmii_phy_s1_p1: ether << 268 reg = <0x1c>; << 269 }; << 270 }; << 271 << 272 /* Slot 2 */ << 273 ls1043mdio_s2: mdio@60 { << 274 reg = <0x60>; << 275 #address-cells = <1>; << 276 #size-cells = <0>; << 277 status = "disabled"; << 278 << 279 qsgmii_phy_s2_p1: ethe << 280 reg = <0x8>; << 281 }; << 282 << 283 qsgmii_phy_s2_p2: ethe << 284 reg = <0x9>; << 285 }; << 286 << 287 qsgmii_phy_s2_p3: ethe << 288 reg = <0xa>; << 289 }; << 290 << 291 qsgmii_phy_s2_p4: ethe << 292 reg = <0xb>; << 293 }; << 294 << 295 sgmii_phy_s2_p1: ether << 296 reg = <0x1c>; << 297 }; << 298 }; << 299 << 300 /* Slot 3 */ << 301 ls1043mdio_s3: mdio@80 { << 302 reg = <0x80>; << 303 #address-cells = <1>; << 304 #size-cells = <0>; << 305 status = "disabled"; << 306 << 307 sgmii_phy_s3_p1: ether << 308 reg = <0x1c>; << 309 }; << 310 }; << 311 << 312 /* Slot 4 */ << 313 ls1043mdio_s4: mdio@a0 { << 314 reg = <0xa0>; << 315 #address-cells = <1>; << 316 #size-cells = <0>; << 317 status = "disabled"; << 318 << 319 sgmii_phy_s4_p1: ether << 320 reg = <0x1c>; << 321 }; << 322 }; << 323 }; << 324 }; <<

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Linux/scripts/dtc/include-prefixes/arm64/freescale/fsl-ls1043a-qds.dts