1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape
4 *
5 * Copyright 2014-2015 Freescale Semiconductor
6 * Copyright 2018, 2020 NXP
7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */
10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen
12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm
14 #include <dt-bindings/gpio/gpio.h>
15
16 / {
17 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
21
22 aliases {
23 crypto = &crypto;
24 fman0 = &fman0;
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 ethernet4 = &enet4;
30 ethernet5 = &enet5;
31 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0;
33 };
34
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
38
39 /*
40 * We expect the enable-method
41 * is dependent on the SoC FW,
42 *
43 * Currently supported enable-
44 */
45 cpu0: cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cort
48 reg = <0x0>;
49 clocks = <&clockgen QO
50 next-level-cache = <&l
51 cpu-idle-states = <&CP
52 #cooling-cells = <2>;
53 };
54
55 cpu1: cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cort
58 reg = <0x1>;
59 clocks = <&clockgen QO
60 next-level-cache = <&l
61 cpu-idle-states = <&CP
62 #cooling-cells = <2>;
63 };
64
65 cpu2: cpu@2 {
66 device_type = "cpu";
67 compatible = "arm,cort
68 reg = <0x2>;
69 clocks = <&clockgen QO
70 next-level-cache = <&l
71 cpu-idle-states = <&CP
72 #cooling-cells = <2>;
73 };
74
75 cpu3: cpu@3 {
76 device_type = "cpu";
77 compatible = "arm,cort
78 reg = <0x3>;
79 clocks = <&clockgen QO
80 next-level-cache = <&l
81 cpu-idle-states = <&CP
82 #cooling-cells = <2>;
83 };
84
85 l2: l2-cache {
86 compatible = "cache";
87 cache-level = <2>;
88 cache-unified;
89 };
90 };
91
92 idle-states {
93 /*
94 * PSCI node is not added defa
95 * parts if it determines to u
96 */
97 entry-method = "psci";
98
99 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle
101 idle-state-name = "PH2
102 arm,psci-suspend-param
103 entry-latency-us = <10
104 exit-latency-us = <100
105 min-residency-us = <30
106 };
107 };
108
109 memory@80000000 {
110 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000
112 /* DRAM space 1, size: 2
113 };
114
115 reserved-memory {
116 #address-cells = <2>;
117 #size-cells = <2>;
118 ranges;
119
120 bman_fbpr: bman-fbpr {
121 compatible = "shared-d
122 size = <0 0x1000000>;
123 alignment = <0 0x10000
124 no-map;
125 };
126
127 qman_fqd: qman-fqd {
128 compatible = "shared-d
129 size = <0 0x400000>;
130 alignment = <0 0x40000
131 no-map;
132 };
133
134 qman_pfdr: qman-pfdr {
135 compatible = "shared-d
136 size = <0 0x2000000>;
137 alignment = <0 0x20000
138 no-map;
139 };
140 };
141
142 sysclk: sysclk {
143 compatible = "fixed-clock";
144 #clock-cells = <0>;
145 clock-frequency = <100000000>;
146 clock-output-names = "sysclk";
147 };
148
149 reboot {
150 compatible = "syscon-reboot";
151 regmap = <&dcfg>;
152 offset = <0xb0>;
153 mask = <0x02>;
154 };
155
156 thermal-zones {
157 ddr-thermal {
158 polling-delay-passive
159 polling-delay = <5000>
160 thermal-sensors = <&tm
161
162 trips {
163 ddr-ctrler-ale
164 temper
165 hyster
166 type =
167 };
168
169 ddr-ctrler-cri
170 temper
171 hyster
172 type =
173 };
174 };
175 };
176
177 serdes-thermal {
178 polling-delay-passive
179 polling-delay = <5000>
180 thermal-sensors = <&tm
181
182 trips {
183 serdes-alert {
184 temper
185 hyster
186 type =
187 };
188
189 serdes-crit {
190 temper
191 hyster
192 type =
193 };
194 };
195 };
196
197 fman-thermal {
198 polling-delay-passive
199 polling-delay = <5000>
200 thermal-sensors = <&tm
201
202 trips {
203 fman-alert {
204 temper
205 hyster
206 type =
207 };
208
209 fman-crit {
210 temper
211 hyster
212 type =
213 };
214 };
215 };
216
217 cluster-thermal {
218 polling-delay-passive
219 polling-delay = <5000>
220 thermal-sensors = <&tm
221
222 trips {
223 core_cluster_a
224 temper
225 hyster
226 type =
227 };
228
229 core_cluster_c
230 temper
231 hyster
232 type =
233 };
234 };
235
236 cooling-maps {
237 map0 {
238 trip =
239 coolin
240
241
242
243
244 };
245 };
246 };
247
248 sec-thermal {
249 polling-delay-passive
250 polling-delay = <5000>
251 thermal-sensors = <&tm
252
253 trips {
254 sec-alert {
255 temper
256 hyster
257 type =
258 };
259
260 sec-crit {
261 temper
262 hyster
263 type =
264 };
265 };
266 };
267 };
268
269 timer {
270 compatible = "arm,armv8-timer"
271 interrupts = <GIC_PPI 13 (GIC_
272 <GIC_PPI 14 (GIC_
273 <GIC_PPI 11 (GIC_
274 <GIC_PPI 10 (GIC_
275 fsl,erratum-a008585;
276 };
277
278 pmu {
279 compatible = "arm,cortex-a53-p
280 interrupts = <GIC_SPI 106 IRQ_
281 <GIC_SPI 107 IRQ_
282 <GIC_SPI 95 IRQ_T
283 <GIC_SPI 97 IRQ_T
284 interrupt-affinity = <&cpu0>,
285 <&cpu1>,
286 <&cpu2>,
287 <&cpu3>;
288 };
289
290 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400";
292 #interrupt-cells = <3>;
293 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000>
295 <0x0 0x1402000 0 0x2000>
296 <0x0 0x1404000 0 0x2000>
297 <0x0 0x1406000 0 0x2000>
298 interrupts = <GIC_PPI 9 (GIC_C
299 };
300
301 soc: soc {
302 compatible = "simple-bus";
303 #address-cells = <2>;
304 #size-cells = <2>;
305 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0
307 dma-coherent;
308
309 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10
311 reg = <0x0 0x1ee1000 0
312 #clock-cells = <2>;
313 clocks = <&sysclk>;
314 };
315
316 scfg: scfg@1570000 {
317 compatible = "fsl,ls10
318 reg = <0x0 0x1570000 0
319 big-endian;
320 #address-cells = <1>;
321 #size-cells = <1>;
322 ranges = <0x0 0x0 0x15
323
324 extirq: interrupt-cont
325 compatible = "
326 #interrupt-cel
327 #address-cells
328 interrupt-cont
329 reg = <0x1ac 4
330 interrupt-map
331 <0 0 &
332 <1 0 &
333 <2 0 &
334 <3 0 &
335 <4 0 &
336 <5 0 &
337 <6 0 &
338 <7 0 &
339 <8 0 &
340 <9 0 &
341 <10 0
342 <11 0
343 interrupt-map-
344 };
345 };
346
347 crypto: crypto@1700000 {
348 compatible = "fsl,sec-
349 "fsl,sec-
350 fsl,sec-era = <3>;
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1
354 reg = <0x00 0x1700000
355 interrupts = <GIC_SPI
356 dma-coherent;
357
358 sec_jr0: jr@10000 {
359 compatible = "
360 "
361 "
362 reg = <0x10000
363 interrupts = <
364 };
365
366 sec_jr1: jr@20000 {
367 compatible = "
368 "
369 "
370 reg = <0x20000
371 interrupts = <
372 };
373
374 sec_jr2: jr@30000 {
375 compatible = "
376 "
377 "
378 reg = <0x30000
379 interrupts = <
380 };
381
382 sec_jr3: jr@40000 {
383 compatible = "
384 "
385 "
386 reg = <0x40000
387 interrupts = <
388 };
389 };
390
391 sfp: efuse@1e80000 {
392 compatible = "fsl,ls10
393 reg = <0x0 0x1e80000 0
394 clocks = <&clockgen QO
395 QO
396 clock-names = "sfp";
397 };
398
399 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10
401 reg = <0x0 0x1ee0000 0
402 big-endian;
403 };
404
405 ifc: memory-controller@1530000
406 compatible = "fsl,ifc"
407 reg = <0x0 0x1530000 0
408 interrupts = <GIC_SPI
409 };
410
411 qspi: spi@1550000 {
412 compatible = "fsl,ls10
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0
416 <0x0 0x4000000
417 reg-names = "QuadSPI",
418 interrupts = <GIC_SPI
419 clock-names = "qspi_en
420 clocks = <&clockgen QO
421 QO
422 <&clockgen QO
423 QO
424 status = "disabled";
425 };
426
427 esdhc: mmc@1560000 {
428 compatible = "fsl,ls10
429 reg = <0x0 0x1560000 0
430 interrupts = <GIC_SPI
431 clock-frequency = <0>;
432 voltage-ranges = <1800
433 sdhci,auto-cmd12;
434 bus-width = <4>;
435 };
436
437 ddr: memory-controller@1080000
438 compatible = "fsl,qori
439 reg = <0x0 0x1080000 0
440 interrupts = <GIC_SPI
441 };
442
443 tmu: tmu@1f00000 {
444 compatible = "fsl,qori
445 reg = <0x0 0x1f00000 0
446 interrupts = <GIC_SPI
447 fsl,tmu-range = <0xb00
448 fsl,tmu-calibration =
449 <0x000
450 <0x000
451 <0x000
452 <0x000
453 <0x000
454 <0x000
455 <0x000
456 <0x000
457 <0x000
458 <0x000
459 <0x000
460 <0x000
461
462 <0x000
463 <0x000
464 <0x000
465 <0x000
466 <0x000
467 <0x000
468 <0x000
469 <0x000
470 <0x000
471 <0x000
472
473 <0x000
474 <0x000
475 <0x000
476 <0x000
477 <0x000
478 <0x000
479 <0x000
480
481 <0x000
482 <0x000
483 <0x000
484 <0x000
485 <0x000
486 <0x000
487 <0x000
488 <0x000
489 #thermal-sensor-cells
490 };
491
492 qman: qman@1880000 {
493 compatible = "fsl,qman
494 reg = <0x0 0x1880000 0
495 interrupts = <GIC_SPI
496 memory-region = <&qman
497 };
498
499 bman: bman@1890000 {
500 compatible = "fsl,bman
501 reg = <0x0 0x1890000 0
502 interrupts = <GIC_SPI
503 memory-region = <&bman
504 };
505
506 bportals: bman-portals-bus@508
507 ranges = <0x0 0x5 0x08
508 };
509
510 qportals: qman-portals-bus@500
511 ranges = <0x0 0x5 0x00
512 };
513
514 dspi0: spi@2100000 {
515 compatible = "fsl,ls10
516 #address-cells = <1>;
517 #size-cells = <0>;
518 reg = <0x0 0x2100000 0
519 interrupts = <GIC_SPI
520 clock-names = "dspi";
521 clocks = <&clockgen QO
522 QO
523 spi-num-chipselects =
524 big-endian;
525 status = "disabled";
526 };
527
528 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10
530 #address-cells = <1>;
531 #size-cells = <0>;
532 reg = <0x0 0x2180000 0
533 interrupts = <GIC_SPI
534 clock-names = "ipg";
535 clocks = <&clockgen QO
536 QO
537 dmas = <&edma0 1 38>,
538 <&edma0 1 39>;
539 dma-names = "rx", "tx"
540 status = "disabled";
541 };
542
543 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10
545 #address-cells = <1>;
546 #size-cells = <0>;
547 reg = <0x0 0x2190000 0
548 interrupts = <GIC_SPI
549 clock-names = "ipg";
550 clocks = <&clockgen QO
551 QO
552 scl-gpios = <&gpio4 2
553 status = "disabled";
554 };
555
556 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10
558 #address-cells = <1>;
559 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0
561 interrupts = <GIC_SPI
562 clock-names = "ipg";
563 clocks = <&clockgen QO
564 QO
565 scl-gpios = <&gpio4 10
566 status = "disabled";
567 };
568
569 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10
571 #address-cells = <1>;
572 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0
574 interrupts = <GIC_SPI
575 clock-names = "ipg";
576 clocks = <&clockgen QO
577 QO
578 scl-gpios = <&gpio4 12
579 status = "disabled";
580 };
581
582 duart0: serial@21c0500 {
583 compatible = "fsl,ns16
584 reg = <0x00 0x21c0500
585 interrupts = <GIC_SPI
586 clocks = <&clockgen QO
587 QO
588 };
589
590 duart1: serial@21c0600 {
591 compatible = "fsl,ns16
592 reg = <0x00 0x21c0600
593 interrupts = <GIC_SPI
594 clocks = <&clockgen QO
595 QO
596 };
597
598 duart2: serial@21d0500 {
599 compatible = "fsl,ns16
600 reg = <0x0 0x21d0500 0
601 interrupts = <GIC_SPI
602 clocks = <&clockgen QO
603 QO
604 };
605
606 duart3: serial@21d0600 {
607 compatible = "fsl,ns16
608 reg = <0x0 0x21d0600 0
609 interrupts = <GIC_SPI
610 clocks = <&clockgen QO
611 QO
612 };
613
614 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10
616 reg = <0x0 0x2300000 0
617 interrupts = <GIC_SPI
618 gpio-controller;
619 #gpio-cells = <2>;
620 interrupt-controller;
621 #interrupt-cells = <2>
622 };
623
624 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10
626 reg = <0x0 0x2310000 0
627 interrupts = <GIC_SPI
628 gpio-controller;
629 #gpio-cells = <2>;
630 interrupt-controller;
631 #interrupt-cells = <2>
632 };
633
634 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10
636 reg = <0x0 0x2320000 0
637 interrupts = <GIC_SPI
638 gpio-controller;
639 #gpio-cells = <2>;
640 interrupt-controller;
641 #interrupt-cells = <2>
642 };
643
644 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10
646 reg = <0x0 0x2330000 0
647 interrupts = <GIC_SPI
648 gpio-controller;
649 #gpio-cells = <2>;
650 interrupt-controller;
651 #interrupt-cells = <2>
652 };
653
654 uqe: uqe-bus@2400000 {
655 #address-cells = <1>;
656 #size-cells = <1>;
657 compatible = "fsl,qe",
658 ranges = <0x0 0x0 0x24
659 reg = <0x0 0x2400000 0
660 brg-frequency = <10000
661 bus-frequency = <20000
662 fsl,qe-num-riscs = <1>
663 fsl,qe-num-snums = <28
664
665 qeic: qeic@80 {
666 compatible = "
667 reg = <0x80 0x
668 interrupt-cont
669 #interrupt-cel
670 interrupts = <
671 <
672 };
673
674 si1: si@700 {
675 compatible = "
676
677 reg = <0x700 0
678 };
679
680 siram1: siram@1000 {
681 compatible = "
682
683 reg = <0x1000
684 };
685
686 ucc@2000 {
687 cell-index = <
688 reg = <0x2000
689 interrupts = <
690 interrupt-pare
691 };
692
693 ucc@2200 {
694 cell-index = <
695 reg = <0x2200
696 interrupts = <
697 interrupt-pare
698 };
699
700 muram@10000 {
701 #address-cells
702 #size-cells =
703 compatible = "
704 ranges = <0x0
705
706 data-only@0 {
707 compat
708 "fsl,c
709 reg =
710 };
711 };
712 };
713
714 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10
716 reg = <0x0 0x2950000 0
717 interrupts = <GIC_SPI
718 clocks = <&clockgen QO
719 clock-names = "ipg";
720 status = "disabled";
721 };
722
723 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10
725 reg = <0x0 0x2960000 0
726 interrupts = <GIC_SPI
727 clocks = <&clockgen QO
728 QO
729 clock-names = "ipg";
730 status = "disabled";
731 };
732
733 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10
735 reg = <0x0 0x2970000 0
736 interrupts = <GIC_SPI
737 clocks = <&clockgen QO
738 QO
739 clock-names = "ipg";
740 status = "disabled";
741 };
742
743 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10
745 reg = <0x0 0x2980000 0
746 interrupts = <GIC_SPI
747 clocks = <&clockgen QO
748 QO
749 clock-names = "ipg";
750 status = "disabled";
751 };
752
753 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10
755 reg = <0x0 0x2990000 0
756 interrupts = <GIC_SPI
757 clocks = <&clockgen QO
758 QO
759 clock-names = "ipg";
760 status = "disabled";
761 };
762
763 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10
765 reg = <0x0 0x29a0000 0
766 interrupts = <GIC_SPI
767 clocks = <&clockgen QO
768 QO
769 clock-names = "ipg";
770 status = "disabled";
771 };
772
773 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls10
775 reg = <0x0 0x2ad0000 0
776 interrupts = <GIC_SPI
777 clocks = <&clockgen QO
778 QO
779 big-endian;
780 };
781
782 edma0: dma-controller@2c00000
783 #dma-cells = <2>;
784 compatible = "fsl,vf61
785 reg = <0x0 0x2c00000 0
786 <0x0 0x2c10000 0
787 <0x0 0x2c20000 0
788 interrupts = <GIC_SPI
789 <GIC_SPI
790 interrupt-names = "edm
791 dma-channels = <32>;
792 big-endian;
793 clock-names = "dmamux0
794 clocks = <&clockgen QO
795 QO
796 <&clockgen QO
797 QO
798 };
799
800 aux_bus: bus {
801 #address-cells = <2>;
802 #size-cells = <2>;
803 compatible = "simple-b
804 ranges;
805 dma-ranges = <0x0 0x0
806
807 usb0: usb@2f00000 {
808 compatible = "
809 reg = <0x0 0x2
810 interrupts = <
811 dr_mode = "hos
812 snps,quirk-fra
813 snps,dis_rxdet
814 usb3-lpm-capab
815 snps,incr-burs
816 status = "disa
817 };
818
819 usb1: usb@3000000 {
820 compatible = "
821 reg = <0x0 0x3
822 interrupts = <
823 dr_mode = "hos
824 snps,quirk-fra
825 snps,dis_rxdet
826 usb3-lpm-capab
827 snps,incr-burs
828 status = "disa
829 };
830
831 usb2: usb@3100000 {
832 compatible = "
833 reg = <0x0 0x3
834 interrupts = <
835 dr_mode = "hos
836 snps,quirk-fra
837 snps,dis_rxdet
838 usb3-lpm-capab
839 snps,incr-burs
840 status = "disa
841 };
842
843 sata: sata@3200000 {
844 compatible = "
845 reg = <0x0 0x3
846 <0x0 0
847 reg-names = "a
848 interrupts = <
849 clocks = <&clo
850
851 dma-coherent;
852 };
853 };
854
855 msi1: msi-controller1@1571000
856 compatible = "fsl,ls10
857 reg = <0x0 0x1571000 0
858 msi-controller;
859 interrupts = <GIC_SPI
860 };
861
862 msi2: msi-controller2@1572000
863 compatible = "fsl,ls10
864 reg = <0x0 0x1572000 0
865 msi-controller;
866 interrupts = <GIC_SPI
867 };
868
869 msi3: msi-controller3@1573000
870 compatible = "fsl,ls10
871 reg = <0x0 0x1573000 0
872 msi-controller;
873 interrupts = <GIC_SPI
874 };
875
876 pcie1: pcie@3400000 {
877 compatible = "fsl,ls10
878 reg = <0x00 0x03400000
879 <0x40 0x00000000
880 reg-names = "regs", "c
881 interrupts = <GIC_SPI
882 <GIC_SPI
883 interrupt-names = "pme
884 #address-cells = <3>;
885 #size-cells = <2>;
886 device_type = "pci";
887 num-viewport = <6>;
888 bus-range = <0x0 0xff>
889 ranges = <0x81000000 0
890 0x82000000 0
891 msi-parent = <&msi1>,
892 #interrupt-cells = <1>
893 interrupt-map-mask = <
894 interrupt-map = <0000
895 <0000
896 <0000
897 <0000
898 fsl,pcie-scfg = <&scfg
899 big-endian;
900 status = "disabled";
901 };
902
903 pcie2: pcie@3500000 {
904 compatible = "fsl,ls10
905 reg = <0x00 0x03500000
906 <0x48 0x00000000
907 reg-names = "regs", "c
908 interrupts = <GIC_SPI
909 <GIC_SPI
910 interrupt-names = "pme
911 #address-cells = <3>;
912 #size-cells = <2>;
913 device_type = "pci";
914 num-viewport = <6>;
915 bus-range = <0x0 0xff>
916 ranges = <0x81000000 0
917 0x82000000 0
918 msi-parent = <&msi1>,
919 #interrupt-cells = <1>
920 interrupt-map-mask = <
921 interrupt-map = <0000
922 <0000
923 <0000
924 <0000
925 fsl,pcie-scfg = <&scfg
926 big-endian;
927 status = "disabled";
928 };
929
930 pcie3: pcie@3600000 {
931 compatible = "fsl,ls10
932 reg = <0x00 0x03600000
933 <0x50 0x00000000
934 reg-names = "regs", "c
935 interrupts = <GIC_SPI
936 <GIC_SPI
937 interrupt-names = "pme
938 #address-cells = <3>;
939 #size-cells = <2>;
940 device_type = "pci";
941 num-viewport = <6>;
942 bus-range = <0x0 0xff>
943 ranges = <0x81000000 0
944 0x82000000 0
945 msi-parent = <&msi1>,
946 #interrupt-cells = <1>
947 interrupt-map-mask = <
948 interrupt-map = <0000
949 <0000
950 <0000
951 <0000
952 fsl,pcie-scfg = <&scfg
953 big-endian;
954 status = "disabled";
955 };
956
957 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls10
959 reg = <0x0 0x8380000 0
960 <0x0 0x8390000 0
961 <0x0 0x83a0000 0
962 interrupts = <GIC_SPI
963 <GIC_SPI
964 <GIC_SPI
965 <GIC_SPI
966 <GIC_SPI
967 interrupt-names = "qdm
968 "qdma-queue1",
969 #dma-cells = <1>;
970 dma-channels = <8>;
971 block-number = <1>;
972 block-offset = <0x1000
973 fsl,dma-queues = <2>;
974 status-sizes = <64>;
975 queue-sizes = <64 64>;
976 big-endian;
977 };
978
979 rcpm: wakeup-controller@1ee214
980 compatible = "fsl,ls10
981 reg = <0x0 0x1ee2140 0
982 #fsl,rcpm-wakeup-cells
983 };
984
985 ftm_alarm0: rtc@29d0000 {
986 compatible = "fsl,ls10
987 reg = <0x0 0x29d0000 0
988 fsl,rcpm-wakeup = <&rc
989 interrupts = <GIC_SPI
990 big-endian;
991 };
992 };
993
994 firmware {
995 optee {
996 compatible = "linaro,o
997 method = "smc";
998 };
999 };
1000
1001 };
1002
1003 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi"
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