1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Device Tree Include file for NXP Layerscape !! 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * 3 *
5 * Copyright 2014-2015 Freescale Semiconductor !! 4 * Copyright 2014-2015, Freescale Semiconductor
6 * Copyright 2018, 2020 NXP <<
7 * 5 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 6 * Mingkai Hu <Mingkai.hu@freescale.com>
>> 7 *
>> 8 * This file is dual-licensed: you can use it either under the terms
>> 9 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 10 * licensing only applies to this file, and not this project as a
>> 11 * whole.
>> 12 *
>> 13 * a) This library is free software; you can redistribute it and/or
>> 14 * modify it under the terms of the GNU General Public License as
>> 15 * published by the Free Software Foundation; either version 2 of the
>> 16 * License, or (at your option) any later version.
>> 17 *
>> 18 * This library is distributed in the hope that it will be useful,
>> 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 21 * GNU General Public License for more details.
>> 22 *
>> 23 * Or, alternatively,
>> 24 *
>> 25 * b) Permission is hereby granted, free of charge, to any person
>> 26 * obtaining a copy of this software and associated documentation
>> 27 * files (the "Software"), to deal in the Software without
>> 28 * restriction, including without limitation the rights to use,
>> 29 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 30 * sell copies of the Software, and to permit persons to whom the
>> 31 * Software is furnished to do so, subject to the following
>> 32 * conditions:
>> 33 *
>> 34 * The above copyright notice and this permission notice shall be
>> 35 * included in all copies or substantial portions of the Software.
>> 36 *
>> 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 44 * OTHER DEALINGS IN THE SOFTWARE.
9 */ 45 */
10 46
11 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
12 #include <dt-bindings/thermal/thermal.h> 47 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm <<
14 #include <dt-bindings/gpio/gpio.h> <<
15 48
16 / { 49 / {
17 compatible = "fsl,ls1043a"; 50 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 51 interrupt-parent = <&gic>;
19 #address-cells = <2>; 52 #address-cells = <2>;
20 #size-cells = <2>; 53 #size-cells = <2>;
21 54
22 aliases { <<
23 crypto = &crypto; <<
24 fman0 = &fman0; <<
25 ethernet0 = &enet0; <<
26 ethernet1 = &enet1; <<
27 ethernet2 = &enet2; <<
28 ethernet3 = &enet3; <<
29 ethernet4 = &enet4; <<
30 ethernet5 = &enet5; <<
31 ethernet6 = &enet6; <<
32 rtc1 = &ftm_alarm0; <<
33 }; <<
34 <<
35 cpus { 55 cpus {
36 #address-cells = <1>; 56 #address-cells = <1>;
37 #size-cells = <0>; 57 #size-cells = <0>;
38 58
39 /* 59 /*
40 * We expect the enable-method 60 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 61 * is dependent on the SoC FW, which will fill this in.
42 * 62 *
43 * Currently supported enable- 63 * Currently supported enable-method is psci v0.2
44 */ 64 */
45 cpu0: cpu@0 { 65 cpu0: cpu@0 {
46 device_type = "cpu"; 66 device_type = "cpu";
47 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
48 reg = <0x0>; 68 reg = <0x0>;
49 clocks = <&clockgen QO !! 69 clocks = <&clockgen 1 0>;
50 next-level-cache = <&l 70 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP <<
52 #cooling-cells = <2>; 71 #cooling-cells = <2>;
53 }; 72 };
54 73
55 cpu1: cpu@1 { 74 cpu1: cpu@1 {
56 device_type = "cpu"; 75 device_type = "cpu";
57 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
58 reg = <0x1>; 77 reg = <0x1>;
59 clocks = <&clockgen QO !! 78 clocks = <&clockgen 1 0>;
60 next-level-cache = <&l 79 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP <<
62 #cooling-cells = <2>; <<
63 }; 80 };
64 81
65 cpu2: cpu@2 { 82 cpu2: cpu@2 {
66 device_type = "cpu"; 83 device_type = "cpu";
67 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
68 reg = <0x2>; 85 reg = <0x2>;
69 clocks = <&clockgen QO !! 86 clocks = <&clockgen 1 0>;
70 next-level-cache = <&l 87 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP <<
72 #cooling-cells = <2>; <<
73 }; 88 };
74 89
75 cpu3: cpu@3 { 90 cpu3: cpu@3 {
76 device_type = "cpu"; 91 device_type = "cpu";
77 compatible = "arm,cort 92 compatible = "arm,cortex-a53";
78 reg = <0x3>; 93 reg = <0x3>;
79 clocks = <&clockgen QO !! 94 clocks = <&clockgen 1 0>;
80 next-level-cache = <&l 95 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP <<
82 #cooling-cells = <2>; <<
83 }; 96 };
84 97
85 l2: l2-cache { 98 l2: l2-cache {
86 compatible = "cache"; 99 compatible = "cache";
87 cache-level = <2>; <<
88 cache-unified; <<
89 }; <<
90 }; <<
91 <<
92 idle-states { <<
93 /* <<
94 * PSCI node is not added defa <<
95 * parts if it determines to u <<
96 */ <<
97 entry-method = "psci"; <<
98 <<
99 CPU_PH20: cpu-ph20 { <<
100 compatible = "arm,idle <<
101 idle-state-name = "PH2 <<
102 arm,psci-suspend-param <<
103 entry-latency-us = <10 <<
104 exit-latency-us = <100 <<
105 min-residency-us = <30 <<
106 }; 100 };
107 }; 101 };
108 102
109 memory@80000000 { 103 memory@80000000 {
110 device_type = "memory"; 104 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 105 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 106 /* DRAM space 1, size: 2GiB DRAM */
113 }; 107 };
114 108
115 reserved-memory { <<
116 #address-cells = <2>; <<
117 #size-cells = <2>; <<
118 ranges; <<
119 <<
120 bman_fbpr: bman-fbpr { <<
121 compatible = "shared-d <<
122 size = <0 0x1000000>; <<
123 alignment = <0 0x10000 <<
124 no-map; <<
125 }; <<
126 <<
127 qman_fqd: qman-fqd { <<
128 compatible = "shared-d <<
129 size = <0 0x400000>; <<
130 alignment = <0 0x40000 <<
131 no-map; <<
132 }; <<
133 <<
134 qman_pfdr: qman-pfdr { <<
135 compatible = "shared-d <<
136 size = <0 0x2000000>; <<
137 alignment = <0 0x20000 <<
138 no-map; <<
139 }; <<
140 }; <<
141 <<
142 sysclk: sysclk { 109 sysclk: sysclk {
143 compatible = "fixed-clock"; 110 compatible = "fixed-clock";
144 #clock-cells = <0>; 111 #clock-cells = <0>;
145 clock-frequency = <100000000>; 112 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 113 clock-output-names = "sysclk";
147 }; 114 };
148 115
149 reboot { 116 reboot {
150 compatible = "syscon-reboot"; !! 117 compatible ="syscon-reboot";
151 regmap = <&dcfg>; 118 regmap = <&dcfg>;
152 offset = <0xb0>; 119 offset = <0xb0>;
153 mask = <0x02>; 120 mask = <0x02>;
154 }; 121 };
155 122
156 thermal-zones { <<
157 ddr-thermal { <<
158 polling-delay-passive <<
159 polling-delay = <5000> <<
160 thermal-sensors = <&tm <<
161 <<
162 trips { <<
163 ddr-ctrler-ale <<
164 temper <<
165 hyster <<
166 type = <<
167 }; <<
168 <<
169 ddr-ctrler-cri <<
170 temper <<
171 hyster <<
172 type = <<
173 }; <<
174 }; <<
175 }; <<
176 <<
177 serdes-thermal { <<
178 polling-delay-passive <<
179 polling-delay = <5000> <<
180 thermal-sensors = <&tm <<
181 <<
182 trips { <<
183 serdes-alert { <<
184 temper <<
185 hyster <<
186 type = <<
187 }; <<
188 <<
189 serdes-crit { <<
190 temper <<
191 hyster <<
192 type = <<
193 }; <<
194 }; <<
195 }; <<
196 <<
197 fman-thermal { <<
198 polling-delay-passive <<
199 polling-delay = <5000> <<
200 thermal-sensors = <&tm <<
201 <<
202 trips { <<
203 fman-alert { <<
204 temper <<
205 hyster <<
206 type = <<
207 }; <<
208 <<
209 fman-crit { <<
210 temper <<
211 hyster <<
212 type = <<
213 }; <<
214 }; <<
215 }; <<
216 <<
217 cluster-thermal { <<
218 polling-delay-passive <<
219 polling-delay = <5000> <<
220 thermal-sensors = <&tm <<
221 <<
222 trips { <<
223 core_cluster_a <<
224 temper <<
225 hyster <<
226 type = <<
227 }; <<
228 <<
229 core_cluster_c <<
230 temper <<
231 hyster <<
232 type = <<
233 }; <<
234 }; <<
235 <<
236 cooling-maps { <<
237 map0 { <<
238 trip = <<
239 coolin <<
240 <<
241 <<
242 <<
243 <<
244 }; <<
245 }; <<
246 }; <<
247 <<
248 sec-thermal { <<
249 polling-delay-passive <<
250 polling-delay = <5000> <<
251 thermal-sensors = <&tm <<
252 <<
253 trips { <<
254 sec-alert { <<
255 temper <<
256 hyster <<
257 type = <<
258 }; <<
259 <<
260 sec-crit { <<
261 temper <<
262 hyster <<
263 type = <<
264 }; <<
265 }; <<
266 }; <<
267 }; <<
268 <<
269 timer { 123 timer {
270 compatible = "arm,armv8-timer" 124 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 125 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 126 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 127 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 128 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 129 fsl,erratum-a008585;
276 }; 130 };
277 131
278 pmu { 132 pmu {
279 compatible = "arm,cortex-a53-p !! 133 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 134 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 135 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 136 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 137 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 138 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 139 <&cpu1>,
286 <&cpu2>, 140 <&cpu2>,
287 <&cpu3>; 141 <&cpu3>;
288 }; 142 };
289 143
290 gic: interrupt-controller@1400000 { 144 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 145 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 146 #interrupt-cells = <3>;
293 interrupt-controller; 147 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 148 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 149 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 150 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 151 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 152 interrupts = <1 9 0xf08>;
299 }; 153 };
300 154
301 soc: soc { !! 155 soc {
302 compatible = "simple-bus"; 156 compatible = "simple-bus";
303 #address-cells = <2>; 157 #address-cells = <2>;
304 #size-cells = <2>; 158 #size-cells = <2>;
305 ranges; 159 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 <<
307 dma-coherent; <<
308 160
309 clockgen: clocking@1ee1000 { 161 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 162 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 163 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 164 #clock-cells = <2>;
313 clocks = <&sysclk>; 165 clocks = <&sysclk>;
314 }; 166 };
315 167
316 scfg: scfg@1570000 { 168 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 169 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 170 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 171 big-endian;
320 #address-cells = <1>; <<
321 #size-cells = <1>; <<
322 ranges = <0x0 0x0 0x15 <<
323 <<
324 extirq: interrupt-cont <<
325 compatible = " <<
326 #interrupt-cel <<
327 #address-cells <<
328 interrupt-cont <<
329 reg = <0x1ac 4 <<
330 interrupt-map <<
331 <0 0 & <<
332 <1 0 & <<
333 <2 0 & <<
334 <3 0 & <<
335 <4 0 & <<
336 <5 0 & <<
337 <6 0 & <<
338 <7 0 & <<
339 <8 0 & <<
340 <9 0 & <<
341 <10 0 <<
342 <11 0 <<
343 interrupt-map- <<
344 }; <<
345 }; 172 };
346 173
347 crypto: crypto@1700000 { 174 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 175 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 176 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 177 fsl,sec-era = <3>;
351 #address-cells = <1>; 178 #address-cells = <1>;
352 #size-cells = <1>; 179 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 180 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 181 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 182 interrupts = <0 75 0x4>;
356 dma-coherent; <<
357 183
358 sec_jr0: jr@10000 { 184 sec_jr0: jr@10000 {
359 compatible = " 185 compatible = "fsl,sec-v5.4-job-ring",
360 " 186 "fsl,sec-v5.0-job-ring",
361 " 187 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 !! 188 reg = <0x10000 0x10000>;
363 interrupts = < !! 189 interrupts = <0 71 0x4>;
364 }; 190 };
365 191
366 sec_jr1: jr@20000 { 192 sec_jr1: jr@20000 {
367 compatible = " 193 compatible = "fsl,sec-v5.4-job-ring",
368 " 194 "fsl,sec-v5.0-job-ring",
369 " 195 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 !! 196 reg = <0x20000 0x10000>;
371 interrupts = < !! 197 interrupts = <0 72 0x4>;
372 }; 198 };
373 199
374 sec_jr2: jr@30000 { 200 sec_jr2: jr@30000 {
375 compatible = " 201 compatible = "fsl,sec-v5.4-job-ring",
376 " 202 "fsl,sec-v5.0-job-ring",
377 " 203 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 !! 204 reg = <0x30000 0x10000>;
379 interrupts = < !! 205 interrupts = <0 73 0x4>;
380 }; 206 };
381 207
382 sec_jr3: jr@40000 { 208 sec_jr3: jr@40000 {
383 compatible = " 209 compatible = "fsl,sec-v5.4-job-ring",
384 " 210 "fsl,sec-v5.0-job-ring",
385 " 211 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 !! 212 reg = <0x40000 0x10000>;
387 interrupts = < !! 213 interrupts = <0 74 0x4>;
388 }; 214 };
389 }; 215 };
390 216
391 sfp: efuse@1e80000 { <<
392 compatible = "fsl,ls10 <<
393 reg = <0x0 0x1e80000 0 <<
394 clocks = <&clockgen QO <<
395 QO <<
396 clock-names = "sfp"; <<
397 }; <<
398 <<
399 dcfg: dcfg@1ee0000 { 217 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 218 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 !! 219 reg = <0x0 0x1ee0000 0x0 0x10000>;
402 big-endian; 220 big-endian;
403 }; 221 };
404 222
405 ifc: memory-controller@1530000 !! 223 ifc: ifc@1530000 {
406 compatible = "fsl,ifc" !! 224 compatible = "fsl,ifc", "simple-bus";
407 reg = <0x0 0x1530000 0 225 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 226 interrupts = <0 43 0x4>;
409 }; 227 };
410 228
411 qspi: spi@1550000 { !! 229 qspi: quadspi@1550000 {
412 compatible = "fsl,ls10 230 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 231 #address-cells = <1>;
414 #size-cells = <0>; 232 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 233 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 234 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 235 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 236 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 237 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO !! 238 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
421 QO !! 239 big-endian;
422 <&clockgen QO <<
423 QO <<
424 status = "disabled"; 240 status = "disabled";
425 }; 241 };
426 242
427 esdhc: mmc@1560000 { !! 243 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 244 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 245 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 246 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 247 clock-frequency = <0>;
432 voltage-ranges = <1800 248 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 249 sdhci,auto-cmd12;
>> 250 big-endian;
434 bus-width = <4>; 251 bus-width = <4>;
435 }; 252 };
436 253
437 ddr: memory-controller@1080000 254 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 255 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 256 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 257 interrupts = <0 144 0x4>;
>> 258 big-endian;
441 }; 259 };
442 260
443 tmu: tmu@1f00000 { 261 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 262 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 263 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 264 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 !! 265 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
448 fsl,tmu-calibration = !! 266 fsl,tmu-calibration = <0x00000000 0x00000026
449 <0x000 !! 267 0x00000001 0x0000002d
450 <0x000 !! 268 0x00000002 0x00000032
451 <0x000 !! 269 0x00000003 0x00000039
452 <0x000 !! 270 0x00000004 0x0000003f
453 <0x000 !! 271 0x00000005 0x00000046
454 <0x000 !! 272 0x00000006 0x0000004d
455 <0x000 !! 273 0x00000007 0x00000054
456 <0x000 !! 274 0x00000008 0x0000005a
457 <0x000 !! 275 0x00000009 0x00000061
458 <0x000 !! 276 0x0000000a 0x0000006a
459 <0x000 !! 277 0x0000000b 0x00000071
460 <0x000 !! 278
461 !! 279 0x00010000 0x00000025
462 <0x000 !! 280 0x00010001 0x0000002c
463 <0x000 !! 281 0x00010002 0x00000035
464 <0x000 !! 282 0x00010003 0x0000003d
465 <0x000 !! 283 0x00010004 0x00000045
466 <0x000 !! 284 0x00010005 0x0000004e
467 <0x000 !! 285 0x00010006 0x00000057
468 <0x000 !! 286 0x00010007 0x00000061
469 <0x000 !! 287 0x00010008 0x0000006b
470 <0x000 !! 288 0x00010009 0x00000076
471 <0x000 !! 289
472 !! 290 0x00020000 0x00000029
473 <0x000 !! 291 0x00020001 0x00000033
474 <0x000 !! 292 0x00020002 0x0000003d
475 <0x000 !! 293 0x00020003 0x00000049
476 <0x000 !! 294 0x00020004 0x00000056
477 <0x000 !! 295 0x00020005 0x00000061
478 <0x000 !! 296 0x00020006 0x0000006d
479 <0x000 !! 297
480 !! 298 0x00030000 0x00000021
481 <0x000 !! 299 0x00030001 0x0000002a
482 <0x000 !! 300 0x00030002 0x0000003c
483 <0x000 !! 301 0x00030003 0x0000004e>;
484 <0x000 <<
485 <0x000 <<
486 <0x000 <<
487 <0x000 <<
488 <0x000 <<
489 #thermal-sensor-cells 302 #thermal-sensor-cells = <1>;
490 }; 303 };
491 304
492 qman: qman@1880000 { !! 305 thermal-zones {
493 compatible = "fsl,qman !! 306 cpu_thermal: cpu-thermal {
494 reg = <0x0 0x1880000 0 !! 307 polling-delay-passive = <1000>;
495 interrupts = <GIC_SPI !! 308 polling-delay = <5000>;
496 memory-region = <&qman !! 309
497 }; !! 310 thermal-sensors = <&tmu 3>;
498 !! 311
499 bman: bman@1890000 { !! 312 trips {
500 compatible = "fsl,bman !! 313 cpu_alert: cpu-alert {
501 reg = <0x0 0x1890000 0 !! 314 temperature = <85000>;
502 interrupts = <GIC_SPI !! 315 hysteresis = <2000>;
503 memory-region = <&bman !! 316 type = "passive";
504 }; !! 317 };
505 !! 318 cpu_crit: cpu-crit {
506 bportals: bman-portals-bus@508 !! 319 temperature = <95000>;
507 ranges = <0x0 0x5 0x08 !! 320 hysteresis = <2000>;
>> 321 type = "critical";
>> 322 };
>> 323 };
>> 324
>> 325 cooling-maps {
>> 326 map0 {
>> 327 trip = <&cpu_alert>;
>> 328 cooling-device =
>> 329 <&cpu0 THERMAL_NO_LIMIT
>> 330 THERMAL_NO_LIMIT>;
>> 331 };
>> 332 };
>> 333 };
508 }; 334 };
509 335
510 qportals: qman-portals-bus@500 !! 336 dspi0: dspi@2100000 {
511 ranges = <0x0 0x5 0x00 !! 337 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 338 #address-cells = <1>;
>> 339 #size-cells = <0>;
>> 340 reg = <0x0 0x2100000 0x0 0x10000>;
>> 341 interrupts = <0 64 0x4>;
>> 342 clock-names = "dspi";
>> 343 clocks = <&clockgen 4 0>;
>> 344 spi-num-chipselects = <5>;
>> 345 big-endian;
>> 346 status = "disabled";
512 }; 347 };
513 348
514 dspi0: spi@2100000 { !! 349 dspi1: dspi@2110000 {
515 compatible = "fsl,ls10 350 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 351 #address-cells = <1>;
517 #size-cells = <0>; 352 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 !! 353 reg = <0x0 0x2110000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 354 interrupts = <0 65 0x4>;
520 clock-names = "dspi"; 355 clock-names = "dspi";
521 clocks = <&clockgen QO !! 356 clocks = <&clockgen 4 0>;
522 QO <<
523 spi-num-chipselects = 357 spi-num-chipselects = <5>;
524 big-endian; 358 big-endian;
525 status = "disabled"; 359 status = "disabled";
526 }; 360 };
527 361
528 i2c0: i2c@2180000 { 362 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 !! 363 compatible = "fsl,vf610-i2c";
530 #address-cells = <1>; 364 #address-cells = <1>;
531 #size-cells = <0>; 365 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 366 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 367 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 368 clock-names = "i2c";
535 clocks = <&clockgen QO !! 369 clocks = <&clockgen 4 0>;
536 QO !! 370 dmas = <&edma0 1 39>,
537 dmas = <&edma0 1 38>, !! 371 <&edma0 1 38>;
538 <&edma0 1 39>; !! 372 dma-names = "tx", "rx";
539 dma-names = "rx", "tx" <<
540 status = "disabled"; 373 status = "disabled";
541 }; 374 };
542 375
543 i2c1: i2c@2190000 { 376 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 !! 377 compatible = "fsl,vf610-i2c";
545 #address-cells = <1>; 378 #address-cells = <1>;
546 #size-cells = <0>; 379 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 380 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 381 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 382 clock-names = "i2c";
550 clocks = <&clockgen QO !! 383 clocks = <&clockgen 4 0>;
551 QO <<
552 scl-gpios = <&gpio4 2 <<
553 status = "disabled"; 384 status = "disabled";
554 }; 385 };
555 386
556 i2c2: i2c@21a0000 { 387 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 !! 388 compatible = "fsl,vf610-i2c";
558 #address-cells = <1>; 389 #address-cells = <1>;
559 #size-cells = <0>; 390 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 391 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 392 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 393 clock-names = "i2c";
563 clocks = <&clockgen QO !! 394 clocks = <&clockgen 4 0>;
564 QO <<
565 scl-gpios = <&gpio4 10 <<
566 status = "disabled"; 395 status = "disabled";
567 }; 396 };
568 397
569 i2c3: i2c@21b0000 { 398 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 !! 399 compatible = "fsl,vf610-i2c";
571 #address-cells = <1>; 400 #address-cells = <1>;
572 #size-cells = <0>; 401 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 402 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 403 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 404 clock-names = "i2c";
576 clocks = <&clockgen QO !! 405 clocks = <&clockgen 4 0>;
577 QO <<
578 scl-gpios = <&gpio4 12 <<
579 status = "disabled"; 406 status = "disabled";
580 }; 407 };
581 408
582 duart0: serial@21c0500 { 409 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 410 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 411 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 412 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO !! 413 clocks = <&clockgen 4 0>;
587 QO <<
588 }; 414 };
589 415
590 duart1: serial@21c0600 { 416 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 417 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 418 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 419 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO !! 420 clocks = <&clockgen 4 0>;
595 QO <<
596 }; 421 };
597 422
598 duart2: serial@21d0500 { 423 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 424 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 425 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 426 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO !! 427 clocks = <&clockgen 4 0>;
603 QO <<
604 }; 428 };
605 429
606 duart3: serial@21d0600 { 430 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 431 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 432 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 433 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO !! 434 clocks = <&clockgen 4 0>;
611 QO <<
612 }; 435 };
613 436
614 gpio1: gpio@2300000 { 437 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 438 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 439 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 440 interrupts = <0 66 0x4>;
618 gpio-controller; 441 gpio-controller;
619 #gpio-cells = <2>; 442 #gpio-cells = <2>;
620 interrupt-controller; 443 interrupt-controller;
621 #interrupt-cells = <2> 444 #interrupt-cells = <2>;
622 }; 445 };
623 446
624 gpio2: gpio@2310000 { 447 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 448 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 449 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 450 interrupts = <0 67 0x4>;
628 gpio-controller; 451 gpio-controller;
629 #gpio-cells = <2>; 452 #gpio-cells = <2>;
630 interrupt-controller; 453 interrupt-controller;
631 #interrupt-cells = <2> 454 #interrupt-cells = <2>;
632 }; 455 };
633 456
634 gpio3: gpio@2320000 { 457 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 458 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 459 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 460 interrupts = <0 68 0x4>;
638 gpio-controller; 461 gpio-controller;
639 #gpio-cells = <2>; 462 #gpio-cells = <2>;
640 interrupt-controller; 463 interrupt-controller;
641 #interrupt-cells = <2> 464 #interrupt-cells = <2>;
642 }; 465 };
643 466
644 gpio4: gpio@2330000 { 467 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 468 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 469 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 470 interrupts = <0 134 0x4>;
648 gpio-controller; 471 gpio-controller;
649 #gpio-cells = <2>; 472 #gpio-cells = <2>;
650 interrupt-controller; 473 interrupt-controller;
651 #interrupt-cells = <2> 474 #interrupt-cells = <2>;
652 }; 475 };
653 476
654 uqe: uqe-bus@2400000 { <<
655 #address-cells = <1>; <<
656 #size-cells = <1>; <<
657 compatible = "fsl,qe", <<
658 ranges = <0x0 0x0 0x24 <<
659 reg = <0x0 0x2400000 0 <<
660 brg-frequency = <10000 <<
661 bus-frequency = <20000 <<
662 fsl,qe-num-riscs = <1> <<
663 fsl,qe-num-snums = <28 <<
664 <<
665 qeic: qeic@80 { <<
666 compatible = " <<
667 reg = <0x80 0x <<
668 interrupt-cont <<
669 #interrupt-cel <<
670 interrupts = < <<
671 < <<
672 }; <<
673 <<
674 si1: si@700 { <<
675 compatible = " <<
676 <<
677 reg = <0x700 0 <<
678 }; <<
679 <<
680 siram1: siram@1000 { <<
681 compatible = " <<
682 <<
683 reg = <0x1000 <<
684 }; <<
685 <<
686 ucc@2000 { <<
687 cell-index = < <<
688 reg = <0x2000 <<
689 interrupts = < <<
690 interrupt-pare <<
691 }; <<
692 <<
693 ucc@2200 { <<
694 cell-index = < <<
695 reg = <0x2200 <<
696 interrupts = < <<
697 interrupt-pare <<
698 }; <<
699 <<
700 muram@10000 { <<
701 #address-cells <<
702 #size-cells = <<
703 compatible = " <<
704 ranges = <0x0 <<
705 <<
706 data-only@0 { <<
707 compat <<
708 "fsl,c <<
709 reg = <<
710 }; <<
711 }; <<
712 }; <<
713 <<
714 lpuart0: serial@2950000 { 477 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 478 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 479 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 480 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO !! 481 clocks = <&clockgen 0 0>;
719 clock-names = "ipg"; 482 clock-names = "ipg";
720 status = "disabled"; 483 status = "disabled";
721 }; 484 };
722 485
723 lpuart1: serial@2960000 { 486 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 487 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 488 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 489 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO !! 490 clocks = <&clockgen 4 0>;
728 QO <<
729 clock-names = "ipg"; 491 clock-names = "ipg";
730 status = "disabled"; 492 status = "disabled";
731 }; 493 };
732 494
733 lpuart2: serial@2970000 { 495 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 496 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 497 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 498 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO !! 499 clocks = <&clockgen 4 0>;
738 QO <<
739 clock-names = "ipg"; 500 clock-names = "ipg";
740 status = "disabled"; 501 status = "disabled";
741 }; 502 };
742 503
743 lpuart3: serial@2980000 { 504 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 505 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 506 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 507 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO !! 508 clocks = <&clockgen 4 0>;
748 QO <<
749 clock-names = "ipg"; 509 clock-names = "ipg";
750 status = "disabled"; 510 status = "disabled";
751 }; 511 };
752 512
753 lpuart4: serial@2990000 { 513 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 514 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 515 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 516 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO !! 517 clocks = <&clockgen 4 0>;
758 QO <<
759 clock-names = "ipg"; 518 clock-names = "ipg";
760 status = "disabled"; 519 status = "disabled";
761 }; 520 };
762 521
763 lpuart5: serial@29a0000 { 522 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 523 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 524 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 525 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO !! 526 clocks = <&clockgen 4 0>;
768 QO <<
769 clock-names = "ipg"; 527 clock-names = "ipg";
770 status = "disabled"; 528 status = "disabled";
771 }; 529 };
772 530
773 wdog0: watchdog@2ad0000 { !! 531 wdog0: wdog@2ad0000 {
774 compatible = "fsl,ls10 532 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 533 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 534 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO !! 535 clocks = <&clockgen 4 0>;
778 QO !! 536 clock-names = "wdog";
779 big-endian; 537 big-endian;
780 }; 538 };
781 539
782 edma0: dma-controller@2c00000 !! 540 edma0: edma@2c00000 {
783 #dma-cells = <2>; 541 #dma-cells = <2>;
784 compatible = "fsl,vf61 542 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 543 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 544 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 545 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 546 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 547 <0 103 0x4>;
790 interrupt-names = "edm 548 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 549 dma-channels = <32>;
792 big-endian; 550 big-endian;
793 clock-names = "dmamux0 551 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO !! 552 clocks = <&clockgen 4 0>,
795 QO !! 553 <&clockgen 4 0>;
796 <&clockgen QO <<
797 QO <<
798 }; 554 };
799 555
800 aux_bus: bus { !! 556 usb0: usb3@2f00000 {
801 #address-cells = <2>; !! 557 compatible = "snps,dwc3";
802 #size-cells = <2>; !! 558 reg = <0x0 0x2f00000 0x0 0x10000>;
803 compatible = "simple-b !! 559 interrupts = <0 60 0x4>;
804 ranges; !! 560 dr_mode = "host";
805 dma-ranges = <0x0 0x0 !! 561 snps,quirk-frame-length-adjustment = <0x20>;
806 !! 562 snps,dis_rxdet_inp3_quirk;
807 usb0: usb@2f00000 { !! 563 };
808 compatible = " !! 564
809 reg = <0x0 0x2 !! 565 usb1: usb3@3000000 {
810 interrupts = < !! 566 compatible = "snps,dwc3";
811 dr_mode = "hos !! 567 reg = <0x0 0x3000000 0x0 0x10000>;
812 snps,quirk-fra !! 568 interrupts = <0 61 0x4>;
813 snps,dis_rxdet !! 569 dr_mode = "host";
814 usb3-lpm-capab !! 570 snps,quirk-frame-length-adjustment = <0x20>;
815 snps,incr-burs !! 571 snps,dis_rxdet_inp3_quirk;
816 status = "disa !! 572 };
817 }; !! 573
818 !! 574 usb2: usb3@3100000 {
819 usb1: usb@3000000 { !! 575 compatible = "snps,dwc3";
820 compatible = " !! 576 reg = <0x0 0x3100000 0x0 0x10000>;
821 reg = <0x0 0x3 !! 577 interrupts = <0 63 0x4>;
822 interrupts = < !! 578 dr_mode = "host";
823 dr_mode = "hos !! 579 snps,quirk-frame-length-adjustment = <0x20>;
824 snps,quirk-fra !! 580 snps,dis_rxdet_inp3_quirk;
825 snps,dis_rxdet !! 581 };
826 usb3-lpm-capab !! 582
827 snps,incr-burs !! 583 sata: sata@3200000 {
828 status = "disa !! 584 compatible = "fsl,ls1043a-ahci";
829 }; !! 585 reg = <0x0 0x3200000 0x0 0x10000>,
830 !! 586 <0x0 0x20140520 0x0 0x4>;
831 usb2: usb@3100000 { !! 587 reg-names = "ahci", "sata-ecc";
832 compatible = " !! 588 interrupts = <0 69 0x4>;
833 reg = <0x0 0x3 !! 589 clocks = <&clockgen 4 0>;
834 interrupts = < !! 590 dma-coherent;
835 dr_mode = "hos <<
836 snps,quirk-fra <<
837 snps,dis_rxdet <<
838 usb3-lpm-capab <<
839 snps,incr-burs <<
840 status = "disa <<
841 }; <<
842 <<
843 sata: sata@3200000 { <<
844 compatible = " <<
845 reg = <0x0 0x3 <<
846 <0x0 0 <<
847 reg-names = "a <<
848 interrupts = < <<
849 clocks = <&clo <<
850 <<
851 dma-coherent; <<
852 }; <<
853 }; 591 };
854 592
855 msi1: msi-controller1@1571000 593 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 !! 594 compatible = "fsl,1s1043a-msi";
857 reg = <0x0 0x1571000 0 595 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 596 msi-controller;
859 interrupts = <GIC_SPI !! 597 interrupts = <0 116 0x4>;
860 }; 598 };
861 599
862 msi2: msi-controller2@1572000 600 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 !! 601 compatible = "fsl,1s1043a-msi";
864 reg = <0x0 0x1572000 0 602 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 603 msi-controller;
866 interrupts = <GIC_SPI !! 604 interrupts = <0 126 0x4>;
867 }; 605 };
868 606
869 msi3: msi-controller3@1573000 607 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 !! 608 compatible = "fsl,1s1043a-msi";
871 reg = <0x0 0x1573000 0 609 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 610 msi-controller;
873 interrupts = <GIC_SPI !! 611 interrupts = <0 160 0x4>;
874 }; 612 };
875 613
876 pcie1: pcie@3400000 { !! 614 pcie@3400000 {
877 compatible = "fsl,ls10 !! 615 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
878 reg = <0x00 0x03400000 !! 616 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
879 <0x40 0x00000000 !! 617 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 618 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 619 interrupts = <0 118 0x4>, /* controller interrupt */
882 <GIC_SPI !! 620 <0 117 0x4>; /* PME interrupt */
883 interrupt-names = "pme !! 621 interrupt-names = "intr", "pme";
884 #address-cells = <3>; 622 #address-cells = <3>;
885 #size-cells = <2>; 623 #size-cells = <2>;
886 device_type = "pci"; 624 device_type = "pci";
887 num-viewport = <6>; !! 625 dma-coherent;
>> 626 num-lanes = <4>;
888 bus-range = <0x0 0xff> 627 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 628 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 629 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, !! 630 msi-parent = <&msi1>;
892 #interrupt-cells = <1> 631 #interrupt-cells = <1>;
893 interrupt-map-mask = < 632 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 633 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 634 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 635 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 636 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg <<
899 big-endian; <<
900 status = "disabled"; <<
901 }; 637 };
902 638
903 pcie2: pcie@3500000 { !! 639 pcie@3500000 {
904 compatible = "fsl,ls10 !! 640 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
905 reg = <0x00 0x03500000 !! 641 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
906 <0x48 0x00000000 !! 642 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 643 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 644 interrupts = <0 128 0x4>,
909 <GIC_SPI !! 645 <0 127 0x4>;
910 interrupt-names = "pme !! 646 interrupt-names = "intr", "pme";
911 #address-cells = <3>; 647 #address-cells = <3>;
912 #size-cells = <2>; 648 #size-cells = <2>;
913 device_type = "pci"; 649 device_type = "pci";
914 num-viewport = <6>; !! 650 dma-coherent;
>> 651 num-lanes = <2>;
915 bus-range = <0x0 0xff> 652 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 653 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 654 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, !! 655 msi-parent = <&msi2>;
919 #interrupt-cells = <1> 656 #interrupt-cells = <1>;
920 interrupt-map-mask = < 657 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 658 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 659 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 660 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 661 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg <<
926 big-endian; <<
927 status = "disabled"; <<
928 }; 662 };
929 663
930 pcie3: pcie@3600000 { !! 664 pcie@3600000 {
931 compatible = "fsl,ls10 !! 665 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
932 reg = <0x00 0x03600000 !! 666 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
933 <0x50 0x00000000 !! 667 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 668 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 669 interrupts = <0 162 0x4>,
936 <GIC_SPI !! 670 <0 161 0x4>;
937 interrupt-names = "pme !! 671 interrupt-names = "intr", "pme";
938 #address-cells = <3>; 672 #address-cells = <3>;
939 #size-cells = <2>; 673 #size-cells = <2>;
940 device_type = "pci"; 674 device_type = "pci";
941 num-viewport = <6>; !! 675 dma-coherent;
>> 676 num-lanes = <2>;
942 bus-range = <0x0 0xff> 677 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 678 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 679 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, !! 680 msi-parent = <&msi3>;
946 #interrupt-cells = <1> 681 #interrupt-cells = <1>;
947 interrupt-map-mask = < 682 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 683 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 684 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 685 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 686 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg <<
953 big-endian; <<
954 status = "disabled"; <<
955 }; <<
956 <<
957 qdma: dma-controller@8380000 { <<
958 compatible = "fsl,ls10 <<
959 reg = <0x0 0x8380000 0 <<
960 <0x0 0x8390000 0 <<
961 <0x0 0x83a0000 0 <<
962 interrupts = <GIC_SPI <<
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 interrupt-names = "qdm <<
968 "qdma-queue1", <<
969 #dma-cells = <1>; <<
970 dma-channels = <8>; <<
971 block-number = <1>; <<
972 block-offset = <0x1000 <<
973 fsl,dma-queues = <2>; <<
974 status-sizes = <64>; <<
975 queue-sizes = <64 64>; <<
976 big-endian; <<
977 }; <<
978 <<
979 rcpm: wakeup-controller@1ee214 <<
980 compatible = "fsl,ls10 <<
981 reg = <0x0 0x1ee2140 0 <<
982 #fsl,rcpm-wakeup-cells <<
983 }; <<
984 <<
985 ftm_alarm0: rtc@29d0000 { <<
986 compatible = "fsl,ls10 <<
987 reg = <0x0 0x29d0000 0 <<
988 fsl,rcpm-wakeup = <&rc <<
989 interrupts = <GIC_SPI <<
990 big-endian; <<
991 }; <<
992 }; <<
993 <<
994 firmware { <<
995 optee { <<
996 compatible = "linaro,o <<
997 method = "smc"; <<
998 }; 687 };
999 }; 688 };
1000 689
1001 }; 690 };
1002 <<
1003 #include "qoriq-qman-portals.dtsi" <<
1004 #include "qoriq-bman-portals.dtsi" <<
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