1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Device Tree Include file for NXP Layerscape !! 2 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * 3 *
5 * Copyright 2014-2015 Freescale Semiconductor 4 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP <<
7 * 5 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 6 * Mingkai Hu <Mingkai.hu@freescale.com>
>> 7 *
>> 8 * This file is dual-licensed: you can use it either under the terms
>> 9 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 10 * licensing only applies to this file, and not this project as a
>> 11 * whole.
>> 12 *
>> 13 * a) This library is free software; you can redistribute it and/or
>> 14 * modify it under the terms of the GNU General Public License as
>> 15 * published by the Free Software Foundation; either version 2 of the
>> 16 * License, or (at your option) any later version.
>> 17 *
>> 18 * This library is distributed in the hope that it will be useful,
>> 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 21 * GNU General Public License for more details.
>> 22 *
>> 23 * Or, alternatively,
>> 24 *
>> 25 * b) Permission is hereby granted, free of charge, to any person
>> 26 * obtaining a copy of this software and associated documentation
>> 27 * files (the "Software"), to deal in the Software without
>> 28 * restriction, including without limitation the rights to use,
>> 29 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 30 * sell copies of the Software, and to permit persons to whom the
>> 31 * Software is furnished to do so, subject to the following
>> 32 * conditions:
>> 33 *
>> 34 * The above copyright notice and this permission notice shall be
>> 35 * included in all copies or substantial portions of the Software.
>> 36 *
>> 37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 44 * OTHER DEALINGS IN THE SOFTWARE.
9 */ 45 */
10 46
11 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
12 #include <dt-bindings/thermal/thermal.h> 47 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 48 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> <<
15 49
16 / { 50 / {
17 compatible = "fsl,ls1043a"; 51 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 52 interrupt-parent = <&gic>;
19 #address-cells = <2>; 53 #address-cells = <2>;
20 #size-cells = <2>; 54 #size-cells = <2>;
21 55
22 aliases { 56 aliases {
23 crypto = &crypto; <<
24 fman0 = &fman0; 57 fman0 = &fman0;
25 ethernet0 = &enet0; 58 ethernet0 = &enet0;
26 ethernet1 = &enet1; 59 ethernet1 = &enet1;
27 ethernet2 = &enet2; 60 ethernet2 = &enet2;
28 ethernet3 = &enet3; 61 ethernet3 = &enet3;
29 ethernet4 = &enet4; 62 ethernet4 = &enet4;
30 ethernet5 = &enet5; 63 ethernet5 = &enet5;
31 ethernet6 = &enet6; 64 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; <<
33 }; 65 };
34 66
35 cpus { 67 cpus {
36 #address-cells = <1>; 68 #address-cells = <1>;
37 #size-cells = <0>; 69 #size-cells = <0>;
38 70
39 /* 71 /*
40 * We expect the enable-method 72 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 73 * is dependent on the SoC FW, which will fill this in.
42 * 74 *
43 * Currently supported enable- 75 * Currently supported enable-method is psci v0.2
44 */ 76 */
45 cpu0: cpu@0 { 77 cpu0: cpu@0 {
46 device_type = "cpu"; 78 device_type = "cpu";
47 compatible = "arm,cort 79 compatible = "arm,cortex-a53";
48 reg = <0x0>; 80 reg = <0x0>;
49 clocks = <&clockgen QO !! 81 clocks = <&clockgen 1 0>;
50 next-level-cache = <&l 82 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP <<
52 #cooling-cells = <2>; 83 #cooling-cells = <2>;
53 }; 84 };
54 85
55 cpu1: cpu@1 { 86 cpu1: cpu@1 {
56 device_type = "cpu"; 87 device_type = "cpu";
57 compatible = "arm,cort 88 compatible = "arm,cortex-a53";
58 reg = <0x1>; 89 reg = <0x1>;
59 clocks = <&clockgen QO !! 90 clocks = <&clockgen 1 0>;
60 next-level-cache = <&l 91 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP <<
62 #cooling-cells = <2>; <<
63 }; 92 };
64 93
65 cpu2: cpu@2 { 94 cpu2: cpu@2 {
66 device_type = "cpu"; 95 device_type = "cpu";
67 compatible = "arm,cort 96 compatible = "arm,cortex-a53";
68 reg = <0x2>; 97 reg = <0x2>;
69 clocks = <&clockgen QO !! 98 clocks = <&clockgen 1 0>;
70 next-level-cache = <&l 99 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP <<
72 #cooling-cells = <2>; <<
73 }; 100 };
74 101
75 cpu3: cpu@3 { 102 cpu3: cpu@3 {
76 device_type = "cpu"; 103 device_type = "cpu";
77 compatible = "arm,cort 104 compatible = "arm,cortex-a53";
78 reg = <0x3>; 105 reg = <0x3>;
79 clocks = <&clockgen QO !! 106 clocks = <&clockgen 1 0>;
80 next-level-cache = <&l 107 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP <<
82 #cooling-cells = <2>; <<
83 }; 108 };
84 109
85 l2: l2-cache { 110 l2: l2-cache {
86 compatible = "cache"; 111 compatible = "cache";
87 cache-level = <2>; <<
88 cache-unified; <<
89 }; <<
90 }; <<
91 <<
92 idle-states { <<
93 /* <<
94 * PSCI node is not added defa <<
95 * parts if it determines to u <<
96 */ <<
97 entry-method = "psci"; <<
98 <<
99 CPU_PH20: cpu-ph20 { <<
100 compatible = "arm,idle <<
101 idle-state-name = "PH2 <<
102 arm,psci-suspend-param <<
103 entry-latency-us = <10 <<
104 exit-latency-us = <100 <<
105 min-residency-us = <30 <<
106 }; 112 };
107 }; 113 };
108 114
109 memory@80000000 { 115 memory@80000000 {
110 device_type = "memory"; 116 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 117 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 118 /* DRAM space 1, size: 2GiB DRAM */
113 }; 119 };
114 120
115 reserved-memory { 121 reserved-memory {
116 #address-cells = <2>; 122 #address-cells = <2>;
117 #size-cells = <2>; 123 #size-cells = <2>;
118 ranges; 124 ranges;
119 125
120 bman_fbpr: bman-fbpr { 126 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 127 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 128 size = <0 0x1000000>;
123 alignment = <0 0x10000 129 alignment = <0 0x1000000>;
124 no-map; 130 no-map;
125 }; 131 };
126 132
127 qman_fqd: qman-fqd { 133 qman_fqd: qman-fqd {
128 compatible = "shared-d 134 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 135 size = <0 0x400000>;
130 alignment = <0 0x40000 136 alignment = <0 0x400000>;
131 no-map; 137 no-map;
132 }; 138 };
133 139
134 qman_pfdr: qman-pfdr { 140 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 141 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 142 size = <0 0x2000000>;
137 alignment = <0 0x20000 143 alignment = <0 0x2000000>;
138 no-map; 144 no-map;
139 }; 145 };
140 }; 146 };
141 147
142 sysclk: sysclk { 148 sysclk: sysclk {
143 compatible = "fixed-clock"; 149 compatible = "fixed-clock";
144 #clock-cells = <0>; 150 #clock-cells = <0>;
145 clock-frequency = <100000000>; 151 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 152 clock-output-names = "sysclk";
147 }; 153 };
148 154
149 reboot { 155 reboot {
150 compatible = "syscon-reboot"; !! 156 compatible ="syscon-reboot";
151 regmap = <&dcfg>; 157 regmap = <&dcfg>;
152 offset = <0xb0>; 158 offset = <0xb0>;
153 mask = <0x02>; 159 mask = <0x02>;
154 }; 160 };
155 161
156 thermal-zones { <<
157 ddr-thermal { <<
158 polling-delay-passive <<
159 polling-delay = <5000> <<
160 thermal-sensors = <&tm <<
161 <<
162 trips { <<
163 ddr-ctrler-ale <<
164 temper <<
165 hyster <<
166 type = <<
167 }; <<
168 <<
169 ddr-ctrler-cri <<
170 temper <<
171 hyster <<
172 type = <<
173 }; <<
174 }; <<
175 }; <<
176 <<
177 serdes-thermal { <<
178 polling-delay-passive <<
179 polling-delay = <5000> <<
180 thermal-sensors = <&tm <<
181 <<
182 trips { <<
183 serdes-alert { <<
184 temper <<
185 hyster <<
186 type = <<
187 }; <<
188 <<
189 serdes-crit { <<
190 temper <<
191 hyster <<
192 type = <<
193 }; <<
194 }; <<
195 }; <<
196 <<
197 fman-thermal { <<
198 polling-delay-passive <<
199 polling-delay = <5000> <<
200 thermal-sensors = <&tm <<
201 <<
202 trips { <<
203 fman-alert { <<
204 temper <<
205 hyster <<
206 type = <<
207 }; <<
208 <<
209 fman-crit { <<
210 temper <<
211 hyster <<
212 type = <<
213 }; <<
214 }; <<
215 }; <<
216 <<
217 cluster-thermal { <<
218 polling-delay-passive <<
219 polling-delay = <5000> <<
220 thermal-sensors = <&tm <<
221 <<
222 trips { <<
223 core_cluster_a <<
224 temper <<
225 hyster <<
226 type = <<
227 }; <<
228 <<
229 core_cluster_c <<
230 temper <<
231 hyster <<
232 type = <<
233 }; <<
234 }; <<
235 <<
236 cooling-maps { <<
237 map0 { <<
238 trip = <<
239 coolin <<
240 <<
241 <<
242 <<
243 <<
244 }; <<
245 }; <<
246 }; <<
247 <<
248 sec-thermal { <<
249 polling-delay-passive <<
250 polling-delay = <5000> <<
251 thermal-sensors = <&tm <<
252 <<
253 trips { <<
254 sec-alert { <<
255 temper <<
256 hyster <<
257 type = <<
258 }; <<
259 <<
260 sec-crit { <<
261 temper <<
262 hyster <<
263 type = <<
264 }; <<
265 }; <<
266 }; <<
267 }; <<
268 <<
269 timer { 162 timer {
270 compatible = "arm,armv8-timer" 163 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 164 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 165 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 166 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 167 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 168 fsl,erratum-a008585;
276 }; 169 };
277 170
278 pmu { 171 pmu {
279 compatible = "arm,cortex-a53-p !! 172 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 173 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 174 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 175 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 176 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 177 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 178 <&cpu1>,
286 <&cpu2>, 179 <&cpu2>,
287 <&cpu3>; 180 <&cpu3>;
288 }; 181 };
289 182
290 gic: interrupt-controller@1400000 { 183 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 184 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 185 #interrupt-cells = <3>;
293 interrupt-controller; 186 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 187 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 188 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 189 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 190 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 191 interrupts = <1 9 0xf08>;
299 }; 192 };
300 193
301 soc: soc { 194 soc: soc {
302 compatible = "simple-bus"; 195 compatible = "simple-bus";
303 #address-cells = <2>; 196 #address-cells = <2>;
304 #size-cells = <2>; 197 #size-cells = <2>;
305 ranges; 198 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 <<
307 dma-coherent; <<
308 199
309 clockgen: clocking@1ee1000 { 200 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 201 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 202 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 203 #clock-cells = <2>;
313 clocks = <&sysclk>; 204 clocks = <&sysclk>;
314 }; 205 };
315 206
316 scfg: scfg@1570000 { 207 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 208 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 209 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 210 big-endian;
320 #address-cells = <1>; <<
321 #size-cells = <1>; <<
322 ranges = <0x0 0x0 0x15 <<
323 <<
324 extirq: interrupt-cont <<
325 compatible = " <<
326 #interrupt-cel <<
327 #address-cells <<
328 interrupt-cont <<
329 reg = <0x1ac 4 <<
330 interrupt-map <<
331 <0 0 & <<
332 <1 0 & <<
333 <2 0 & <<
334 <3 0 & <<
335 <4 0 & <<
336 <5 0 & <<
337 <6 0 & <<
338 <7 0 & <<
339 <8 0 & <<
340 <9 0 & <<
341 <10 0 <<
342 <11 0 <<
343 interrupt-map- <<
344 }; <<
345 }; 211 };
346 212
347 crypto: crypto@1700000 { 213 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 214 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 215 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 216 fsl,sec-era = <3>;
351 #address-cells = <1>; 217 #address-cells = <1>;
352 #size-cells = <1>; 218 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 219 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 220 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 221 interrupts = <0 75 0x4>;
356 dma-coherent; <<
357 222
358 sec_jr0: jr@10000 { 223 sec_jr0: jr@10000 {
359 compatible = " 224 compatible = "fsl,sec-v5.4-job-ring",
360 " 225 "fsl,sec-v5.0-job-ring",
361 " 226 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 !! 227 reg = <0x10000 0x10000>;
363 interrupts = < !! 228 interrupts = <0 71 0x4>;
364 }; 229 };
365 230
366 sec_jr1: jr@20000 { 231 sec_jr1: jr@20000 {
367 compatible = " 232 compatible = "fsl,sec-v5.4-job-ring",
368 " 233 "fsl,sec-v5.0-job-ring",
369 " 234 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 !! 235 reg = <0x20000 0x10000>;
371 interrupts = < !! 236 interrupts = <0 72 0x4>;
372 }; 237 };
373 238
374 sec_jr2: jr@30000 { 239 sec_jr2: jr@30000 {
375 compatible = " 240 compatible = "fsl,sec-v5.4-job-ring",
376 " 241 "fsl,sec-v5.0-job-ring",
377 " 242 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 !! 243 reg = <0x30000 0x10000>;
379 interrupts = < !! 244 interrupts = <0 73 0x4>;
380 }; 245 };
381 246
382 sec_jr3: jr@40000 { 247 sec_jr3: jr@40000 {
383 compatible = " 248 compatible = "fsl,sec-v5.4-job-ring",
384 " 249 "fsl,sec-v5.0-job-ring",
385 " 250 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 !! 251 reg = <0x40000 0x10000>;
387 interrupts = < !! 252 interrupts = <0 74 0x4>;
388 }; 253 };
389 }; 254 };
390 255
391 sfp: efuse@1e80000 { <<
392 compatible = "fsl,ls10 <<
393 reg = <0x0 0x1e80000 0 <<
394 clocks = <&clockgen QO <<
395 QO <<
396 clock-names = "sfp"; <<
397 }; <<
398 <<
399 dcfg: dcfg@1ee0000 { 256 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 257 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 !! 258 reg = <0x0 0x1ee0000 0x0 0x10000>;
402 big-endian; 259 big-endian;
403 }; 260 };
404 261
405 ifc: memory-controller@1530000 !! 262 ifc: ifc@1530000 {
406 compatible = "fsl,ifc" !! 263 compatible = "fsl,ifc", "simple-bus";
407 reg = <0x0 0x1530000 0 264 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 265 big-endian;
>> 266 interrupts = <0 43 0x4>;
409 }; 267 };
410 268
411 qspi: spi@1550000 { !! 269 qspi: quadspi@1550000 {
412 compatible = "fsl,ls10 270 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 271 #address-cells = <1>;
414 #size-cells = <0>; 272 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 273 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 274 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 275 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 276 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 277 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO !! 278 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
421 QO !! 279 big-endian;
422 <&clockgen QO <<
423 QO <<
424 status = "disabled"; 280 status = "disabled";
425 }; 281 };
426 282
427 esdhc: mmc@1560000 { !! 283 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 284 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 285 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 286 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 287 clock-frequency = <0>;
432 voltage-ranges = <1800 288 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 289 sdhci,auto-cmd12;
>> 290 big-endian;
434 bus-width = <4>; 291 bus-width = <4>;
435 }; 292 };
436 293
437 ddr: memory-controller@1080000 294 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 295 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 296 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 297 interrupts = <0 144 0x4>;
>> 298 big-endian;
441 }; 299 };
442 300
443 tmu: tmu@1f00000 { 301 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 302 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 303 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 304 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 !! 305 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
448 fsl,tmu-calibration = !! 306 fsl,tmu-calibration = <0x00000000 0x00000026
449 <0x000 !! 307 0x00000001 0x0000002d
450 <0x000 !! 308 0x00000002 0x00000032
451 <0x000 !! 309 0x00000003 0x00000039
452 <0x000 !! 310 0x00000004 0x0000003f
453 <0x000 !! 311 0x00000005 0x00000046
454 <0x000 !! 312 0x00000006 0x0000004d
455 <0x000 !! 313 0x00000007 0x00000054
456 <0x000 !! 314 0x00000008 0x0000005a
457 <0x000 !! 315 0x00000009 0x00000061
458 <0x000 !! 316 0x0000000a 0x0000006a
459 <0x000 !! 317 0x0000000b 0x00000071
460 <0x000 !! 318
461 !! 319 0x00010000 0x00000025
462 <0x000 !! 320 0x00010001 0x0000002c
463 <0x000 !! 321 0x00010002 0x00000035
464 <0x000 !! 322 0x00010003 0x0000003d
465 <0x000 !! 323 0x00010004 0x00000045
466 <0x000 !! 324 0x00010005 0x0000004e
467 <0x000 !! 325 0x00010006 0x00000057
468 <0x000 !! 326 0x00010007 0x00000061
469 <0x000 !! 327 0x00010008 0x0000006b
470 <0x000 !! 328 0x00010009 0x00000076
471 <0x000 !! 329
472 !! 330 0x00020000 0x00000029
473 <0x000 !! 331 0x00020001 0x00000033
474 <0x000 !! 332 0x00020002 0x0000003d
475 <0x000 !! 333 0x00020003 0x00000049
476 <0x000 !! 334 0x00020004 0x00000056
477 <0x000 !! 335 0x00020005 0x00000061
478 <0x000 !! 336 0x00020006 0x0000006d
479 <0x000 !! 337
480 !! 338 0x00030000 0x00000021
481 <0x000 !! 339 0x00030001 0x0000002a
482 <0x000 !! 340 0x00030002 0x0000003c
483 <0x000 !! 341 0x00030003 0x0000004e>;
484 <0x000 <<
485 <0x000 <<
486 <0x000 <<
487 <0x000 <<
488 <0x000 <<
489 #thermal-sensor-cells 342 #thermal-sensor-cells = <1>;
490 }; 343 };
491 344
>> 345 thermal-zones {
>> 346 cpu_thermal: cpu-thermal {
>> 347 polling-delay-passive = <1000>;
>> 348 polling-delay = <5000>;
>> 349
>> 350 thermal-sensors = <&tmu 3>;
>> 351
>> 352 trips {
>> 353 cpu_alert: cpu-alert {
>> 354 temperature = <85000>;
>> 355 hysteresis = <2000>;
>> 356 type = "passive";
>> 357 };
>> 358 cpu_crit: cpu-crit {
>> 359 temperature = <95000>;
>> 360 hysteresis = <2000>;
>> 361 type = "critical";
>> 362 };
>> 363 };
>> 364
>> 365 cooling-maps {
>> 366 map0 {
>> 367 trip = <&cpu_alert>;
>> 368 cooling-device =
>> 369 <&cpu0 THERMAL_NO_LIMIT
>> 370 THERMAL_NO_LIMIT>;
>> 371 };
>> 372 };
>> 373 };
>> 374 };
>> 375
492 qman: qman@1880000 { 376 qman: qman@1880000 {
493 compatible = "fsl,qman 377 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 378 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 379 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 380 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 381 };
498 382
499 bman: bman@1890000 { 383 bman: bman@1890000 {
500 compatible = "fsl,bman 384 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 385 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 386 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 387 memory-region = <&bman_fbpr>;
504 }; 388 };
505 389
506 bportals: bman-portals-bus@508 !! 390 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 391 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 392 };
509 393
510 qportals: qman-portals-bus@500 !! 394 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 395 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 396 };
513 397
514 dspi0: spi@2100000 { !! 398 dspi0: dspi@2100000 {
515 compatible = "fsl,ls10 399 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 400 #address-cells = <1>;
517 #size-cells = <0>; 401 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 402 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 403 interrupts = <0 64 0x4>;
520 clock-names = "dspi"; 404 clock-names = "dspi";
521 clocks = <&clockgen QO !! 405 clocks = <&clockgen 4 0>;
522 QO !! 406 spi-num-chipselects = <5>;
>> 407 big-endian;
>> 408 status = "disabled";
>> 409 };
>> 410
>> 411 dspi1: dspi@2110000 {
>> 412 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 413 #address-cells = <1>;
>> 414 #size-cells = <0>;
>> 415 reg = <0x0 0x2110000 0x0 0x10000>;
>> 416 interrupts = <0 65 0x4>;
>> 417 clock-names = "dspi";
>> 418 clocks = <&clockgen 4 0>;
523 spi-num-chipselects = 419 spi-num-chipselects = <5>;
524 big-endian; 420 big-endian;
525 status = "disabled"; 421 status = "disabled";
526 }; 422 };
527 423
528 i2c0: i2c@2180000 { 424 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 !! 425 compatible = "fsl,vf610-i2c";
530 #address-cells = <1>; 426 #address-cells = <1>;
531 #size-cells = <0>; 427 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 428 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 429 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 430 clock-names = "i2c";
535 clocks = <&clockgen QO !! 431 clocks = <&clockgen 4 0>;
536 QO !! 432 dmas = <&edma0 1 39>,
537 dmas = <&edma0 1 38>, !! 433 <&edma0 1 38>;
538 <&edma0 1 39>; !! 434 dma-names = "tx", "rx";
539 dma-names = "rx", "tx" <<
540 status = "disabled"; 435 status = "disabled";
541 }; 436 };
542 437
543 i2c1: i2c@2190000 { 438 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 !! 439 compatible = "fsl,vf610-i2c";
545 #address-cells = <1>; 440 #address-cells = <1>;
546 #size-cells = <0>; 441 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 442 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 443 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 444 clock-names = "i2c";
550 clocks = <&clockgen QO !! 445 clocks = <&clockgen 4 0>;
551 QO <<
552 scl-gpios = <&gpio4 2 <<
553 status = "disabled"; 446 status = "disabled";
554 }; 447 };
555 448
556 i2c2: i2c@21a0000 { 449 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 !! 450 compatible = "fsl,vf610-i2c";
558 #address-cells = <1>; 451 #address-cells = <1>;
559 #size-cells = <0>; 452 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 453 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 454 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 455 clock-names = "i2c";
563 clocks = <&clockgen QO !! 456 clocks = <&clockgen 4 0>;
564 QO <<
565 scl-gpios = <&gpio4 10 <<
566 status = "disabled"; 457 status = "disabled";
567 }; 458 };
568 459
569 i2c3: i2c@21b0000 { 460 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 !! 461 compatible = "fsl,vf610-i2c";
571 #address-cells = <1>; 462 #address-cells = <1>;
572 #size-cells = <0>; 463 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 464 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 465 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 466 clock-names = "i2c";
576 clocks = <&clockgen QO !! 467 clocks = <&clockgen 4 0>;
577 QO <<
578 scl-gpios = <&gpio4 12 <<
579 status = "disabled"; 468 status = "disabled";
580 }; 469 };
581 470
582 duart0: serial@21c0500 { 471 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 472 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 473 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 474 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO !! 475 clocks = <&clockgen 4 0>;
587 QO <<
588 }; 476 };
589 477
590 duart1: serial@21c0600 { 478 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 479 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 480 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 481 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO !! 482 clocks = <&clockgen 4 0>;
595 QO <<
596 }; 483 };
597 484
598 duart2: serial@21d0500 { 485 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 486 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 487 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 488 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO !! 489 clocks = <&clockgen 4 0>;
603 QO <<
604 }; 490 };
605 491
606 duart3: serial@21d0600 { 492 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 493 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 494 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 495 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO !! 496 clocks = <&clockgen 4 0>;
611 QO <<
612 }; 497 };
613 498
614 gpio1: gpio@2300000 { 499 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 500 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 501 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 502 interrupts = <0 66 0x4>;
618 gpio-controller; 503 gpio-controller;
619 #gpio-cells = <2>; 504 #gpio-cells = <2>;
620 interrupt-controller; 505 interrupt-controller;
621 #interrupt-cells = <2> 506 #interrupt-cells = <2>;
622 }; 507 };
623 508
624 gpio2: gpio@2310000 { 509 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 510 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 511 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 512 interrupts = <0 67 0x4>;
628 gpio-controller; 513 gpio-controller;
629 #gpio-cells = <2>; 514 #gpio-cells = <2>;
630 interrupt-controller; 515 interrupt-controller;
631 #interrupt-cells = <2> 516 #interrupt-cells = <2>;
632 }; 517 };
633 518
634 gpio3: gpio@2320000 { 519 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 520 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 521 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 522 interrupts = <0 68 0x4>;
638 gpio-controller; 523 gpio-controller;
639 #gpio-cells = <2>; 524 #gpio-cells = <2>;
640 interrupt-controller; 525 interrupt-controller;
641 #interrupt-cells = <2> 526 #interrupt-cells = <2>;
642 }; 527 };
643 528
644 gpio4: gpio@2330000 { 529 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 530 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 531 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 532 interrupts = <0 134 0x4>;
648 gpio-controller; 533 gpio-controller;
649 #gpio-cells = <2>; 534 #gpio-cells = <2>;
650 interrupt-controller; 535 interrupt-controller;
651 #interrupt-cells = <2> 536 #interrupt-cells = <2>;
652 }; 537 };
653 538
654 uqe: uqe-bus@2400000 { <<
655 #address-cells = <1>; <<
656 #size-cells = <1>; <<
657 compatible = "fsl,qe", <<
658 ranges = <0x0 0x0 0x24 <<
659 reg = <0x0 0x2400000 0 <<
660 brg-frequency = <10000 <<
661 bus-frequency = <20000 <<
662 fsl,qe-num-riscs = <1> <<
663 fsl,qe-num-snums = <28 <<
664 <<
665 qeic: qeic@80 { <<
666 compatible = " <<
667 reg = <0x80 0x <<
668 interrupt-cont <<
669 #interrupt-cel <<
670 interrupts = < <<
671 < <<
672 }; <<
673 <<
674 si1: si@700 { <<
675 compatible = " <<
676 <<
677 reg = <0x700 0 <<
678 }; <<
679 <<
680 siram1: siram@1000 { <<
681 compatible = " <<
682 <<
683 reg = <0x1000 <<
684 }; <<
685 <<
686 ucc@2000 { <<
687 cell-index = < <<
688 reg = <0x2000 <<
689 interrupts = < <<
690 interrupt-pare <<
691 }; <<
692 <<
693 ucc@2200 { <<
694 cell-index = < <<
695 reg = <0x2200 <<
696 interrupts = < <<
697 interrupt-pare <<
698 }; <<
699 <<
700 muram@10000 { <<
701 #address-cells <<
702 #size-cells = <<
703 compatible = " <<
704 ranges = <0x0 <<
705 <<
706 data-only@0 { <<
707 compat <<
708 "fsl,c <<
709 reg = <<
710 }; <<
711 }; <<
712 }; <<
713 <<
714 lpuart0: serial@2950000 { 539 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 540 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 541 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 542 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO !! 543 clocks = <&clockgen 0 0>;
719 clock-names = "ipg"; 544 clock-names = "ipg";
720 status = "disabled"; 545 status = "disabled";
721 }; 546 };
722 547
723 lpuart1: serial@2960000 { 548 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 549 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 550 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 551 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO !! 552 clocks = <&clockgen 4 0>;
728 QO <<
729 clock-names = "ipg"; 553 clock-names = "ipg";
730 status = "disabled"; 554 status = "disabled";
731 }; 555 };
732 556
733 lpuart2: serial@2970000 { 557 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 558 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 559 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 560 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO !! 561 clocks = <&clockgen 4 0>;
738 QO <<
739 clock-names = "ipg"; 562 clock-names = "ipg";
740 status = "disabled"; 563 status = "disabled";
741 }; 564 };
742 565
743 lpuart3: serial@2980000 { 566 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 567 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 568 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 569 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO !! 570 clocks = <&clockgen 4 0>;
748 QO <<
749 clock-names = "ipg"; 571 clock-names = "ipg";
750 status = "disabled"; 572 status = "disabled";
751 }; 573 };
752 574
753 lpuart4: serial@2990000 { 575 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 576 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 577 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 578 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO !! 579 clocks = <&clockgen 4 0>;
758 QO <<
759 clock-names = "ipg"; 580 clock-names = "ipg";
760 status = "disabled"; 581 status = "disabled";
761 }; 582 };
762 583
763 lpuart5: serial@29a0000 { 584 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 585 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 586 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 587 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO !! 588 clocks = <&clockgen 4 0>;
768 QO <<
769 clock-names = "ipg"; 589 clock-names = "ipg";
770 status = "disabled"; 590 status = "disabled";
771 }; 591 };
772 592
773 wdog0: watchdog@2ad0000 { !! 593 wdog0: wdog@2ad0000 {
774 compatible = "fsl,ls10 594 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 595 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 596 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO !! 597 clocks = <&clockgen 4 0>;
778 QO !! 598 clock-names = "wdog";
779 big-endian; 599 big-endian;
780 }; 600 };
781 601
782 edma0: dma-controller@2c00000 !! 602 edma0: edma@2c00000 {
783 #dma-cells = <2>; 603 #dma-cells = <2>;
784 compatible = "fsl,vf61 604 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 605 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 606 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 607 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 608 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 609 <0 103 0x4>;
790 interrupt-names = "edm 610 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 611 dma-channels = <32>;
792 big-endian; 612 big-endian;
793 clock-names = "dmamux0 613 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO !! 614 clocks = <&clockgen 4 0>,
795 QO !! 615 <&clockgen 4 0>;
796 <&clockgen QO <<
797 QO <<
798 }; 616 };
799 617
800 aux_bus: bus { !! 618 usb0: usb3@2f00000 {
801 #address-cells = <2>; !! 619 compatible = "snps,dwc3";
802 #size-cells = <2>; !! 620 reg = <0x0 0x2f00000 0x0 0x10000>;
803 compatible = "simple-b !! 621 interrupts = <0 60 0x4>;
804 ranges; !! 622 dr_mode = "host";
805 dma-ranges = <0x0 0x0 !! 623 snps,quirk-frame-length-adjustment = <0x20>;
806 !! 624 snps,dis_rxdet_inp3_quirk;
807 usb0: usb@2f00000 { !! 625 };
808 compatible = " !! 626
809 reg = <0x0 0x2 !! 627 usb1: usb3@3000000 {
810 interrupts = < !! 628 compatible = "snps,dwc3";
811 dr_mode = "hos !! 629 reg = <0x0 0x3000000 0x0 0x10000>;
812 snps,quirk-fra !! 630 interrupts = <0 61 0x4>;
813 snps,dis_rxdet !! 631 dr_mode = "host";
814 usb3-lpm-capab !! 632 snps,quirk-frame-length-adjustment = <0x20>;
815 snps,incr-burs !! 633 snps,dis_rxdet_inp3_quirk;
816 status = "disa !! 634 };
817 }; !! 635
818 !! 636 usb2: usb3@3100000 {
819 usb1: usb@3000000 { !! 637 compatible = "snps,dwc3";
820 compatible = " !! 638 reg = <0x0 0x3100000 0x0 0x10000>;
821 reg = <0x0 0x3 !! 639 interrupts = <0 63 0x4>;
822 interrupts = < !! 640 dr_mode = "host";
823 dr_mode = "hos !! 641 snps,quirk-frame-length-adjustment = <0x20>;
824 snps,quirk-fra !! 642 snps,dis_rxdet_inp3_quirk;
825 snps,dis_rxdet !! 643 };
826 usb3-lpm-capab !! 644
827 snps,incr-burs !! 645 sata: sata@3200000 {
828 status = "disa !! 646 compatible = "fsl,ls1043a-ahci";
829 }; !! 647 reg = <0x0 0x3200000 0x0 0x10000>,
830 !! 648 <0x0 0x20140520 0x0 0x4>;
831 usb2: usb@3100000 { !! 649 reg-names = "ahci", "sata-ecc";
832 compatible = " !! 650 interrupts = <0 69 0x4>;
833 reg = <0x0 0x3 !! 651 clocks = <&clockgen 4 0>;
834 interrupts = < !! 652 dma-coherent;
835 dr_mode = "hos <<
836 snps,quirk-fra <<
837 snps,dis_rxdet <<
838 usb3-lpm-capab <<
839 snps,incr-burs <<
840 status = "disa <<
841 }; <<
842 <<
843 sata: sata@3200000 { <<
844 compatible = " <<
845 reg = <0x0 0x3 <<
846 <0x0 0 <<
847 reg-names = "a <<
848 interrupts = < <<
849 clocks = <&clo <<
850 <<
851 dma-coherent; <<
852 }; <<
853 }; 653 };
854 654
855 msi1: msi-controller1@1571000 655 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 656 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 657 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 658 msi-controller;
859 interrupts = <GIC_SPI !! 659 interrupts = <0 116 0x4>;
860 }; 660 };
861 661
862 msi2: msi-controller2@1572000 662 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 663 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 664 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 665 msi-controller;
866 interrupts = <GIC_SPI !! 666 interrupts = <0 126 0x4>;
867 }; 667 };
868 668
869 msi3: msi-controller3@1573000 669 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 670 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 671 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 672 msi-controller;
873 interrupts = <GIC_SPI !! 673 interrupts = <0 160 0x4>;
874 }; 674 };
875 675
876 pcie1: pcie@3400000 { !! 676 pcie@3400000 {
877 compatible = "fsl,ls10 !! 677 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
878 reg = <0x00 0x03400000 !! 678 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
879 <0x40 0x00000000 !! 679 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 680 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 681 interrupts = <0 118 0x4>, /* controller interrupt */
882 <GIC_SPI !! 682 <0 117 0x4>; /* PME interrupt */
883 interrupt-names = "pme !! 683 interrupt-names = "intr", "pme";
884 #address-cells = <3>; 684 #address-cells = <3>;
885 #size-cells = <2>; 685 #size-cells = <2>;
886 device_type = "pci"; 686 device_type = "pci";
887 num-viewport = <6>; !! 687 dma-coherent;
>> 688 num-lanes = <4>;
888 bus-range = <0x0 0xff> 689 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 690 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 691 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 692 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 693 #interrupt-cells = <1>;
893 interrupt-map-mask = < 694 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 695 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 696 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 697 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 698 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg <<
899 big-endian; <<
900 status = "disabled"; <<
901 }; 699 };
902 700
903 pcie2: pcie@3500000 { !! 701 pcie@3500000 {
904 compatible = "fsl,ls10 !! 702 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
905 reg = <0x00 0x03500000 !! 703 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
906 <0x48 0x00000000 !! 704 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 705 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 706 interrupts = <0 128 0x4>,
909 <GIC_SPI !! 707 <0 127 0x4>;
910 interrupt-names = "pme !! 708 interrupt-names = "intr", "pme";
911 #address-cells = <3>; 709 #address-cells = <3>;
912 #size-cells = <2>; 710 #size-cells = <2>;
913 device_type = "pci"; 711 device_type = "pci";
914 num-viewport = <6>; !! 712 dma-coherent;
>> 713 num-lanes = <2>;
915 bus-range = <0x0 0xff> 714 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 715 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 716 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 717 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 718 #interrupt-cells = <1>;
920 interrupt-map-mask = < 719 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 720 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 721 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 722 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 723 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg <<
926 big-endian; <<
927 status = "disabled"; <<
928 }; 724 };
929 725
930 pcie3: pcie@3600000 { !! 726 pcie@3600000 {
931 compatible = "fsl,ls10 !! 727 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
932 reg = <0x00 0x03600000 !! 728 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
933 <0x50 0x00000000 !! 729 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 730 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 731 interrupts = <0 162 0x4>,
936 <GIC_SPI !! 732 <0 161 0x4>;
937 interrupt-names = "pme !! 733 interrupt-names = "intr", "pme";
938 #address-cells = <3>; 734 #address-cells = <3>;
939 #size-cells = <2>; 735 #size-cells = <2>;
940 device_type = "pci"; 736 device_type = "pci";
941 num-viewport = <6>; !! 737 dma-coherent;
>> 738 num-lanes = <2>;
942 bus-range = <0x0 0xff> 739 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 740 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 741 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 742 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 743 #interrupt-cells = <1>;
947 interrupt-map-mask = < 744 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 745 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 746 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 747 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 748 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg <<
953 big-endian; <<
954 status = "disabled"; <<
955 }; <<
956 <<
957 qdma: dma-controller@8380000 { <<
958 compatible = "fsl,ls10 <<
959 reg = <0x0 0x8380000 0 <<
960 <0x0 0x8390000 0 <<
961 <0x0 0x83a0000 0 <<
962 interrupts = <GIC_SPI <<
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 interrupt-names = "qdm <<
968 "qdma-queue1", <<
969 #dma-cells = <1>; <<
970 dma-channels = <8>; <<
971 block-number = <1>; <<
972 block-offset = <0x1000 <<
973 fsl,dma-queues = <2>; <<
974 status-sizes = <64>; <<
975 queue-sizes = <64 64>; <<
976 big-endian; <<
977 }; <<
978 <<
979 rcpm: wakeup-controller@1ee214 <<
980 compatible = "fsl,ls10 <<
981 reg = <0x0 0x1ee2140 0 <<
982 #fsl,rcpm-wakeup-cells <<
983 }; <<
984 <<
985 ftm_alarm0: rtc@29d0000 { <<
986 compatible = "fsl,ls10 <<
987 reg = <0x0 0x29d0000 0 <<
988 fsl,rcpm-wakeup = <&rc <<
989 interrupts = <GIC_SPI <<
990 big-endian; <<
991 }; 749 };
992 }; 750 };
993 751
994 firmware { 752 firmware {
995 optee { 753 optee {
996 compatible = "linaro,o 754 compatible = "linaro,optee-tz";
997 method = "smc"; 755 method = "smc";
998 }; 756 };
999 }; 757 };
1000 758
1001 }; 759 };
1002 760
1003 #include "qoriq-qman-portals.dtsi" 761 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 762 #include "qoriq-bman-portals.dtsi"
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