1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape !! 3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
4 * 4 *
5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP !! 6 * Copyright 2018 NXP
7 * 7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */ 9 */
10 10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
12 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> <<
15 13
16 / { 14 / {
17 compatible = "fsl,ls1043a"; 15 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 aliases { 20 aliases {
23 crypto = &crypto; <<
24 fman0 = &fman0; 21 fman0 = &fman0;
25 ethernet0 = &enet0; 22 ethernet0 = &enet0;
26 ethernet1 = &enet1; 23 ethernet1 = &enet1;
27 ethernet2 = &enet2; 24 ethernet2 = &enet2;
28 ethernet3 = &enet3; 25 ethernet3 = &enet3;
29 ethernet4 = &enet4; 26 ethernet4 = &enet4;
30 ethernet5 = &enet5; 27 ethernet5 = &enet5;
31 ethernet6 = &enet6; 28 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; <<
33 }; 29 };
34 30
35 cpus { 31 cpus {
36 #address-cells = <1>; 32 #address-cells = <1>;
37 #size-cells = <0>; 33 #size-cells = <0>;
38 34
39 /* 35 /*
40 * We expect the enable-method 36 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 37 * is dependent on the SoC FW, which will fill this in.
42 * 38 *
43 * Currently supported enable- 39 * Currently supported enable-method is psci v0.2
44 */ 40 */
45 cpu0: cpu@0 { 41 cpu0: cpu@0 {
46 device_type = "cpu"; 42 device_type = "cpu";
47 compatible = "arm,cort 43 compatible = "arm,cortex-a53";
48 reg = <0x0>; 44 reg = <0x0>;
49 clocks = <&clockgen QO !! 45 clocks = <&clockgen 1 0>;
50 next-level-cache = <&l 46 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP 47 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>; 48 #cooling-cells = <2>;
53 }; 49 };
54 50
55 cpu1: cpu@1 { 51 cpu1: cpu@1 {
56 device_type = "cpu"; 52 device_type = "cpu";
57 compatible = "arm,cort 53 compatible = "arm,cortex-a53";
58 reg = <0x1>; 54 reg = <0x1>;
59 clocks = <&clockgen QO !! 55 clocks = <&clockgen 1 0>;
60 next-level-cache = <&l 56 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP 57 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>; 58 #cooling-cells = <2>;
63 }; 59 };
64 60
65 cpu2: cpu@2 { 61 cpu2: cpu@2 {
66 device_type = "cpu"; 62 device_type = "cpu";
67 compatible = "arm,cort 63 compatible = "arm,cortex-a53";
68 reg = <0x2>; 64 reg = <0x2>;
69 clocks = <&clockgen QO !! 65 clocks = <&clockgen 1 0>;
70 next-level-cache = <&l 66 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP 67 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 68 #cooling-cells = <2>;
73 }; 69 };
74 70
75 cpu3: cpu@3 { 71 cpu3: cpu@3 {
76 device_type = "cpu"; 72 device_type = "cpu";
77 compatible = "arm,cort 73 compatible = "arm,cortex-a53";
78 reg = <0x3>; 74 reg = <0x3>;
79 clocks = <&clockgen QO !! 75 clocks = <&clockgen 1 0>;
80 next-level-cache = <&l 76 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP 77 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>; 78 #cooling-cells = <2>;
83 }; 79 };
84 80
85 l2: l2-cache { 81 l2: l2-cache {
86 compatible = "cache"; 82 compatible = "cache";
87 cache-level = <2>; <<
88 cache-unified; <<
89 }; 83 };
90 }; 84 };
91 85
92 idle-states { 86 idle-states {
93 /* 87 /*
94 * PSCI node is not added defa 88 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to u 89 * parts if it determines to use PSCI.
96 */ 90 */
97 entry-method = "psci"; 91 entry-method = "psci";
98 92
99 CPU_PH20: cpu-ph20 { 93 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle 94 compatible = "arm,idle-state";
101 idle-state-name = "PH2 95 idle-state-name = "PH20";
102 arm,psci-suspend-param 96 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <10 97 entry-latency-us = <1000>;
104 exit-latency-us = <100 98 exit-latency-us = <1000>;
105 min-residency-us = <30 99 min-residency-us = <3000>;
106 }; 100 };
107 }; 101 };
108 102
109 memory@80000000 { 103 memory@80000000 {
110 device_type = "memory"; 104 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 105 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 106 /* DRAM space 1, size: 2GiB DRAM */
113 }; 107 };
114 108
115 reserved-memory { 109 reserved-memory {
116 #address-cells = <2>; 110 #address-cells = <2>;
117 #size-cells = <2>; 111 #size-cells = <2>;
118 ranges; 112 ranges;
119 113
120 bman_fbpr: bman-fbpr { 114 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 115 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 116 size = <0 0x1000000>;
123 alignment = <0 0x10000 117 alignment = <0 0x1000000>;
124 no-map; 118 no-map;
125 }; 119 };
126 120
127 qman_fqd: qman-fqd { 121 qman_fqd: qman-fqd {
128 compatible = "shared-d 122 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 123 size = <0 0x400000>;
130 alignment = <0 0x40000 124 alignment = <0 0x400000>;
131 no-map; 125 no-map;
132 }; 126 };
133 127
134 qman_pfdr: qman-pfdr { 128 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 129 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 130 size = <0 0x2000000>;
137 alignment = <0 0x20000 131 alignment = <0 0x2000000>;
138 no-map; 132 no-map;
139 }; 133 };
140 }; 134 };
141 135
142 sysclk: sysclk { 136 sysclk: sysclk {
143 compatible = "fixed-clock"; 137 compatible = "fixed-clock";
144 #clock-cells = <0>; 138 #clock-cells = <0>;
145 clock-frequency = <100000000>; 139 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 140 clock-output-names = "sysclk";
147 }; 141 };
148 142
149 reboot { 143 reboot {
150 compatible = "syscon-reboot"; !! 144 compatible ="syscon-reboot";
151 regmap = <&dcfg>; 145 regmap = <&dcfg>;
152 offset = <0xb0>; 146 offset = <0xb0>;
153 mask = <0x02>; 147 mask = <0x02>;
154 }; 148 };
155 149
156 thermal-zones { 150 thermal-zones {
157 ddr-thermal { !! 151 cpu_thermal: cpu-thermal {
158 polling-delay-passive 152 polling-delay-passive = <1000>;
159 polling-delay = <5000> 153 polling-delay = <5000>;
160 thermal-sensors = <&tm <<
161 154
162 trips { <<
163 ddr-ctrler-ale <<
164 temper <<
165 hyster <<
166 type = <<
167 }; <<
168 <<
169 ddr-ctrler-cri <<
170 temper <<
171 hyster <<
172 type = <<
173 }; <<
174 }; <<
175 }; <<
176 <<
177 serdes-thermal { <<
178 polling-delay-passive <<
179 polling-delay = <5000> <<
180 thermal-sensors = <&tm <<
181 <<
182 trips { <<
183 serdes-alert { <<
184 temper <<
185 hyster <<
186 type = <<
187 }; <<
188 <<
189 serdes-crit { <<
190 temper <<
191 hyster <<
192 type = <<
193 }; <<
194 }; <<
195 }; <<
196 <<
197 fman-thermal { <<
198 polling-delay-passive <<
199 polling-delay = <5000> <<
200 thermal-sensors = <&tm <<
201 <<
202 trips { <<
203 fman-alert { <<
204 temper <<
205 hyster <<
206 type = <<
207 }; <<
208 <<
209 fman-crit { <<
210 temper <<
211 hyster <<
212 type = <<
213 }; <<
214 }; <<
215 }; <<
216 <<
217 cluster-thermal { <<
218 polling-delay-passive <<
219 polling-delay = <5000> <<
220 thermal-sensors = <&tm 155 thermal-sensors = <&tmu 3>;
221 156
222 trips { 157 trips {
223 core_cluster_a !! 158 cpu_alert: cpu-alert {
224 temper 159 temperature = <85000>;
225 hyster 160 hysteresis = <2000>;
226 type = 161 type = "passive";
227 }; 162 };
228 !! 163 cpu_crit: cpu-crit {
229 core_cluster_c <<
230 temper 164 temperature = <95000>;
231 hyster 165 hysteresis = <2000>;
232 type = 166 type = "critical";
233 }; 167 };
234 }; 168 };
235 169
236 cooling-maps { 170 cooling-maps {
237 map0 { 171 map0 {
238 trip = !! 172 trip = <&cpu_alert>;
239 coolin 173 cooling-device =
240 !! 174 <&cpu0 THERMAL_NO_LIMIT
241 !! 175 THERMAL_NO_LIMIT>;
242 <<
243 <<
244 }; <<
245 }; <<
246 }; <<
247 <<
248 sec-thermal { <<
249 polling-delay-passive <<
250 polling-delay = <5000> <<
251 thermal-sensors = <&tm <<
252 <<
253 trips { <<
254 sec-alert { <<
255 temper <<
256 hyster <<
257 type = <<
258 }; <<
259 <<
260 sec-crit { <<
261 temper <<
262 hyster <<
263 type = <<
264 }; 176 };
265 }; 177 };
266 }; 178 };
267 }; 179 };
268 180
269 timer { 181 timer {
270 compatible = "arm,armv8-timer" 182 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 183 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 184 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 185 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 186 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 187 fsl,erratum-a008585;
276 }; 188 };
277 189
278 pmu { 190 pmu {
279 compatible = "arm,cortex-a53-p !! 191 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 192 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 193 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 194 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 195 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 196 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 197 <&cpu1>,
286 <&cpu2>, 198 <&cpu2>,
287 <&cpu3>; 199 <&cpu3>;
288 }; 200 };
289 201
290 gic: interrupt-controller@1400000 { 202 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 203 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 204 #interrupt-cells = <3>;
293 interrupt-controller; 205 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 206 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 207 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 208 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 209 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 210 interrupts = <1 9 0xf08>;
299 }; 211 };
300 212
301 soc: soc { 213 soc: soc {
302 compatible = "simple-bus"; 214 compatible = "simple-bus";
303 #address-cells = <2>; 215 #address-cells = <2>;
304 #size-cells = <2>; 216 #size-cells = <2>;
305 ranges; 217 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 <<
307 dma-coherent; <<
308 218
309 clockgen: clocking@1ee1000 { 219 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 220 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 221 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 222 #clock-cells = <2>;
313 clocks = <&sysclk>; 223 clocks = <&sysclk>;
314 }; 224 };
315 225
316 scfg: scfg@1570000 { 226 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 227 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 228 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 229 big-endian;
320 #address-cells = <1>; <<
321 #size-cells = <1>; <<
322 ranges = <0x0 0x0 0x15 <<
323 <<
324 extirq: interrupt-cont <<
325 compatible = " <<
326 #interrupt-cel <<
327 #address-cells <<
328 interrupt-cont <<
329 reg = <0x1ac 4 <<
330 interrupt-map <<
331 <0 0 & <<
332 <1 0 & <<
333 <2 0 & <<
334 <3 0 & <<
335 <4 0 & <<
336 <5 0 & <<
337 <6 0 & <<
338 <7 0 & <<
339 <8 0 & <<
340 <9 0 & <<
341 <10 0 <<
342 <11 0 <<
343 interrupt-map- <<
344 }; <<
345 }; 230 };
346 231
347 crypto: crypto@1700000 { 232 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 233 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 234 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 235 fsl,sec-era = <3>;
351 #address-cells = <1>; 236 #address-cells = <1>;
352 #size-cells = <1>; 237 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 238 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 239 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 240 interrupts = <0 75 0x4>;
356 dma-coherent; <<
357 241
358 sec_jr0: jr@10000 { 242 sec_jr0: jr@10000 {
359 compatible = " 243 compatible = "fsl,sec-v5.4-job-ring",
360 " 244 "fsl,sec-v5.0-job-ring",
361 " 245 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 !! 246 reg = <0x10000 0x10000>;
363 interrupts = < !! 247 interrupts = <0 71 0x4>;
364 }; 248 };
365 249
366 sec_jr1: jr@20000 { 250 sec_jr1: jr@20000 {
367 compatible = " 251 compatible = "fsl,sec-v5.4-job-ring",
368 " 252 "fsl,sec-v5.0-job-ring",
369 " 253 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 !! 254 reg = <0x20000 0x10000>;
371 interrupts = < !! 255 interrupts = <0 72 0x4>;
372 }; 256 };
373 257
374 sec_jr2: jr@30000 { 258 sec_jr2: jr@30000 {
375 compatible = " 259 compatible = "fsl,sec-v5.4-job-ring",
376 " 260 "fsl,sec-v5.0-job-ring",
377 " 261 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 !! 262 reg = <0x30000 0x10000>;
379 interrupts = < !! 263 interrupts = <0 73 0x4>;
380 }; 264 };
381 265
382 sec_jr3: jr@40000 { 266 sec_jr3: jr@40000 {
383 compatible = " 267 compatible = "fsl,sec-v5.4-job-ring",
384 " 268 "fsl,sec-v5.0-job-ring",
385 " 269 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 !! 270 reg = <0x40000 0x10000>;
387 interrupts = < !! 271 interrupts = <0 74 0x4>;
388 }; 272 };
389 }; 273 };
390 274
391 sfp: efuse@1e80000 { <<
392 compatible = "fsl,ls10 <<
393 reg = <0x0 0x1e80000 0 <<
394 clocks = <&clockgen QO <<
395 QO <<
396 clock-names = "sfp"; <<
397 }; <<
398 <<
399 dcfg: dcfg@1ee0000 { 275 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 276 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 !! 277 reg = <0x0 0x1ee0000 0x0 0x10000>;
402 big-endian; 278 big-endian;
403 }; 279 };
404 280
405 ifc: memory-controller@1530000 !! 281 ifc: ifc@1530000 {
406 compatible = "fsl,ifc" !! 282 compatible = "fsl,ifc", "simple-bus";
407 reg = <0x0 0x1530000 0 283 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 284 interrupts = <0 43 0x4>;
409 }; 285 };
410 286
411 qspi: spi@1550000 { 287 qspi: spi@1550000 {
412 compatible = "fsl,ls10 288 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 289 #address-cells = <1>;
414 #size-cells = <0>; 290 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 291 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 292 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 293 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 294 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 295 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO !! 296 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
421 QO !! 297 big-endian;
422 <&clockgen QO <<
423 QO <<
424 status = "disabled"; 298 status = "disabled";
425 }; 299 };
426 300
427 esdhc: mmc@1560000 { !! 301 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 302 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 303 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 304 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 305 clock-frequency = <0>;
432 voltage-ranges = <1800 306 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 307 sdhci,auto-cmd12;
>> 308 big-endian;
434 bus-width = <4>; 309 bus-width = <4>;
435 }; 310 };
436 311
437 ddr: memory-controller@1080000 312 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 313 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 314 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 315 interrupts = <0 144 0x4>;
>> 316 big-endian;
441 }; 317 };
442 318
443 tmu: tmu@1f00000 { 319 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 320 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 321 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 322 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 !! 323 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
448 fsl,tmu-calibration = !! 324 fsl,tmu-calibration = <0x00000000 0x00000026
449 <0x000 !! 325 0x00000001 0x0000002d
450 <0x000 !! 326 0x00000002 0x00000032
451 <0x000 !! 327 0x00000003 0x00000039
452 <0x000 !! 328 0x00000004 0x0000003f
453 <0x000 !! 329 0x00000005 0x00000046
454 <0x000 !! 330 0x00000006 0x0000004d
455 <0x000 !! 331 0x00000007 0x00000054
456 <0x000 !! 332 0x00000008 0x0000005a
457 <0x000 !! 333 0x00000009 0x00000061
458 <0x000 !! 334 0x0000000a 0x0000006a
459 <0x000 !! 335 0x0000000b 0x00000071
460 <0x000 !! 336
461 !! 337 0x00010000 0x00000025
462 <0x000 !! 338 0x00010001 0x0000002c
463 <0x000 !! 339 0x00010002 0x00000035
464 <0x000 !! 340 0x00010003 0x0000003d
465 <0x000 !! 341 0x00010004 0x00000045
466 <0x000 !! 342 0x00010005 0x0000004e
467 <0x000 !! 343 0x00010006 0x00000057
468 <0x000 !! 344 0x00010007 0x00000061
469 <0x000 !! 345 0x00010008 0x0000006b
470 <0x000 !! 346 0x00010009 0x00000076
471 <0x000 !! 347
472 !! 348 0x00020000 0x00000029
473 <0x000 !! 349 0x00020001 0x00000033
474 <0x000 !! 350 0x00020002 0x0000003d
475 <0x000 !! 351 0x00020003 0x00000049
476 <0x000 !! 352 0x00020004 0x00000056
477 <0x000 !! 353 0x00020005 0x00000061
478 <0x000 !! 354 0x00020006 0x0000006d
479 <0x000 !! 355
480 !! 356 0x00030000 0x00000021
481 <0x000 !! 357 0x00030001 0x0000002a
482 <0x000 !! 358 0x00030002 0x0000003c
483 <0x000 !! 359 0x00030003 0x0000004e>;
484 <0x000 <<
485 <0x000 <<
486 <0x000 <<
487 <0x000 <<
488 <0x000 <<
489 #thermal-sensor-cells 360 #thermal-sensor-cells = <1>;
490 }; 361 };
491 362
492 qman: qman@1880000 { 363 qman: qman@1880000 {
493 compatible = "fsl,qman 364 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 365 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 366 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 367 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 368 };
498 369
499 bman: bman@1890000 { 370 bman: bman@1890000 {
500 compatible = "fsl,bman 371 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 372 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 373 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 374 memory-region = <&bman_fbpr>;
504 }; 375 };
505 376
506 bportals: bman-portals-bus@508 !! 377 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 378 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 379 };
509 380
510 qportals: qman-portals-bus@500 !! 381 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 382 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 383 };
513 384
514 dspi0: spi@2100000 { 385 dspi0: spi@2100000 {
515 compatible = "fsl,ls10 386 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 387 #address-cells = <1>;
517 #size-cells = <0>; 388 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 389 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 390 interrupts = <0 64 0x4>;
>> 391 clock-names = "dspi";
>> 392 clocks = <&clockgen 4 0>;
>> 393 spi-num-chipselects = <5>;
>> 394 big-endian;
>> 395 status = "disabled";
>> 396 };
>> 397
>> 398 dspi1: spi@2110000 {
>> 399 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 400 #address-cells = <1>;
>> 401 #size-cells = <0>;
>> 402 reg = <0x0 0x2110000 0x0 0x10000>;
>> 403 interrupts = <0 65 0x4>;
520 clock-names = "dspi"; 404 clock-names = "dspi";
521 clocks = <&clockgen QO !! 405 clocks = <&clockgen 4 0>;
522 QO <<
523 spi-num-chipselects = 406 spi-num-chipselects = <5>;
524 big-endian; 407 big-endian;
525 status = "disabled"; 408 status = "disabled";
526 }; 409 };
527 410
528 i2c0: i2c@2180000 { 411 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 !! 412 compatible = "fsl,vf610-i2c";
530 #address-cells = <1>; 413 #address-cells = <1>;
531 #size-cells = <0>; 414 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 415 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 416 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 417 clock-names = "i2c";
535 clocks = <&clockgen QO !! 418 clocks = <&clockgen 4 0>;
536 QO !! 419 dmas = <&edma0 1 39>,
537 dmas = <&edma0 1 38>, !! 420 <&edma0 1 38>;
538 <&edma0 1 39>; !! 421 dma-names = "tx", "rx";
539 dma-names = "rx", "tx" <<
540 status = "disabled"; 422 status = "disabled";
541 }; 423 };
542 424
543 i2c1: i2c@2190000 { 425 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 !! 426 compatible = "fsl,vf610-i2c";
545 #address-cells = <1>; 427 #address-cells = <1>;
546 #size-cells = <0>; 428 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 429 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 430 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 431 clock-names = "i2c";
550 clocks = <&clockgen QO !! 432 clocks = <&clockgen 4 0>;
551 QO <<
552 scl-gpios = <&gpio4 2 <<
553 status = "disabled"; 433 status = "disabled";
554 }; 434 };
555 435
556 i2c2: i2c@21a0000 { 436 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 !! 437 compatible = "fsl,vf610-i2c";
558 #address-cells = <1>; 438 #address-cells = <1>;
559 #size-cells = <0>; 439 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 440 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 441 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 442 clock-names = "i2c";
563 clocks = <&clockgen QO !! 443 clocks = <&clockgen 4 0>;
564 QO <<
565 scl-gpios = <&gpio4 10 <<
566 status = "disabled"; 444 status = "disabled";
567 }; 445 };
568 446
569 i2c3: i2c@21b0000 { 447 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 !! 448 compatible = "fsl,vf610-i2c";
571 #address-cells = <1>; 449 #address-cells = <1>;
572 #size-cells = <0>; 450 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 451 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 452 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 453 clock-names = "i2c";
576 clocks = <&clockgen QO !! 454 clocks = <&clockgen 4 0>;
577 QO <<
578 scl-gpios = <&gpio4 12 <<
579 status = "disabled"; 455 status = "disabled";
580 }; 456 };
581 457
582 duart0: serial@21c0500 { 458 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 459 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 460 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 461 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO !! 462 clocks = <&clockgen 4 0>;
587 QO <<
588 }; 463 };
589 464
590 duart1: serial@21c0600 { 465 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 466 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 467 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 468 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO !! 469 clocks = <&clockgen 4 0>;
595 QO <<
596 }; 470 };
597 471
598 duart2: serial@21d0500 { 472 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 473 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 474 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 475 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO !! 476 clocks = <&clockgen 4 0>;
603 QO <<
604 }; 477 };
605 478
606 duart3: serial@21d0600 { 479 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 480 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 481 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 482 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO !! 483 clocks = <&clockgen 4 0>;
611 QO <<
612 }; 484 };
613 485
614 gpio1: gpio@2300000 { 486 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 487 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 488 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 489 interrupts = <0 66 0x4>;
618 gpio-controller; 490 gpio-controller;
619 #gpio-cells = <2>; 491 #gpio-cells = <2>;
620 interrupt-controller; 492 interrupt-controller;
621 #interrupt-cells = <2> 493 #interrupt-cells = <2>;
622 }; 494 };
623 495
624 gpio2: gpio@2310000 { 496 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 497 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 498 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 499 interrupts = <0 67 0x4>;
628 gpio-controller; 500 gpio-controller;
629 #gpio-cells = <2>; 501 #gpio-cells = <2>;
630 interrupt-controller; 502 interrupt-controller;
631 #interrupt-cells = <2> 503 #interrupt-cells = <2>;
632 }; 504 };
633 505
634 gpio3: gpio@2320000 { 506 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 507 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 508 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 509 interrupts = <0 68 0x4>;
638 gpio-controller; 510 gpio-controller;
639 #gpio-cells = <2>; 511 #gpio-cells = <2>;
640 interrupt-controller; 512 interrupt-controller;
641 #interrupt-cells = <2> 513 #interrupt-cells = <2>;
642 }; 514 };
643 515
644 gpio4: gpio@2330000 { 516 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 517 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 518 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 519 interrupts = <0 134 0x4>;
648 gpio-controller; 520 gpio-controller;
649 #gpio-cells = <2>; 521 #gpio-cells = <2>;
650 interrupt-controller; 522 interrupt-controller;
651 #interrupt-cells = <2> 523 #interrupt-cells = <2>;
652 }; 524 };
653 525
654 uqe: uqe-bus@2400000 { <<
655 #address-cells = <1>; <<
656 #size-cells = <1>; <<
657 compatible = "fsl,qe", <<
658 ranges = <0x0 0x0 0x24 <<
659 reg = <0x0 0x2400000 0 <<
660 brg-frequency = <10000 <<
661 bus-frequency = <20000 <<
662 fsl,qe-num-riscs = <1> <<
663 fsl,qe-num-snums = <28 <<
664 <<
665 qeic: qeic@80 { <<
666 compatible = " <<
667 reg = <0x80 0x <<
668 interrupt-cont <<
669 #interrupt-cel <<
670 interrupts = < <<
671 < <<
672 }; <<
673 <<
674 si1: si@700 { <<
675 compatible = " <<
676 <<
677 reg = <0x700 0 <<
678 }; <<
679 <<
680 siram1: siram@1000 { <<
681 compatible = " <<
682 <<
683 reg = <0x1000 <<
684 }; <<
685 <<
686 ucc@2000 { <<
687 cell-index = < <<
688 reg = <0x2000 <<
689 interrupts = < <<
690 interrupt-pare <<
691 }; <<
692 <<
693 ucc@2200 { <<
694 cell-index = < <<
695 reg = <0x2200 <<
696 interrupts = < <<
697 interrupt-pare <<
698 }; <<
699 <<
700 muram@10000 { <<
701 #address-cells <<
702 #size-cells = <<
703 compatible = " <<
704 ranges = <0x0 <<
705 <<
706 data-only@0 { <<
707 compat <<
708 "fsl,c <<
709 reg = <<
710 }; <<
711 }; <<
712 }; <<
713 <<
714 lpuart0: serial@2950000 { 526 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 527 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 528 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 529 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO !! 530 clocks = <&clockgen 0 0>;
719 clock-names = "ipg"; 531 clock-names = "ipg";
720 status = "disabled"; 532 status = "disabled";
721 }; 533 };
722 534
723 lpuart1: serial@2960000 { 535 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 536 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 537 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 538 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO !! 539 clocks = <&clockgen 4 0>;
728 QO <<
729 clock-names = "ipg"; 540 clock-names = "ipg";
730 status = "disabled"; 541 status = "disabled";
731 }; 542 };
732 543
733 lpuart2: serial@2970000 { 544 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 545 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 546 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 547 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO !! 548 clocks = <&clockgen 4 0>;
738 QO <<
739 clock-names = "ipg"; 549 clock-names = "ipg";
740 status = "disabled"; 550 status = "disabled";
741 }; 551 };
742 552
743 lpuart3: serial@2980000 { 553 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 554 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 555 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 556 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO !! 557 clocks = <&clockgen 4 0>;
748 QO <<
749 clock-names = "ipg"; 558 clock-names = "ipg";
750 status = "disabled"; 559 status = "disabled";
751 }; 560 };
752 561
753 lpuart4: serial@2990000 { 562 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 563 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 564 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 565 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO !! 566 clocks = <&clockgen 4 0>;
758 QO <<
759 clock-names = "ipg"; 567 clock-names = "ipg";
760 status = "disabled"; 568 status = "disabled";
761 }; 569 };
762 570
763 lpuart5: serial@29a0000 { 571 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 572 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 573 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 574 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO !! 575 clocks = <&clockgen 4 0>;
768 QO <<
769 clock-names = "ipg"; 576 clock-names = "ipg";
770 status = "disabled"; 577 status = "disabled";
771 }; 578 };
772 579
773 wdog0: watchdog@2ad0000 { !! 580 wdog0: wdog@2ad0000 {
774 compatible = "fsl,ls10 581 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 582 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 583 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO !! 584 clocks = <&clockgen 4 0>;
778 QO !! 585 clock-names = "wdog";
779 big-endian; 586 big-endian;
780 }; 587 };
781 588
782 edma0: dma-controller@2c00000 !! 589 edma0: edma@2c00000 {
783 #dma-cells = <2>; 590 #dma-cells = <2>;
784 compatible = "fsl,vf61 591 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 592 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 593 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 594 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 595 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 596 <0 103 0x4>;
790 interrupt-names = "edm 597 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 598 dma-channels = <32>;
792 big-endian; 599 big-endian;
793 clock-names = "dmamux0 600 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO !! 601 clocks = <&clockgen 4 0>,
795 QO !! 602 <&clockgen 4 0>;
796 <&clockgen QO <<
797 QO <<
798 }; 603 };
799 604
800 aux_bus: bus { !! 605 usb0: usb3@2f00000 {
801 #address-cells = <2>; !! 606 compatible = "snps,dwc3";
802 #size-cells = <2>; !! 607 reg = <0x0 0x2f00000 0x0 0x10000>;
803 compatible = "simple-b !! 608 interrupts = <0 60 0x4>;
804 ranges; !! 609 dr_mode = "host";
805 dma-ranges = <0x0 0x0 !! 610 snps,quirk-frame-length-adjustment = <0x20>;
806 !! 611 snps,dis_rxdet_inp3_quirk;
807 usb0: usb@2f00000 { !! 612 };
808 compatible = " !! 613
809 reg = <0x0 0x2 !! 614 usb1: usb3@3000000 {
810 interrupts = < !! 615 compatible = "snps,dwc3";
811 dr_mode = "hos !! 616 reg = <0x0 0x3000000 0x0 0x10000>;
812 snps,quirk-fra !! 617 interrupts = <0 61 0x4>;
813 snps,dis_rxdet !! 618 dr_mode = "host";
814 usb3-lpm-capab !! 619 snps,quirk-frame-length-adjustment = <0x20>;
815 snps,incr-burs !! 620 snps,dis_rxdet_inp3_quirk;
816 status = "disa !! 621 };
817 }; !! 622
818 !! 623 usb2: usb3@3100000 {
819 usb1: usb@3000000 { !! 624 compatible = "snps,dwc3";
820 compatible = " !! 625 reg = <0x0 0x3100000 0x0 0x10000>;
821 reg = <0x0 0x3 !! 626 interrupts = <0 63 0x4>;
822 interrupts = < !! 627 dr_mode = "host";
823 dr_mode = "hos !! 628 snps,quirk-frame-length-adjustment = <0x20>;
824 snps,quirk-fra !! 629 snps,dis_rxdet_inp3_quirk;
825 snps,dis_rxdet !! 630 };
826 usb3-lpm-capab !! 631
827 snps,incr-burs !! 632 sata: sata@3200000 {
828 status = "disa !! 633 compatible = "fsl,ls1043a-ahci";
829 }; !! 634 reg = <0x0 0x3200000 0x0 0x10000>,
830 !! 635 <0x0 0x20140520 0x0 0x4>;
831 usb2: usb@3100000 { !! 636 reg-names = "ahci", "sata-ecc";
832 compatible = " !! 637 interrupts = <0 69 0x4>;
833 reg = <0x0 0x3 !! 638 clocks = <&clockgen 4 0>;
834 interrupts = < !! 639 dma-coherent;
835 dr_mode = "hos <<
836 snps,quirk-fra <<
837 snps,dis_rxdet <<
838 usb3-lpm-capab <<
839 snps,incr-burs <<
840 status = "disa <<
841 }; <<
842 <<
843 sata: sata@3200000 { <<
844 compatible = " <<
845 reg = <0x0 0x3 <<
846 <0x0 0 <<
847 reg-names = "a <<
848 interrupts = < <<
849 clocks = <&clo <<
850 <<
851 dma-coherent; <<
852 }; <<
853 }; 640 };
854 641
855 msi1: msi-controller1@1571000 642 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 643 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 644 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 645 msi-controller;
859 interrupts = <GIC_SPI !! 646 interrupts = <0 116 0x4>;
860 }; 647 };
861 648
862 msi2: msi-controller2@1572000 649 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 650 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 651 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 652 msi-controller;
866 interrupts = <GIC_SPI !! 653 interrupts = <0 126 0x4>;
867 }; 654 };
868 655
869 msi3: msi-controller3@1573000 656 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 657 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 658 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 659 msi-controller;
873 interrupts = <GIC_SPI !! 660 interrupts = <0 160 0x4>;
874 }; 661 };
875 662
876 pcie1: pcie@3400000 { !! 663 pcie@3400000 {
877 compatible = "fsl,ls10 !! 664 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
878 reg = <0x00 0x03400000 !! 665 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
879 <0x40 0x00000000 !! 666 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 667 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 668 interrupts = <0 118 0x4>, /* controller interrupt */
882 <GIC_SPI !! 669 <0 117 0x4>; /* PME interrupt */
883 interrupt-names = "pme !! 670 interrupt-names = "intr", "pme";
884 #address-cells = <3>; 671 #address-cells = <3>;
885 #size-cells = <2>; 672 #size-cells = <2>;
886 device_type = "pci"; 673 device_type = "pci";
887 num-viewport = <6>; !! 674 dma-coherent;
>> 675 num-lanes = <4>;
888 bus-range = <0x0 0xff> 676 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 677 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 678 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 679 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 680 #interrupt-cells = <1>;
893 interrupt-map-mask = < 681 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 682 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 683 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 684 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 685 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg <<
899 big-endian; <<
900 status = "disabled"; <<
901 }; 686 };
902 687
903 pcie2: pcie@3500000 { !! 688 pcie@3500000 {
904 compatible = "fsl,ls10 !! 689 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
905 reg = <0x00 0x03500000 !! 690 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
906 <0x48 0x00000000 !! 691 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 692 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 693 interrupts = <0 128 0x4>,
909 <GIC_SPI !! 694 <0 127 0x4>;
910 interrupt-names = "pme !! 695 interrupt-names = "intr", "pme";
911 #address-cells = <3>; 696 #address-cells = <3>;
912 #size-cells = <2>; 697 #size-cells = <2>;
913 device_type = "pci"; 698 device_type = "pci";
914 num-viewport = <6>; !! 699 dma-coherent;
>> 700 num-lanes = <2>;
915 bus-range = <0x0 0xff> 701 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 702 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 703 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 704 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 705 #interrupt-cells = <1>;
920 interrupt-map-mask = < 706 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 707 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 708 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 709 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 710 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg <<
926 big-endian; <<
927 status = "disabled"; <<
928 }; 711 };
929 712
930 pcie3: pcie@3600000 { !! 713 pcie@3600000 {
931 compatible = "fsl,ls10 !! 714 compatible = "fsl,ls1043a-pcie", "snps,dw-pcie";
932 reg = <0x00 0x03600000 !! 715 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
933 <0x50 0x00000000 !! 716 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 717 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 718 interrupts = <0 162 0x4>,
936 <GIC_SPI !! 719 <0 161 0x4>;
937 interrupt-names = "pme !! 720 interrupt-names = "intr", "pme";
938 #address-cells = <3>; 721 #address-cells = <3>;
939 #size-cells = <2>; 722 #size-cells = <2>;
940 device_type = "pci"; 723 device_type = "pci";
941 num-viewport = <6>; !! 724 dma-coherent;
>> 725 num-lanes = <2>;
942 bus-range = <0x0 0xff> 726 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 727 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 728 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 729 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 730 #interrupt-cells = <1>;
947 interrupt-map-mask = < 731 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 732 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 733 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 734 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 735 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg <<
953 big-endian; <<
954 status = "disabled"; <<
955 }; <<
956 <<
957 qdma: dma-controller@8380000 { <<
958 compatible = "fsl,ls10 <<
959 reg = <0x0 0x8380000 0 <<
960 <0x0 0x8390000 0 <<
961 <0x0 0x83a0000 0 <<
962 interrupts = <GIC_SPI <<
963 <GIC_SPI <<
964 <GIC_SPI <<
965 <GIC_SPI <<
966 <GIC_SPI <<
967 interrupt-names = "qdm <<
968 "qdma-queue1", <<
969 #dma-cells = <1>; <<
970 dma-channels = <8>; <<
971 block-number = <1>; <<
972 block-offset = <0x1000 <<
973 fsl,dma-queues = <2>; <<
974 status-sizes = <64>; <<
975 queue-sizes = <64 64>; <<
976 big-endian; <<
977 }; <<
978 <<
979 rcpm: wakeup-controller@1ee214 <<
980 compatible = "fsl,ls10 <<
981 reg = <0x0 0x1ee2140 0 <<
982 #fsl,rcpm-wakeup-cells <<
983 }; <<
984 <<
985 ftm_alarm0: rtc@29d0000 { <<
986 compatible = "fsl,ls10 <<
987 reg = <0x0 0x29d0000 0 <<
988 fsl,rcpm-wakeup = <&rc <<
989 interrupts = <GIC_SPI <<
990 big-endian; <<
991 }; 736 };
992 }; 737 };
993 738
994 firmware { 739 firmware {
995 optee { 740 optee {
996 compatible = "linaro,o 741 compatible = "linaro,optee-tz";
997 method = "smc"; 742 method = "smc";
998 }; 743 };
999 }; 744 };
1000 745
1001 }; 746 };
1002 747
1003 #include "qoriq-qman-portals.dtsi" 748 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 749 #include "qoriq-bman-portals.dtsi"
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