1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 * 4 *
5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP 6 * Copyright 2018, 2020 NXP
7 * 7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */ 9 */
10 10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
12 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> <<
15 13
16 / { 14 / {
17 compatible = "fsl,ls1043a"; 15 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 aliases { 20 aliases {
23 crypto = &crypto; 21 crypto = &crypto;
24 fman0 = &fman0; 22 fman0 = &fman0;
25 ethernet0 = &enet0; 23 ethernet0 = &enet0;
26 ethernet1 = &enet1; 24 ethernet1 = &enet1;
27 ethernet2 = &enet2; 25 ethernet2 = &enet2;
28 ethernet3 = &enet3; 26 ethernet3 = &enet3;
29 ethernet4 = &enet4; 27 ethernet4 = &enet4;
30 ethernet5 = &enet5; 28 ethernet5 = &enet5;
31 ethernet6 = &enet6; 29 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; 30 rtc1 = &ftm_alarm0;
33 }; 31 };
34 32
35 cpus { 33 cpus {
36 #address-cells = <1>; 34 #address-cells = <1>;
37 #size-cells = <0>; 35 #size-cells = <0>;
38 36
39 /* 37 /*
40 * We expect the enable-method 38 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 39 * is dependent on the SoC FW, which will fill this in.
42 * 40 *
43 * Currently supported enable- 41 * Currently supported enable-method is psci v0.2
44 */ 42 */
45 cpu0: cpu@0 { 43 cpu0: cpu@0 {
46 device_type = "cpu"; 44 device_type = "cpu";
47 compatible = "arm,cort 45 compatible = "arm,cortex-a53";
48 reg = <0x0>; 46 reg = <0x0>;
49 clocks = <&clockgen QO !! 47 clocks = <&clockgen 1 0>;
50 next-level-cache = <&l 48 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP 49 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>; 50 #cooling-cells = <2>;
53 }; 51 };
54 52
55 cpu1: cpu@1 { 53 cpu1: cpu@1 {
56 device_type = "cpu"; 54 device_type = "cpu";
57 compatible = "arm,cort 55 compatible = "arm,cortex-a53";
58 reg = <0x1>; 56 reg = <0x1>;
59 clocks = <&clockgen QO !! 57 clocks = <&clockgen 1 0>;
60 next-level-cache = <&l 58 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP 59 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>; 60 #cooling-cells = <2>;
63 }; 61 };
64 62
65 cpu2: cpu@2 { 63 cpu2: cpu@2 {
66 device_type = "cpu"; 64 device_type = "cpu";
67 compatible = "arm,cort 65 compatible = "arm,cortex-a53";
68 reg = <0x2>; 66 reg = <0x2>;
69 clocks = <&clockgen QO !! 67 clocks = <&clockgen 1 0>;
70 next-level-cache = <&l 68 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP 69 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 70 #cooling-cells = <2>;
73 }; 71 };
74 72
75 cpu3: cpu@3 { 73 cpu3: cpu@3 {
76 device_type = "cpu"; 74 device_type = "cpu";
77 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
78 reg = <0x3>; 76 reg = <0x3>;
79 clocks = <&clockgen QO !! 77 clocks = <&clockgen 1 0>;
80 next-level-cache = <&l 78 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP 79 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>; 80 #cooling-cells = <2>;
83 }; 81 };
84 82
85 l2: l2-cache { 83 l2: l2-cache {
86 compatible = "cache"; 84 compatible = "cache";
87 cache-level = <2>; <<
88 cache-unified; <<
89 }; 85 };
90 }; 86 };
91 87
92 idle-states { 88 idle-states {
93 /* 89 /*
94 * PSCI node is not added defa 90 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to u 91 * parts if it determines to use PSCI.
96 */ 92 */
97 entry-method = "psci"; 93 entry-method = "psci";
98 94
99 CPU_PH20: cpu-ph20 { 95 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle 96 compatible = "arm,idle-state";
101 idle-state-name = "PH2 97 idle-state-name = "PH20";
102 arm,psci-suspend-param 98 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <10 99 entry-latency-us = <1000>;
104 exit-latency-us = <100 100 exit-latency-us = <1000>;
105 min-residency-us = <30 101 min-residency-us = <3000>;
106 }; 102 };
107 }; 103 };
108 104
109 memory@80000000 { 105 memory@80000000 {
110 device_type = "memory"; 106 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 107 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 108 /* DRAM space 1, size: 2GiB DRAM */
113 }; 109 };
114 110
115 reserved-memory { 111 reserved-memory {
116 #address-cells = <2>; 112 #address-cells = <2>;
117 #size-cells = <2>; 113 #size-cells = <2>;
118 ranges; 114 ranges;
119 115
120 bman_fbpr: bman-fbpr { 116 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 117 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 118 size = <0 0x1000000>;
123 alignment = <0 0x10000 119 alignment = <0 0x1000000>;
124 no-map; 120 no-map;
125 }; 121 };
126 122
127 qman_fqd: qman-fqd { 123 qman_fqd: qman-fqd {
128 compatible = "shared-d 124 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 125 size = <0 0x400000>;
130 alignment = <0 0x40000 126 alignment = <0 0x400000>;
131 no-map; 127 no-map;
132 }; 128 };
133 129
134 qman_pfdr: qman-pfdr { 130 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 131 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 132 size = <0 0x2000000>;
137 alignment = <0 0x20000 133 alignment = <0 0x2000000>;
138 no-map; 134 no-map;
139 }; 135 };
140 }; 136 };
141 137
142 sysclk: sysclk { 138 sysclk: sysclk {
143 compatible = "fixed-clock"; 139 compatible = "fixed-clock";
144 #clock-cells = <0>; 140 #clock-cells = <0>;
145 clock-frequency = <100000000>; 141 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 142 clock-output-names = "sysclk";
147 }; 143 };
148 144
149 reboot { 145 reboot {
150 compatible = "syscon-reboot"; !! 146 compatible ="syscon-reboot";
151 regmap = <&dcfg>; 147 regmap = <&dcfg>;
152 offset = <0xb0>; 148 offset = <0xb0>;
153 mask = <0x02>; 149 mask = <0x02>;
154 }; 150 };
155 151
156 thermal-zones { 152 thermal-zones {
157 ddr-thermal { !! 153 ddr-controller {
158 polling-delay-passive 154 polling-delay-passive = <1000>;
159 polling-delay = <5000> 155 polling-delay = <5000>;
160 thermal-sensors = <&tm 156 thermal-sensors = <&tmu 0>;
161 157
162 trips { 158 trips {
163 ddr-ctrler-ale 159 ddr-ctrler-alert {
164 temper 160 temperature = <85000>;
165 hyster 161 hysteresis = <2000>;
166 type = 162 type = "passive";
167 }; 163 };
168 164
169 ddr-ctrler-cri 165 ddr-ctrler-crit {
170 temper 166 temperature = <95000>;
171 hyster 167 hysteresis = <2000>;
172 type = 168 type = "critical";
173 }; 169 };
174 }; 170 };
175 }; 171 };
176 172
177 serdes-thermal { !! 173 serdes {
178 polling-delay-passive 174 polling-delay-passive = <1000>;
179 polling-delay = <5000> 175 polling-delay = <5000>;
180 thermal-sensors = <&tm 176 thermal-sensors = <&tmu 1>;
181 177
182 trips { 178 trips {
183 serdes-alert { 179 serdes-alert {
184 temper 180 temperature = <85000>;
185 hyster 181 hysteresis = <2000>;
186 type = 182 type = "passive";
187 }; 183 };
188 184
189 serdes-crit { 185 serdes-crit {
190 temper 186 temperature = <95000>;
191 hyster 187 hysteresis = <2000>;
192 type = 188 type = "critical";
193 }; 189 };
194 }; 190 };
195 }; 191 };
196 192
197 fman-thermal { !! 193 fman {
198 polling-delay-passive 194 polling-delay-passive = <1000>;
199 polling-delay = <5000> 195 polling-delay = <5000>;
200 thermal-sensors = <&tm 196 thermal-sensors = <&tmu 2>;
201 197
202 trips { 198 trips {
203 fman-alert { 199 fman-alert {
204 temper 200 temperature = <85000>;
205 hyster 201 hysteresis = <2000>;
206 type = 202 type = "passive";
207 }; 203 };
208 204
209 fman-crit { 205 fman-crit {
210 temper 206 temperature = <95000>;
211 hyster 207 hysteresis = <2000>;
212 type = 208 type = "critical";
213 }; 209 };
214 }; 210 };
215 }; 211 };
216 212
217 cluster-thermal { !! 213 core-cluster {
218 polling-delay-passive 214 polling-delay-passive = <1000>;
219 polling-delay = <5000> 215 polling-delay = <5000>;
220 thermal-sensors = <&tm 216 thermal-sensors = <&tmu 3>;
221 217
222 trips { 218 trips {
223 core_cluster_a 219 core_cluster_alert: core-cluster-alert {
224 temper 220 temperature = <85000>;
225 hyster 221 hysteresis = <2000>;
226 type = 222 type = "passive";
227 }; 223 };
228 224
229 core_cluster_c 225 core_cluster_crit: core-cluster-crit {
230 temper 226 temperature = <95000>;
231 hyster 227 hysteresis = <2000>;
232 type = 228 type = "critical";
233 }; 229 };
234 }; 230 };
235 231
236 cooling-maps { 232 cooling-maps {
237 map0 { 233 map0 {
238 trip = 234 trip = <&core_cluster_alert>;
239 coolin 235 cooling-device =
240 236 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
241 237 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
242 238 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
243 239 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 }; 240 };
245 }; 241 };
246 }; 242 };
247 243
248 sec-thermal { !! 244 sec {
249 polling-delay-passive 245 polling-delay-passive = <1000>;
250 polling-delay = <5000> 246 polling-delay = <5000>;
251 thermal-sensors = <&tm 247 thermal-sensors = <&tmu 4>;
252 248
253 trips { 249 trips {
254 sec-alert { 250 sec-alert {
255 temper 251 temperature = <85000>;
256 hyster 252 hysteresis = <2000>;
257 type = 253 type = "passive";
258 }; 254 };
259 255
260 sec-crit { 256 sec-crit {
261 temper 257 temperature = <95000>;
262 hyster 258 hysteresis = <2000>;
263 type = 259 type = "critical";
264 }; 260 };
265 }; 261 };
266 }; 262 };
267 }; 263 };
268 264
269 timer { 265 timer {
270 compatible = "arm,armv8-timer" 266 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 267 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 268 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 269 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 270 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 271 fsl,erratum-a008585;
276 }; 272 };
277 273
278 pmu { 274 pmu {
279 compatible = "arm,cortex-a53-p !! 275 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 276 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 277 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 278 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 279 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 280 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 281 <&cpu1>,
286 <&cpu2>, 282 <&cpu2>,
287 <&cpu3>; 283 <&cpu3>;
288 }; 284 };
289 285
290 gic: interrupt-controller@1400000 { 286 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 287 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 288 #interrupt-cells = <3>;
293 interrupt-controller; 289 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 290 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 291 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 292 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 293 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 294 interrupts = <1 9 0xf08>;
299 }; 295 };
300 296
301 soc: soc { 297 soc: soc {
302 compatible = "simple-bus"; 298 compatible = "simple-bus";
303 #address-cells = <2>; 299 #address-cells = <2>;
304 #size-cells = <2>; 300 #size-cells = <2>;
305 ranges; 301 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 <<
307 dma-coherent; <<
308 302
309 clockgen: clocking@1ee1000 { 303 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 304 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 305 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 306 #clock-cells = <2>;
313 clocks = <&sysclk>; 307 clocks = <&sysclk>;
314 }; 308 };
315 309
316 scfg: scfg@1570000 { 310 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 311 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 312 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 313 big-endian;
320 #address-cells = <1>; <<
321 #size-cells = <1>; <<
322 ranges = <0x0 0x0 0x15 <<
323 <<
324 extirq: interrupt-cont <<
325 compatible = " <<
326 #interrupt-cel <<
327 #address-cells <<
328 interrupt-cont <<
329 reg = <0x1ac 4 <<
330 interrupt-map <<
331 <0 0 & <<
332 <1 0 & <<
333 <2 0 & <<
334 <3 0 & <<
335 <4 0 & <<
336 <5 0 & <<
337 <6 0 & <<
338 <7 0 & <<
339 <8 0 & <<
340 <9 0 & <<
341 <10 0 <<
342 <11 0 <<
343 interrupt-map- <<
344 }; <<
345 }; 314 };
346 315
347 crypto: crypto@1700000 { 316 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 317 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 318 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 319 fsl,sec-era = <3>;
351 #address-cells = <1>; 320 #address-cells = <1>;
352 #size-cells = <1>; 321 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 322 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 323 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 324 interrupts = <0 75 0x4>;
356 dma-coherent; 325 dma-coherent;
357 326
358 sec_jr0: jr@10000 { 327 sec_jr0: jr@10000 {
359 compatible = " 328 compatible = "fsl,sec-v5.4-job-ring",
360 " 329 "fsl,sec-v5.0-job-ring",
361 " 330 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 !! 331 reg = <0x10000 0x10000>;
363 interrupts = < !! 332 interrupts = <0 71 0x4>;
364 }; 333 };
365 334
366 sec_jr1: jr@20000 { 335 sec_jr1: jr@20000 {
367 compatible = " 336 compatible = "fsl,sec-v5.4-job-ring",
368 " 337 "fsl,sec-v5.0-job-ring",
369 " 338 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 !! 339 reg = <0x20000 0x10000>;
371 interrupts = < !! 340 interrupts = <0 72 0x4>;
372 }; 341 };
373 342
374 sec_jr2: jr@30000 { 343 sec_jr2: jr@30000 {
375 compatible = " 344 compatible = "fsl,sec-v5.4-job-ring",
376 " 345 "fsl,sec-v5.0-job-ring",
377 " 346 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 !! 347 reg = <0x30000 0x10000>;
379 interrupts = < !! 348 interrupts = <0 73 0x4>;
380 }; 349 };
381 350
382 sec_jr3: jr@40000 { 351 sec_jr3: jr@40000 {
383 compatible = " 352 compatible = "fsl,sec-v5.4-job-ring",
384 " 353 "fsl,sec-v5.0-job-ring",
385 " 354 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 !! 355 reg = <0x40000 0x10000>;
387 interrupts = < !! 356 interrupts = <0 74 0x4>;
388 }; 357 };
389 }; 358 };
390 359
391 sfp: efuse@1e80000 { <<
392 compatible = "fsl,ls10 <<
393 reg = <0x0 0x1e80000 0 <<
394 clocks = <&clockgen QO <<
395 QO <<
396 clock-names = "sfp"; <<
397 }; <<
398 <<
399 dcfg: dcfg@1ee0000 { 360 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 361 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 !! 362 reg = <0x0 0x1ee0000 0x0 0x10000>;
402 big-endian; 363 big-endian;
403 }; 364 };
404 365
405 ifc: memory-controller@1530000 !! 366 ifc: ifc@1530000 {
406 compatible = "fsl,ifc" !! 367 compatible = "fsl,ifc", "simple-bus";
407 reg = <0x0 0x1530000 0 368 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 369 interrupts = <0 43 0x4>;
409 }; 370 };
410 371
411 qspi: spi@1550000 { 372 qspi: spi@1550000 {
412 compatible = "fsl,ls10 373 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 374 #address-cells = <1>;
414 #size-cells = <0>; 375 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 376 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 377 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 378 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 379 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 380 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO !! 381 clocks = <&clockgen 4 0>, <&clockgen 4 0>;
421 QO <<
422 <&clockgen QO <<
423 QO <<
424 status = "disabled"; 382 status = "disabled";
425 }; 383 };
426 384
427 esdhc: mmc@1560000 { !! 385 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 386 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 387 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 388 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 389 clock-frequency = <0>;
432 voltage-ranges = <1800 390 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 391 sdhci,auto-cmd12;
>> 392 big-endian;
434 bus-width = <4>; 393 bus-width = <4>;
435 }; 394 };
436 395
437 ddr: memory-controller@1080000 396 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 397 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 398 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 399 interrupts = <0 144 0x4>;
>> 400 big-endian;
441 }; 401 };
442 402
443 tmu: tmu@1f00000 { 403 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 404 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 405 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 406 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 407 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration = !! 408 fsl,tmu-calibration = <0x00000000 0x00000023
449 <0x000 !! 409 0x00000001 0x0000002a
450 <0x000 !! 410 0x00000002 0x00000031
451 <0x000 !! 411 0x00000003 0x00000037
452 <0x000 !! 412 0x00000004 0x0000003e
453 <0x000 !! 413 0x00000005 0x00000044
454 <0x000 !! 414 0x00000006 0x0000004b
455 <0x000 !! 415 0x00000007 0x00000051
456 <0x000 !! 416 0x00000008 0x00000058
457 <0x000 !! 417 0x00000009 0x0000005e
458 <0x000 !! 418 0x0000000a 0x00000065
459 <0x000 !! 419 0x0000000b 0x0000006b
460 <0x000 !! 420
461 !! 421 0x00010000 0x00000023
462 <0x000 !! 422 0x00010001 0x0000002b
463 <0x000 !! 423 0x00010002 0x00000033
464 <0x000 !! 424 0x00010003 0x0000003b
465 <0x000 !! 425 0x00010004 0x00000043
466 <0x000 !! 426 0x00010005 0x0000004b
467 <0x000 !! 427 0x00010006 0x00000054
468 <0x000 !! 428 0x00010007 0x0000005c
469 <0x000 !! 429 0x00010008 0x00000064
470 <0x000 !! 430 0x00010009 0x0000006c
471 <0x000 !! 431
472 !! 432 0x00020000 0x00000021
473 <0x000 !! 433 0x00020001 0x0000002c
474 <0x000 !! 434 0x00020002 0x00000036
475 <0x000 !! 435 0x00020003 0x00000040
476 <0x000 !! 436 0x00020004 0x0000004b
477 <0x000 !! 437 0x00020005 0x00000055
478 <0x000 !! 438 0x00020006 0x0000005f
479 <0x000 !! 439
480 !! 440 0x00030000 0x00000013
481 <0x000 !! 441 0x00030001 0x0000001d
482 <0x000 !! 442 0x00030002 0x00000028
483 <0x000 !! 443 0x00030003 0x00000032
484 <0x000 !! 444 0x00030004 0x0000003d
485 <0x000 !! 445 0x00030005 0x00000047
486 <0x000 !! 446 0x00030006 0x00000052
487 <0x000 !! 447 0x00030007 0x0000005c>;
488 <0x000 <<
489 #thermal-sensor-cells 448 #thermal-sensor-cells = <1>;
490 }; 449 };
491 450
492 qman: qman@1880000 { 451 qman: qman@1880000 {
493 compatible = "fsl,qman 452 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 453 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 454 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 455 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 456 };
498 457
499 bman: bman@1890000 { 458 bman: bman@1890000 {
500 compatible = "fsl,bman 459 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 460 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 461 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 462 memory-region = <&bman_fbpr>;
504 }; 463 };
505 464
506 bportals: bman-portals-bus@508 !! 465 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 466 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 467 };
509 468
510 qportals: qman-portals-bus@500 !! 469 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 470 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 471 };
513 472
514 dspi0: spi@2100000 { 473 dspi0: spi@2100000 {
515 compatible = "fsl,ls10 474 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 475 #address-cells = <1>;
517 #size-cells = <0>; 476 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 477 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 478 interrupts = <0 64 0x4>;
520 clock-names = "dspi"; 479 clock-names = "dspi";
521 clocks = <&clockgen QO !! 480 clocks = <&clockgen 4 0>;
522 QO !! 481 spi-num-chipselects = <5>;
>> 482 big-endian;
>> 483 status = "disabled";
>> 484 };
>> 485
>> 486 dspi1: spi@2110000 {
>> 487 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 488 #address-cells = <1>;
>> 489 #size-cells = <0>;
>> 490 reg = <0x0 0x2110000 0x0 0x10000>;
>> 491 interrupts = <0 65 0x4>;
>> 492 clock-names = "dspi";
>> 493 clocks = <&clockgen 4 0>;
523 spi-num-chipselects = 494 spi-num-chipselects = <5>;
524 big-endian; 495 big-endian;
525 status = "disabled"; 496 status = "disabled";
526 }; 497 };
527 498
528 i2c0: i2c@2180000 { 499 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 !! 500 compatible = "fsl,vf610-i2c";
530 #address-cells = <1>; 501 #address-cells = <1>;
531 #size-cells = <0>; 502 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 503 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 504 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 505 clock-names = "i2c";
535 clocks = <&clockgen QO !! 506 clocks = <&clockgen 4 0>;
536 QO !! 507 dmas = <&edma0 1 39>,
537 dmas = <&edma0 1 38>, !! 508 <&edma0 1 38>;
538 <&edma0 1 39>; !! 509 dma-names = "tx", "rx";
539 dma-names = "rx", "tx" <<
540 status = "disabled"; 510 status = "disabled";
541 }; 511 };
542 512
543 i2c1: i2c@2190000 { 513 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 !! 514 compatible = "fsl,vf610-i2c";
545 #address-cells = <1>; 515 #address-cells = <1>;
546 #size-cells = <0>; 516 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 517 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 518 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 519 clock-names = "i2c";
550 clocks = <&clockgen QO !! 520 clocks = <&clockgen 4 0>;
551 QO <<
552 scl-gpios = <&gpio4 2 <<
553 status = "disabled"; 521 status = "disabled";
554 }; 522 };
555 523
556 i2c2: i2c@21a0000 { 524 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 !! 525 compatible = "fsl,vf610-i2c";
558 #address-cells = <1>; 526 #address-cells = <1>;
559 #size-cells = <0>; 527 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 528 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 529 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 530 clock-names = "i2c";
563 clocks = <&clockgen QO !! 531 clocks = <&clockgen 4 0>;
564 QO <<
565 scl-gpios = <&gpio4 10 <<
566 status = "disabled"; 532 status = "disabled";
567 }; 533 };
568 534
569 i2c3: i2c@21b0000 { 535 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 !! 536 compatible = "fsl,vf610-i2c";
571 #address-cells = <1>; 537 #address-cells = <1>;
572 #size-cells = <0>; 538 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 539 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 540 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 541 clock-names = "i2c";
576 clocks = <&clockgen QO !! 542 clocks = <&clockgen 4 0>;
577 QO <<
578 scl-gpios = <&gpio4 12 <<
579 status = "disabled"; 543 status = "disabled";
580 }; 544 };
581 545
582 duart0: serial@21c0500 { 546 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 547 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 548 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 549 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO !! 550 clocks = <&clockgen 4 0>;
587 QO <<
588 }; 551 };
589 552
590 duart1: serial@21c0600 { 553 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 554 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 555 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 556 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO !! 557 clocks = <&clockgen 4 0>;
595 QO <<
596 }; 558 };
597 559
598 duart2: serial@21d0500 { 560 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 561 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 562 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 563 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO !! 564 clocks = <&clockgen 4 0>;
603 QO <<
604 }; 565 };
605 566
606 duart3: serial@21d0600 { 567 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 568 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 569 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 570 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO !! 571 clocks = <&clockgen 4 0>;
611 QO <<
612 }; 572 };
613 573
614 gpio1: gpio@2300000 { 574 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 575 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 576 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 577 interrupts = <0 66 0x4>;
618 gpio-controller; 578 gpio-controller;
619 #gpio-cells = <2>; 579 #gpio-cells = <2>;
620 interrupt-controller; 580 interrupt-controller;
621 #interrupt-cells = <2> 581 #interrupt-cells = <2>;
622 }; 582 };
623 583
624 gpio2: gpio@2310000 { 584 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 585 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 586 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 587 interrupts = <0 67 0x4>;
628 gpio-controller; 588 gpio-controller;
629 #gpio-cells = <2>; 589 #gpio-cells = <2>;
630 interrupt-controller; 590 interrupt-controller;
631 #interrupt-cells = <2> 591 #interrupt-cells = <2>;
632 }; 592 };
633 593
634 gpio3: gpio@2320000 { 594 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 595 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 596 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 597 interrupts = <0 68 0x4>;
638 gpio-controller; 598 gpio-controller;
639 #gpio-cells = <2>; 599 #gpio-cells = <2>;
640 interrupt-controller; 600 interrupt-controller;
641 #interrupt-cells = <2> 601 #interrupt-cells = <2>;
642 }; 602 };
643 603
644 gpio4: gpio@2330000 { 604 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 605 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 606 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 607 interrupts = <0 134 0x4>;
648 gpio-controller; 608 gpio-controller;
649 #gpio-cells = <2>; 609 #gpio-cells = <2>;
650 interrupt-controller; 610 interrupt-controller;
651 #interrupt-cells = <2> 611 #interrupt-cells = <2>;
652 }; 612 };
653 613
654 uqe: uqe-bus@2400000 { !! 614 uqe: uqe@2400000 {
655 #address-cells = <1>; 615 #address-cells = <1>;
656 #size-cells = <1>; 616 #size-cells = <1>;
657 compatible = "fsl,qe", 617 compatible = "fsl,qe", "simple-bus";
658 ranges = <0x0 0x0 0x24 618 ranges = <0x0 0x0 0x2400000 0x40000>;
659 reg = <0x0 0x2400000 0 619 reg = <0x0 0x2400000 0x0 0x480>;
660 brg-frequency = <10000 620 brg-frequency = <100000000>;
661 bus-frequency = <20000 621 bus-frequency = <200000000>;
662 fsl,qe-num-riscs = <1> 622 fsl,qe-num-riscs = <1>;
663 fsl,qe-num-snums = <28 623 fsl,qe-num-snums = <28>;
664 624
665 qeic: qeic@80 { 625 qeic: qeic@80 {
666 compatible = " 626 compatible = "fsl,qe-ic";
667 reg = <0x80 0x 627 reg = <0x80 0x80>;
>> 628 #address-cells = <0>;
668 interrupt-cont 629 interrupt-controller;
669 #interrupt-cel 630 #interrupt-cells = <1>;
670 interrupts = < 631 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
671 < 632 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
672 }; 633 };
673 634
674 si1: si@700 { 635 si1: si@700 {
>> 636 #address-cells = <1>;
>> 637 #size-cells = <0>;
675 compatible = " 638 compatible = "fsl,ls1043-qe-si",
676 639 "fsl,t1040-qe-si";
677 reg = <0x700 0 640 reg = <0x700 0x80>;
678 }; 641 };
679 642
680 siram1: siram@1000 { 643 siram1: siram@1000 {
>> 644 #address-cells = <1>;
>> 645 #size-cells = <1>;
681 compatible = " 646 compatible = "fsl,ls1043-qe-siram",
682 647 "fsl,t1040-qe-siram";
683 reg = <0x1000 648 reg = <0x1000 0x800>;
684 }; 649 };
685 650
686 ucc@2000 { 651 ucc@2000 {
687 cell-index = < 652 cell-index = <1>;
688 reg = <0x2000 653 reg = <0x2000 0x200>;
689 interrupts = < 654 interrupts = <32>;
690 interrupt-pare 655 interrupt-parent = <&qeic>;
691 }; 656 };
692 657
693 ucc@2200 { 658 ucc@2200 {
694 cell-index = < 659 cell-index = <3>;
695 reg = <0x2200 660 reg = <0x2200 0x200>;
696 interrupts = < 661 interrupts = <34>;
697 interrupt-pare 662 interrupt-parent = <&qeic>;
698 }; 663 };
699 664
700 muram@10000 { 665 muram@10000 {
701 #address-cells 666 #address-cells = <1>;
702 #size-cells = 667 #size-cells = <1>;
703 compatible = " 668 compatible = "fsl,qe-muram", "fsl,cpm-muram";
704 ranges = <0x0 669 ranges = <0x0 0x10000 0x6000>;
705 670
706 data-only@0 { 671 data-only@0 {
707 compat 672 compatible = "fsl,qe-muram-data",
708 "fsl,c 673 "fsl,cpm-muram-data";
709 reg = 674 reg = <0x0 0x6000>;
710 }; 675 };
711 }; 676 };
712 }; 677 };
713 678
714 lpuart0: serial@2950000 { 679 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 680 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 681 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 682 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO !! 683 clocks = <&clockgen 0 0>;
719 clock-names = "ipg"; 684 clock-names = "ipg";
720 status = "disabled"; 685 status = "disabled";
721 }; 686 };
722 687
723 lpuart1: serial@2960000 { 688 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 689 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 690 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 691 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO !! 692 clocks = <&clockgen 4 0>;
728 QO <<
729 clock-names = "ipg"; 693 clock-names = "ipg";
730 status = "disabled"; 694 status = "disabled";
731 }; 695 };
732 696
733 lpuart2: serial@2970000 { 697 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 698 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 699 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 700 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO !! 701 clocks = <&clockgen 4 0>;
738 QO <<
739 clock-names = "ipg"; 702 clock-names = "ipg";
740 status = "disabled"; 703 status = "disabled";
741 }; 704 };
742 705
743 lpuart3: serial@2980000 { 706 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 707 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 708 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 709 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO !! 710 clocks = <&clockgen 4 0>;
748 QO <<
749 clock-names = "ipg"; 711 clock-names = "ipg";
750 status = "disabled"; 712 status = "disabled";
751 }; 713 };
752 714
753 lpuart4: serial@2990000 { 715 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 716 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 717 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 718 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO !! 719 clocks = <&clockgen 4 0>;
758 QO <<
759 clock-names = "ipg"; 720 clock-names = "ipg";
760 status = "disabled"; 721 status = "disabled";
761 }; 722 };
762 723
763 lpuart5: serial@29a0000 { 724 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 725 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 726 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 727 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO !! 728 clocks = <&clockgen 4 0>;
768 QO <<
769 clock-names = "ipg"; 729 clock-names = "ipg";
770 status = "disabled"; 730 status = "disabled";
771 }; 731 };
772 732
773 wdog0: watchdog@2ad0000 { 733 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls10 734 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 735 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 736 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO !! 737 clocks = <&clockgen 4 0>;
778 QO !! 738 clock-names = "wdog";
779 big-endian; 739 big-endian;
780 }; 740 };
781 741
782 edma0: dma-controller@2c00000 !! 742 edma0: edma@2c00000 {
783 #dma-cells = <2>; 743 #dma-cells = <2>;
784 compatible = "fsl,vf61 744 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 745 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 746 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 747 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 748 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 749 <0 103 0x4>;
790 interrupt-names = "edm 750 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 751 dma-channels = <32>;
792 big-endian; 752 big-endian;
793 clock-names = "dmamux0 753 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO !! 754 clocks = <&clockgen 4 0>,
795 QO !! 755 <&clockgen 4 0>;
796 <&clockgen QO <<
797 QO <<
798 }; 756 };
799 757
800 aux_bus: bus { !! 758 usb0: usb@2f00000 {
801 #address-cells = <2>; !! 759 compatible = "snps,dwc3";
802 #size-cells = <2>; !! 760 reg = <0x0 0x2f00000 0x0 0x10000>;
803 compatible = "simple-b !! 761 interrupts = <0 60 0x4>;
804 ranges; !! 762 dr_mode = "host";
805 dma-ranges = <0x0 0x0 !! 763 snps,quirk-frame-length-adjustment = <0x20>;
806 !! 764 snps,dis_rxdet_inp3_quirk;
807 usb0: usb@2f00000 { !! 765 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
808 compatible = " !! 766 status = "disabled";
809 reg = <0x0 0x2 !! 767 };
810 interrupts = < !! 768
811 dr_mode = "hos !! 769 usb1: usb@3000000 {
812 snps,quirk-fra !! 770 compatible = "snps,dwc3";
813 snps,dis_rxdet !! 771 reg = <0x0 0x3000000 0x0 0x10000>;
814 usb3-lpm-capab !! 772 interrupts = <0 61 0x4>;
815 snps,incr-burs !! 773 dr_mode = "host";
816 status = "disa !! 774 snps,quirk-frame-length-adjustment = <0x20>;
817 }; !! 775 snps,dis_rxdet_inp3_quirk;
818 !! 776 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
819 usb1: usb@3000000 { !! 777 status = "disabled";
820 compatible = " !! 778 };
821 reg = <0x0 0x3 !! 779
822 interrupts = < !! 780 usb2: usb@3100000 {
823 dr_mode = "hos !! 781 compatible = "snps,dwc3";
824 snps,quirk-fra !! 782 reg = <0x0 0x3100000 0x0 0x10000>;
825 snps,dis_rxdet !! 783 interrupts = <0 63 0x4>;
826 usb3-lpm-capab !! 784 dr_mode = "host";
827 snps,incr-burs !! 785 snps,quirk-frame-length-adjustment = <0x20>;
828 status = "disa !! 786 snps,dis_rxdet_inp3_quirk;
829 }; !! 787 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
830 !! 788 status = "disabled";
831 usb2: usb@3100000 { !! 789 };
832 compatible = " !! 790
833 reg = <0x0 0x3 !! 791 sata: sata@3200000 {
834 interrupts = < !! 792 compatible = "fsl,ls1043a-ahci";
835 dr_mode = "hos !! 793 reg = <0x0 0x3200000 0x0 0x10000>,
836 snps,quirk-fra !! 794 <0x0 0x20140520 0x0 0x4>;
837 snps,dis_rxdet !! 795 reg-names = "ahci", "sata-ecc";
838 usb3-lpm-capab !! 796 interrupts = <0 69 0x4>;
839 snps,incr-burs !! 797 clocks = <&clockgen 4 0>;
840 status = "disa !! 798 dma-coherent;
841 }; <<
842 <<
843 sata: sata@3200000 { <<
844 compatible = " <<
845 reg = <0x0 0x3 <<
846 <0x0 0 <<
847 reg-names = "a <<
848 interrupts = < <<
849 clocks = <&clo <<
850 <<
851 dma-coherent; <<
852 }; <<
853 }; 799 };
854 800
855 msi1: msi-controller1@1571000 801 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 802 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 803 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 804 msi-controller;
859 interrupts = <GIC_SPI !! 805 interrupts = <0 116 0x4>;
860 }; 806 };
861 807
862 msi2: msi-controller2@1572000 808 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 809 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 810 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 811 msi-controller;
866 interrupts = <GIC_SPI !! 812 interrupts = <0 126 0x4>;
867 }; 813 };
868 814
869 msi3: msi-controller3@1573000 815 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 816 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 817 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 818 msi-controller;
873 interrupts = <GIC_SPI !! 819 interrupts = <0 160 0x4>;
874 }; 820 };
875 821
876 pcie1: pcie@3400000 { 822 pcie1: pcie@3400000 {
877 compatible = "fsl,ls10 823 compatible = "fsl,ls1043a-pcie";
878 reg = <0x00 0x03400000 !! 824 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
879 <0x40 0x00000000 !! 825 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 826 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 827 interrupts = <0 118 0x4>, /* controller interrupt */
882 <GIC_SPI !! 828 <0 117 0x4>; /* PME interrupt */
883 interrupt-names = "pme !! 829 interrupt-names = "intr", "pme";
884 #address-cells = <3>; 830 #address-cells = <3>;
885 #size-cells = <2>; 831 #size-cells = <2>;
886 device_type = "pci"; 832 device_type = "pci";
>> 833 dma-coherent;
887 num-viewport = <6>; 834 num-viewport = <6>;
888 bus-range = <0x0 0xff> 835 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 836 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 837 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 838 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 839 #interrupt-cells = <1>;
893 interrupt-map-mask = < 840 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 841 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 842 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 843 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 844 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg <<
899 big-endian; <<
900 status = "disabled"; 845 status = "disabled";
901 }; 846 };
902 847
903 pcie2: pcie@3500000 { 848 pcie2: pcie@3500000 {
904 compatible = "fsl,ls10 849 compatible = "fsl,ls1043a-pcie";
905 reg = <0x00 0x03500000 !! 850 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
906 <0x48 0x00000000 !! 851 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 852 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 853 interrupts = <0 128 0x4>,
909 <GIC_SPI !! 854 <0 127 0x4>;
910 interrupt-names = "pme !! 855 interrupt-names = "intr", "pme";
911 #address-cells = <3>; 856 #address-cells = <3>;
912 #size-cells = <2>; 857 #size-cells = <2>;
913 device_type = "pci"; 858 device_type = "pci";
>> 859 dma-coherent;
914 num-viewport = <6>; 860 num-viewport = <6>;
915 bus-range = <0x0 0xff> 861 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 862 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 863 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 864 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 865 #interrupt-cells = <1>;
920 interrupt-map-mask = < 866 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 867 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 868 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 869 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 870 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg <<
926 big-endian; <<
927 status = "disabled"; 871 status = "disabled";
928 }; 872 };
929 873
930 pcie3: pcie@3600000 { 874 pcie3: pcie@3600000 {
931 compatible = "fsl,ls10 875 compatible = "fsl,ls1043a-pcie";
932 reg = <0x00 0x03600000 !! 876 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
933 <0x50 0x00000000 !! 877 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 878 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 879 interrupts = <0 162 0x4>,
936 <GIC_SPI !! 880 <0 161 0x4>;
937 interrupt-names = "pme !! 881 interrupt-names = "intr", "pme";
938 #address-cells = <3>; 882 #address-cells = <3>;
939 #size-cells = <2>; 883 #size-cells = <2>;
940 device_type = "pci"; 884 device_type = "pci";
>> 885 dma-coherent;
941 num-viewport = <6>; 886 num-viewport = <6>;
942 bus-range = <0x0 0xff> 887 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 888 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 889 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 890 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 891 #interrupt-cells = <1>;
947 interrupt-map-mask = < 892 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 893 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 894 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 895 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 896 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg <<
953 big-endian; <<
954 status = "disabled"; 897 status = "disabled";
955 }; 898 };
956 899
957 qdma: dma-controller@8380000 { 900 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls10 !! 901 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
959 reg = <0x0 0x8380000 0 902 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
960 <0x0 0x8390000 0 903 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
961 <0x0 0x83a0000 0 904 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
962 interrupts = <GIC_SPI 905 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 906 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 907 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 908 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 909 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "qdm 910 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", 911 "qdma-queue1", "qdma-queue2", "qdma-queue3";
969 #dma-cells = <1>; <<
970 dma-channels = <8>; 912 dma-channels = <8>;
971 block-number = <1>; 913 block-number = <1>;
972 block-offset = <0x1000 914 block-offset = <0x10000>;
973 fsl,dma-queues = <2>; 915 fsl,dma-queues = <2>;
974 status-sizes = <64>; 916 status-sizes = <64>;
975 queue-sizes = <64 64>; 917 queue-sizes = <64 64>;
976 big-endian; 918 big-endian;
977 }; 919 };
978 920
979 rcpm: wakeup-controller@1ee214 !! 921 rcpm: power-controller@1ee2140 {
980 compatible = "fsl,ls10 922 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
981 reg = <0x0 0x1ee2140 0 923 reg = <0x0 0x1ee2140 0x0 0x4>;
982 #fsl,rcpm-wakeup-cells 924 #fsl,rcpm-wakeup-cells = <1>;
983 }; 925 };
984 926
985 ftm_alarm0: rtc@29d0000 { !! 927 ftm_alarm0: timer@29d0000 {
986 compatible = "fsl,ls10 928 compatible = "fsl,ls1043a-ftm-alarm";
987 reg = <0x0 0x29d0000 0 929 reg = <0x0 0x29d0000 0x0 0x10000>;
988 fsl,rcpm-wakeup = <&rc 930 fsl,rcpm-wakeup = <&rcpm 0x20000>;
989 interrupts = <GIC_SPI 931 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
990 big-endian; 932 big-endian;
991 }; 933 };
992 }; 934 };
993 935
994 firmware { 936 firmware {
995 optee { 937 optee {
996 compatible = "linaro,o 938 compatible = "linaro,optee-tz";
997 method = "smc"; 939 method = "smc";
998 }; 940 };
999 }; 941 };
1000 942
1001 }; 943 };
1002 944
1003 #include "qoriq-qman-portals.dtsi" 945 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 946 #include "qoriq-bman-portals.dtsi"
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