1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 * 4 *
5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP 6 * Copyright 2018, 2020 NXP
7 * 7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */ 9 */
10 10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> <<
15 14
16 / { 15 / {
17 compatible = "fsl,ls1043a"; 16 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
19 #address-cells = <2>; 18 #address-cells = <2>;
20 #size-cells = <2>; 19 #size-cells = <2>;
21 20
22 aliases { 21 aliases {
23 crypto = &crypto; 22 crypto = &crypto;
24 fman0 = &fman0; 23 fman0 = &fman0;
25 ethernet0 = &enet0; 24 ethernet0 = &enet0;
26 ethernet1 = &enet1; 25 ethernet1 = &enet1;
27 ethernet2 = &enet2; 26 ethernet2 = &enet2;
28 ethernet3 = &enet3; 27 ethernet3 = &enet3;
29 ethernet4 = &enet4; 28 ethernet4 = &enet4;
30 ethernet5 = &enet5; 29 ethernet5 = &enet5;
31 ethernet6 = &enet6; 30 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; 31 rtc1 = &ftm_alarm0;
33 }; 32 };
34 33
35 cpus { 34 cpus {
36 #address-cells = <1>; 35 #address-cells = <1>;
37 #size-cells = <0>; 36 #size-cells = <0>;
38 37
39 /* 38 /*
40 * We expect the enable-method 39 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 40 * is dependent on the SoC FW, which will fill this in.
42 * 41 *
43 * Currently supported enable- 42 * Currently supported enable-method is psci v0.2
44 */ 43 */
45 cpu0: cpu@0 { 44 cpu0: cpu@0 {
46 device_type = "cpu"; 45 device_type = "cpu";
47 compatible = "arm,cort 46 compatible = "arm,cortex-a53";
48 reg = <0x0>; 47 reg = <0x0>;
49 clocks = <&clockgen QO 48 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
50 next-level-cache = <&l 49 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP 50 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>; 51 #cooling-cells = <2>;
53 }; 52 };
54 53
55 cpu1: cpu@1 { 54 cpu1: cpu@1 {
56 device_type = "cpu"; 55 device_type = "cpu";
57 compatible = "arm,cort 56 compatible = "arm,cortex-a53";
58 reg = <0x1>; 57 reg = <0x1>;
59 clocks = <&clockgen QO 58 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 next-level-cache = <&l 59 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>; 61 #cooling-cells = <2>;
63 }; 62 };
64 63
65 cpu2: cpu@2 { 64 cpu2: cpu@2 {
66 device_type = "cpu"; 65 device_type = "cpu";
67 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
68 reg = <0x2>; 67 reg = <0x2>;
69 clocks = <&clockgen QO 68 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
70 next-level-cache = <&l 69 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP 70 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 71 #cooling-cells = <2>;
73 }; 72 };
74 73
75 cpu3: cpu@3 { 74 cpu3: cpu@3 {
76 device_type = "cpu"; 75 device_type = "cpu";
77 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
78 reg = <0x3>; 77 reg = <0x3>;
79 clocks = <&clockgen QO 78 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
80 next-level-cache = <&l 79 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP 80 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>; 81 #cooling-cells = <2>;
83 }; 82 };
84 83
85 l2: l2-cache { 84 l2: l2-cache {
86 compatible = "cache"; 85 compatible = "cache";
87 cache-level = <2>; <<
88 cache-unified; <<
89 }; 86 };
90 }; 87 };
91 88
92 idle-states { 89 idle-states {
93 /* 90 /*
94 * PSCI node is not added defa 91 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to u 92 * parts if it determines to use PSCI.
96 */ 93 */
97 entry-method = "psci"; 94 entry-method = "psci";
98 95
99 CPU_PH20: cpu-ph20 { 96 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle 97 compatible = "arm,idle-state";
101 idle-state-name = "PH2 98 idle-state-name = "PH20";
102 arm,psci-suspend-param 99 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <10 100 entry-latency-us = <1000>;
104 exit-latency-us = <100 101 exit-latency-us = <1000>;
105 min-residency-us = <30 102 min-residency-us = <3000>;
106 }; 103 };
107 }; 104 };
108 105
109 memory@80000000 { 106 memory@80000000 {
110 device_type = "memory"; 107 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 108 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 109 /* DRAM space 1, size: 2GiB DRAM */
113 }; 110 };
114 111
115 reserved-memory { 112 reserved-memory {
116 #address-cells = <2>; 113 #address-cells = <2>;
117 #size-cells = <2>; 114 #size-cells = <2>;
118 ranges; 115 ranges;
119 116
120 bman_fbpr: bman-fbpr { 117 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 118 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 119 size = <0 0x1000000>;
123 alignment = <0 0x10000 120 alignment = <0 0x1000000>;
124 no-map; 121 no-map;
125 }; 122 };
126 123
127 qman_fqd: qman-fqd { 124 qman_fqd: qman-fqd {
128 compatible = "shared-d 125 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 126 size = <0 0x400000>;
130 alignment = <0 0x40000 127 alignment = <0 0x400000>;
131 no-map; 128 no-map;
132 }; 129 };
133 130
134 qman_pfdr: qman-pfdr { 131 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 132 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 133 size = <0 0x2000000>;
137 alignment = <0 0x20000 134 alignment = <0 0x2000000>;
138 no-map; 135 no-map;
139 }; 136 };
140 }; 137 };
141 138
142 sysclk: sysclk { 139 sysclk: sysclk {
143 compatible = "fixed-clock"; 140 compatible = "fixed-clock";
144 #clock-cells = <0>; 141 #clock-cells = <0>;
145 clock-frequency = <100000000>; 142 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 143 clock-output-names = "sysclk";
147 }; 144 };
148 145
149 reboot { 146 reboot {
150 compatible = "syscon-reboot"; !! 147 compatible ="syscon-reboot";
151 regmap = <&dcfg>; 148 regmap = <&dcfg>;
152 offset = <0xb0>; 149 offset = <0xb0>;
153 mask = <0x02>; 150 mask = <0x02>;
154 }; 151 };
155 152
156 thermal-zones { 153 thermal-zones {
157 ddr-thermal { !! 154 ddr-controller {
158 polling-delay-passive 155 polling-delay-passive = <1000>;
159 polling-delay = <5000> 156 polling-delay = <5000>;
160 thermal-sensors = <&tm 157 thermal-sensors = <&tmu 0>;
161 158
162 trips { 159 trips {
163 ddr-ctrler-ale 160 ddr-ctrler-alert {
164 temper 161 temperature = <85000>;
165 hyster 162 hysteresis = <2000>;
166 type = 163 type = "passive";
167 }; 164 };
168 165
169 ddr-ctrler-cri 166 ddr-ctrler-crit {
170 temper 167 temperature = <95000>;
171 hyster 168 hysteresis = <2000>;
172 type = 169 type = "critical";
173 }; 170 };
174 }; 171 };
175 }; 172 };
176 173
177 serdes-thermal { !! 174 serdes {
178 polling-delay-passive 175 polling-delay-passive = <1000>;
179 polling-delay = <5000> 176 polling-delay = <5000>;
180 thermal-sensors = <&tm 177 thermal-sensors = <&tmu 1>;
181 178
182 trips { 179 trips {
183 serdes-alert { 180 serdes-alert {
184 temper 181 temperature = <85000>;
185 hyster 182 hysteresis = <2000>;
186 type = 183 type = "passive";
187 }; 184 };
188 185
189 serdes-crit { 186 serdes-crit {
190 temper 187 temperature = <95000>;
191 hyster 188 hysteresis = <2000>;
192 type = 189 type = "critical";
193 }; 190 };
194 }; 191 };
195 }; 192 };
196 193
197 fman-thermal { !! 194 fman {
198 polling-delay-passive 195 polling-delay-passive = <1000>;
199 polling-delay = <5000> 196 polling-delay = <5000>;
200 thermal-sensors = <&tm 197 thermal-sensors = <&tmu 2>;
201 198
202 trips { 199 trips {
203 fman-alert { 200 fman-alert {
204 temper 201 temperature = <85000>;
205 hyster 202 hysteresis = <2000>;
206 type = 203 type = "passive";
207 }; 204 };
208 205
209 fman-crit { 206 fman-crit {
210 temper 207 temperature = <95000>;
211 hyster 208 hysteresis = <2000>;
212 type = 209 type = "critical";
213 }; 210 };
214 }; 211 };
215 }; 212 };
216 213
217 cluster-thermal { !! 214 core-cluster {
218 polling-delay-passive 215 polling-delay-passive = <1000>;
219 polling-delay = <5000> 216 polling-delay = <5000>;
220 thermal-sensors = <&tm 217 thermal-sensors = <&tmu 3>;
221 218
222 trips { 219 trips {
223 core_cluster_a 220 core_cluster_alert: core-cluster-alert {
224 temper 221 temperature = <85000>;
225 hyster 222 hysteresis = <2000>;
226 type = 223 type = "passive";
227 }; 224 };
228 225
229 core_cluster_c 226 core_cluster_crit: core-cluster-crit {
230 temper 227 temperature = <95000>;
231 hyster 228 hysteresis = <2000>;
232 type = 229 type = "critical";
233 }; 230 };
234 }; 231 };
235 232
236 cooling-maps { 233 cooling-maps {
237 map0 { 234 map0 {
238 trip = 235 trip = <&core_cluster_alert>;
239 coolin 236 cooling-device =
240 237 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
241 238 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
242 239 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
243 240 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 }; 241 };
245 }; 242 };
246 }; 243 };
247 244
248 sec-thermal { !! 245 sec {
249 polling-delay-passive 246 polling-delay-passive = <1000>;
250 polling-delay = <5000> 247 polling-delay = <5000>;
251 thermal-sensors = <&tm 248 thermal-sensors = <&tmu 4>;
252 249
253 trips { 250 trips {
254 sec-alert { 251 sec-alert {
255 temper 252 temperature = <85000>;
256 hyster 253 hysteresis = <2000>;
257 type = 254 type = "passive";
258 }; 255 };
259 256
260 sec-crit { 257 sec-crit {
261 temper 258 temperature = <95000>;
262 hyster 259 hysteresis = <2000>;
263 type = 260 type = "critical";
264 }; 261 };
265 }; 262 };
266 }; 263 };
267 }; 264 };
268 265
269 timer { 266 timer {
270 compatible = "arm,armv8-timer" 267 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 268 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 269 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 270 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 271 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 272 fsl,erratum-a008585;
276 }; 273 };
277 274
278 pmu { 275 pmu {
279 compatible = "arm,cortex-a53-p !! 276 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 277 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 278 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 279 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 280 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 281 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 282 <&cpu1>,
286 <&cpu2>, 283 <&cpu2>,
287 <&cpu3>; 284 <&cpu3>;
288 }; 285 };
289 286
290 gic: interrupt-controller@1400000 { 287 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 288 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 289 #interrupt-cells = <3>;
293 interrupt-controller; 290 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 291 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 292 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 293 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 294 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 295 interrupts = <1 9 0xf08>;
299 }; 296 };
300 297
301 soc: soc { 298 soc: soc {
302 compatible = "simple-bus"; 299 compatible = "simple-bus";
303 #address-cells = <2>; 300 #address-cells = <2>;
304 #size-cells = <2>; 301 #size-cells = <2>;
305 ranges; 302 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 <<
307 dma-coherent; <<
308 303
309 clockgen: clocking@1ee1000 { 304 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 305 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 306 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 307 #clock-cells = <2>;
313 clocks = <&sysclk>; 308 clocks = <&sysclk>;
314 }; 309 };
315 310
316 scfg: scfg@1570000 { 311 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 312 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 313 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 314 big-endian;
320 #address-cells = <1>; 315 #address-cells = <1>;
321 #size-cells = <1>; 316 #size-cells = <1>;
322 ranges = <0x0 0x0 0x15 317 ranges = <0x0 0x0 0x1570000 0x10000>;
323 318
324 extirq: interrupt-cont 319 extirq: interrupt-controller@1ac {
325 compatible = " 320 compatible = "fsl,ls1043a-extirq";
326 #interrupt-cel 321 #interrupt-cells = <2>;
327 #address-cells 322 #address-cells = <0>;
328 interrupt-cont 323 interrupt-controller;
329 reg = <0x1ac 4 324 reg = <0x1ac 4>;
330 interrupt-map 325 interrupt-map =
331 <0 0 & 326 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 & 327 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 & 328 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 & 329 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 & 330 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 & 331 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 & 332 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 & 333 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 & 334 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 & 335 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 336 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 337 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map- !! 338 interrupt-map-mask = <0xffffffff 0x0>;
344 }; 339 };
345 }; 340 };
346 341
347 crypto: crypto@1700000 { 342 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 343 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 344 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 345 fsl,sec-era = <3>;
351 #address-cells = <1>; 346 #address-cells = <1>;
352 #size-cells = <1>; 347 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 348 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 349 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 350 interrupts = <0 75 0x4>;
356 dma-coherent; 351 dma-coherent;
357 352
358 sec_jr0: jr@10000 { 353 sec_jr0: jr@10000 {
359 compatible = " 354 compatible = "fsl,sec-v5.4-job-ring",
360 " 355 "fsl,sec-v5.0-job-ring",
361 " 356 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 !! 357 reg = <0x10000 0x10000>;
363 interrupts = < !! 358 interrupts = <0 71 0x4>;
364 }; 359 };
365 360
366 sec_jr1: jr@20000 { 361 sec_jr1: jr@20000 {
367 compatible = " 362 compatible = "fsl,sec-v5.4-job-ring",
368 " 363 "fsl,sec-v5.0-job-ring",
369 " 364 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 !! 365 reg = <0x20000 0x10000>;
371 interrupts = < !! 366 interrupts = <0 72 0x4>;
372 }; 367 };
373 368
374 sec_jr2: jr@30000 { 369 sec_jr2: jr@30000 {
375 compatible = " 370 compatible = "fsl,sec-v5.4-job-ring",
376 " 371 "fsl,sec-v5.0-job-ring",
377 " 372 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 !! 373 reg = <0x30000 0x10000>;
379 interrupts = < !! 374 interrupts = <0 73 0x4>;
380 }; 375 };
381 376
382 sec_jr3: jr@40000 { 377 sec_jr3: jr@40000 {
383 compatible = " 378 compatible = "fsl,sec-v5.4-job-ring",
384 " 379 "fsl,sec-v5.0-job-ring",
385 " 380 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 !! 381 reg = <0x40000 0x10000>;
387 interrupts = < !! 382 interrupts = <0 74 0x4>;
388 }; 383 };
389 }; 384 };
390 385
391 sfp: efuse@1e80000 { <<
392 compatible = "fsl,ls10 <<
393 reg = <0x0 0x1e80000 0 <<
394 clocks = <&clockgen QO <<
395 QO <<
396 clock-names = "sfp"; <<
397 }; <<
398 <<
399 dcfg: dcfg@1ee0000 { 386 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 387 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 !! 388 reg = <0x0 0x1ee0000 0x0 0x10000>;
402 big-endian; 389 big-endian;
403 }; 390 };
404 391
405 ifc: memory-controller@1530000 !! 392 ifc: ifc@1530000 {
406 compatible = "fsl,ifc" !! 393 compatible = "fsl,ifc", "simple-bus";
407 reg = <0x0 0x1530000 0 394 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 395 interrupts = <0 43 0x4>;
409 }; 396 };
410 397
411 qspi: spi@1550000 { 398 qspi: spi@1550000 {
412 compatible = "fsl,ls10 399 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 400 #address-cells = <1>;
414 #size-cells = <0>; 401 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 402 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 403 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 404 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 405 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 406 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO 407 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QO 408 QORIQ_CLK_PLL_DIV(1)>,
422 <&clockgen QO 409 <&clockgen QORIQ_CLK_PLATFORM_PLL
423 QO 410 QORIQ_CLK_PLL_DIV(1)>;
424 status = "disabled"; 411 status = "disabled";
425 }; 412 };
426 413
427 esdhc: mmc@1560000 { !! 414 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 415 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 416 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 417 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 418 clock-frequency = <0>;
432 voltage-ranges = <1800 419 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 420 sdhci,auto-cmd12;
>> 421 big-endian;
434 bus-width = <4>; 422 bus-width = <4>;
435 }; 423 };
436 424
437 ddr: memory-controller@1080000 425 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 426 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 427 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 428 interrupts = <0 144 0x4>;
>> 429 big-endian;
441 }; 430 };
442 431
443 tmu: tmu@1f00000 { 432 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 433 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 434 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 435 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 436 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration = !! 437 fsl,tmu-calibration = <0x00000000 0x00000023
449 <0x000 !! 438 0x00000001 0x0000002a
450 <0x000 !! 439 0x00000002 0x00000031
451 <0x000 !! 440 0x00000003 0x00000037
452 <0x000 !! 441 0x00000004 0x0000003e
453 <0x000 !! 442 0x00000005 0x00000044
454 <0x000 !! 443 0x00000006 0x0000004b
455 <0x000 !! 444 0x00000007 0x00000051
456 <0x000 !! 445 0x00000008 0x00000058
457 <0x000 !! 446 0x00000009 0x0000005e
458 <0x000 !! 447 0x0000000a 0x00000065
459 <0x000 !! 448 0x0000000b 0x0000006b
460 <0x000 !! 449
461 !! 450 0x00010000 0x00000023
462 <0x000 !! 451 0x00010001 0x0000002b
463 <0x000 !! 452 0x00010002 0x00000033
464 <0x000 !! 453 0x00010003 0x0000003b
465 <0x000 !! 454 0x00010004 0x00000043
466 <0x000 !! 455 0x00010005 0x0000004b
467 <0x000 !! 456 0x00010006 0x00000054
468 <0x000 !! 457 0x00010007 0x0000005c
469 <0x000 !! 458 0x00010008 0x00000064
470 <0x000 !! 459 0x00010009 0x0000006c
471 <0x000 !! 460
472 !! 461 0x00020000 0x00000021
473 <0x000 !! 462 0x00020001 0x0000002c
474 <0x000 !! 463 0x00020002 0x00000036
475 <0x000 !! 464 0x00020003 0x00000040
476 <0x000 !! 465 0x00020004 0x0000004b
477 <0x000 !! 466 0x00020005 0x00000055
478 <0x000 !! 467 0x00020006 0x0000005f
479 <0x000 !! 468
480 !! 469 0x00030000 0x00000013
481 <0x000 !! 470 0x00030001 0x0000001d
482 <0x000 !! 471 0x00030002 0x00000028
483 <0x000 !! 472 0x00030003 0x00000032
484 <0x000 !! 473 0x00030004 0x0000003d
485 <0x000 !! 474 0x00030005 0x00000047
486 <0x000 !! 475 0x00030006 0x00000052
487 <0x000 !! 476 0x00030007 0x0000005c>;
488 <0x000 <<
489 #thermal-sensor-cells 477 #thermal-sensor-cells = <1>;
490 }; 478 };
491 479
492 qman: qman@1880000 { 480 qman: qman@1880000 {
493 compatible = "fsl,qman 481 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 482 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 483 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 484 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 485 };
498 486
499 bman: bman@1890000 { 487 bman: bman@1890000 {
500 compatible = "fsl,bman 488 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 489 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 490 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 491 memory-region = <&bman_fbpr>;
504 }; 492 };
505 493
506 bportals: bman-portals-bus@508 !! 494 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 495 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 496 };
509 497
510 qportals: qman-portals-bus@500 !! 498 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 499 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 500 };
513 501
514 dspi0: spi@2100000 { 502 dspi0: spi@2100000 {
515 compatible = "fsl,ls10 503 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 504 #address-cells = <1>;
517 #size-cells = <0>; 505 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 506 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 507 interrupts = <0 64 0x4>;
>> 508 clock-names = "dspi";
>> 509 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
>> 510 QORIQ_CLK_PLL_DIV(1)>;
>> 511 spi-num-chipselects = <5>;
>> 512 big-endian;
>> 513 status = "disabled";
>> 514 };
>> 515
>> 516 dspi1: spi@2110000 {
>> 517 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 518 #address-cells = <1>;
>> 519 #size-cells = <0>;
>> 520 reg = <0x0 0x2110000 0x0 0x10000>;
>> 521 interrupts = <0 65 0x4>;
520 clock-names = "dspi"; 522 clock-names = "dspi";
521 clocks = <&clockgen QO 523 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
522 QO 524 QORIQ_CLK_PLL_DIV(1)>;
523 spi-num-chipselects = 525 spi-num-chipselects = <5>;
524 big-endian; 526 big-endian;
525 status = "disabled"; 527 status = "disabled";
526 }; 528 };
527 529
528 i2c0: i2c@2180000 { 530 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 !! 531 compatible = "fsl,vf610-i2c";
530 #address-cells = <1>; 532 #address-cells = <1>;
531 #size-cells = <0>; 533 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 534 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 535 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 536 clock-names = "i2c";
535 clocks = <&clockgen QO 537 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
536 QO 538 QORIQ_CLK_PLL_DIV(1)>;
537 dmas = <&edma0 1 38>, !! 539 dmas = <&edma0 1 39>,
538 <&edma0 1 39>; !! 540 <&edma0 1 38>;
539 dma-names = "rx", "tx" !! 541 dma-names = "tx", "rx";
540 status = "disabled"; 542 status = "disabled";
541 }; 543 };
542 544
543 i2c1: i2c@2190000 { 545 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 !! 546 compatible = "fsl,vf610-i2c";
545 #address-cells = <1>; 547 #address-cells = <1>;
546 #size-cells = <0>; 548 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 549 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 550 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 551 clock-names = "i2c";
550 clocks = <&clockgen QO 552 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
551 QO 553 QORIQ_CLK_PLL_DIV(1)>;
552 scl-gpios = <&gpio4 2 <<
553 status = "disabled"; 554 status = "disabled";
554 }; 555 };
555 556
556 i2c2: i2c@21a0000 { 557 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 !! 558 compatible = "fsl,vf610-i2c";
558 #address-cells = <1>; 559 #address-cells = <1>;
559 #size-cells = <0>; 560 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 561 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 562 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 563 clock-names = "i2c";
563 clocks = <&clockgen QO 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564 QO 565 QORIQ_CLK_PLL_DIV(1)>;
565 scl-gpios = <&gpio4 10 <<
566 status = "disabled"; 566 status = "disabled";
567 }; 567 };
568 568
569 i2c3: i2c@21b0000 { 569 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 !! 570 compatible = "fsl,vf610-i2c";
571 #address-cells = <1>; 571 #address-cells = <1>;
572 #size-cells = <0>; 572 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 573 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 574 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 575 clock-names = "i2c";
576 clocks = <&clockgen QO 576 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
577 QO 577 QORIQ_CLK_PLL_DIV(1)>;
578 scl-gpios = <&gpio4 12 <<
579 status = "disabled"; 578 status = "disabled";
580 }; 579 };
581 580
582 duart0: serial@21c0500 { 581 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 582 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 583 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 584 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO 585 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
587 QO 586 QORIQ_CLK_PLL_DIV(1)>;
588 }; 587 };
589 588
590 duart1: serial@21c0600 { 589 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 590 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 591 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 592 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO 593 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
595 QO 594 QORIQ_CLK_PLL_DIV(1)>;
596 }; 595 };
597 596
598 duart2: serial@21d0500 { 597 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 598 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 599 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 600 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO 601 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
603 QO 602 QORIQ_CLK_PLL_DIV(1)>;
604 }; 603 };
605 604
606 duart3: serial@21d0600 { 605 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 606 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 607 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 608 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO 609 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
611 QO 610 QORIQ_CLK_PLL_DIV(1)>;
612 }; 611 };
613 612
614 gpio1: gpio@2300000 { 613 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 614 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 615 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 616 interrupts = <0 66 0x4>;
618 gpio-controller; 617 gpio-controller;
619 #gpio-cells = <2>; 618 #gpio-cells = <2>;
620 interrupt-controller; 619 interrupt-controller;
621 #interrupt-cells = <2> 620 #interrupt-cells = <2>;
622 }; 621 };
623 622
624 gpio2: gpio@2310000 { 623 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 624 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 625 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 626 interrupts = <0 67 0x4>;
628 gpio-controller; 627 gpio-controller;
629 #gpio-cells = <2>; 628 #gpio-cells = <2>;
630 interrupt-controller; 629 interrupt-controller;
631 #interrupt-cells = <2> 630 #interrupt-cells = <2>;
632 }; 631 };
633 632
634 gpio3: gpio@2320000 { 633 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 634 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 635 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 636 interrupts = <0 68 0x4>;
638 gpio-controller; 637 gpio-controller;
639 #gpio-cells = <2>; 638 #gpio-cells = <2>;
640 interrupt-controller; 639 interrupt-controller;
641 #interrupt-cells = <2> 640 #interrupt-cells = <2>;
642 }; 641 };
643 642
644 gpio4: gpio@2330000 { 643 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 644 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 645 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 646 interrupts = <0 134 0x4>;
648 gpio-controller; 647 gpio-controller;
649 #gpio-cells = <2>; 648 #gpio-cells = <2>;
650 interrupt-controller; 649 interrupt-controller;
651 #interrupt-cells = <2> 650 #interrupt-cells = <2>;
652 }; 651 };
653 652
654 uqe: uqe-bus@2400000 { !! 653 uqe: uqe@2400000 {
655 #address-cells = <1>; 654 #address-cells = <1>;
656 #size-cells = <1>; 655 #size-cells = <1>;
657 compatible = "fsl,qe", 656 compatible = "fsl,qe", "simple-bus";
658 ranges = <0x0 0x0 0x24 657 ranges = <0x0 0x0 0x2400000 0x40000>;
659 reg = <0x0 0x2400000 0 658 reg = <0x0 0x2400000 0x0 0x480>;
660 brg-frequency = <10000 659 brg-frequency = <100000000>;
661 bus-frequency = <20000 660 bus-frequency = <200000000>;
662 fsl,qe-num-riscs = <1> 661 fsl,qe-num-riscs = <1>;
663 fsl,qe-num-snums = <28 662 fsl,qe-num-snums = <28>;
664 663
665 qeic: qeic@80 { 664 qeic: qeic@80 {
666 compatible = " 665 compatible = "fsl,qe-ic";
667 reg = <0x80 0x 666 reg = <0x80 0x80>;
>> 667 #address-cells = <0>;
668 interrupt-cont 668 interrupt-controller;
669 #interrupt-cel 669 #interrupt-cells = <1>;
670 interrupts = < 670 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
671 < 671 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
672 }; 672 };
673 673
674 si1: si@700 { 674 si1: si@700 {
>> 675 #address-cells = <1>;
>> 676 #size-cells = <0>;
675 compatible = " 677 compatible = "fsl,ls1043-qe-si",
676 678 "fsl,t1040-qe-si";
677 reg = <0x700 0 679 reg = <0x700 0x80>;
678 }; 680 };
679 681
680 siram1: siram@1000 { 682 siram1: siram@1000 {
>> 683 #address-cells = <1>;
>> 684 #size-cells = <1>;
681 compatible = " 685 compatible = "fsl,ls1043-qe-siram",
682 686 "fsl,t1040-qe-siram";
683 reg = <0x1000 687 reg = <0x1000 0x800>;
684 }; 688 };
685 689
686 ucc@2000 { 690 ucc@2000 {
687 cell-index = < 691 cell-index = <1>;
688 reg = <0x2000 692 reg = <0x2000 0x200>;
689 interrupts = < 693 interrupts = <32>;
690 interrupt-pare 694 interrupt-parent = <&qeic>;
691 }; 695 };
692 696
693 ucc@2200 { 697 ucc@2200 {
694 cell-index = < 698 cell-index = <3>;
695 reg = <0x2200 699 reg = <0x2200 0x200>;
696 interrupts = < 700 interrupts = <34>;
697 interrupt-pare 701 interrupt-parent = <&qeic>;
698 }; 702 };
699 703
700 muram@10000 { 704 muram@10000 {
701 #address-cells 705 #address-cells = <1>;
702 #size-cells = 706 #size-cells = <1>;
703 compatible = " 707 compatible = "fsl,qe-muram", "fsl,cpm-muram";
704 ranges = <0x0 708 ranges = <0x0 0x10000 0x6000>;
705 709
706 data-only@0 { 710 data-only@0 {
707 compat 711 compatible = "fsl,qe-muram-data",
708 "fsl,c 712 "fsl,cpm-muram-data";
709 reg = 713 reg = <0x0 0x6000>;
710 }; 714 };
711 }; 715 };
712 }; 716 };
713 717
714 lpuart0: serial@2950000 { 718 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 719 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 720 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 721 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO 722 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
719 clock-names = "ipg"; 723 clock-names = "ipg";
720 status = "disabled"; 724 status = "disabled";
721 }; 725 };
722 726
723 lpuart1: serial@2960000 { 727 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 728 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 729 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 730 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO 731 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
728 QO 732 QORIQ_CLK_PLL_DIV(1)>;
729 clock-names = "ipg"; 733 clock-names = "ipg";
730 status = "disabled"; 734 status = "disabled";
731 }; 735 };
732 736
733 lpuart2: serial@2970000 { 737 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 738 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 739 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 740 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO 741 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
738 QO 742 QORIQ_CLK_PLL_DIV(1)>;
739 clock-names = "ipg"; 743 clock-names = "ipg";
740 status = "disabled"; 744 status = "disabled";
741 }; 745 };
742 746
743 lpuart3: serial@2980000 { 747 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 748 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 749 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 750 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO 751 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
748 QO 752 QORIQ_CLK_PLL_DIV(1)>;
749 clock-names = "ipg"; 753 clock-names = "ipg";
750 status = "disabled"; 754 status = "disabled";
751 }; 755 };
752 756
753 lpuart4: serial@2990000 { 757 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 758 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 759 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 760 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO 761 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
758 QO 762 QORIQ_CLK_PLL_DIV(1)>;
759 clock-names = "ipg"; 763 clock-names = "ipg";
760 status = "disabled"; 764 status = "disabled";
761 }; 765 };
762 766
763 lpuart5: serial@29a0000 { 767 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 768 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 769 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 770 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO 771 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
768 QO 772 QORIQ_CLK_PLL_DIV(1)>;
769 clock-names = "ipg"; 773 clock-names = "ipg";
770 status = "disabled"; 774 status = "disabled";
771 }; 775 };
772 776
773 wdog0: watchdog@2ad0000 { 777 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls10 778 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 779 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 780 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO 781 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
778 QO 782 QORIQ_CLK_PLL_DIV(1)>;
>> 783 clock-names = "wdog";
779 big-endian; 784 big-endian;
780 }; 785 };
781 786
782 edma0: dma-controller@2c00000 !! 787 edma0: edma@2c00000 {
783 #dma-cells = <2>; 788 #dma-cells = <2>;
784 compatible = "fsl,vf61 789 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 790 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 791 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 792 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 793 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 794 <0 103 0x4>;
790 interrupt-names = "edm 795 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 796 dma-channels = <32>;
792 big-endian; 797 big-endian;
793 clock-names = "dmamux0 798 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO 799 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
795 QO 800 QORIQ_CLK_PLL_DIV(1)>,
796 <&clockgen QO 801 <&clockgen QORIQ_CLK_PLATFORM_PLL
797 QO 802 QORIQ_CLK_PLL_DIV(1)>;
798 }; 803 };
799 804
800 aux_bus: bus { !! 805 usb0: usb@2f00000 {
801 #address-cells = <2>; !! 806 compatible = "snps,dwc3";
802 #size-cells = <2>; !! 807 reg = <0x0 0x2f00000 0x0 0x10000>;
803 compatible = "simple-b !! 808 interrupts = <0 60 0x4>;
804 ranges; !! 809 dr_mode = "host";
805 dma-ranges = <0x0 0x0 !! 810 snps,quirk-frame-length-adjustment = <0x20>;
806 !! 811 snps,dis_rxdet_inp3_quirk;
807 usb0: usb@2f00000 { !! 812 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
808 compatible = " !! 813 status = "disabled";
809 reg = <0x0 0x2 !! 814 };
810 interrupts = < !! 815
811 dr_mode = "hos !! 816 usb1: usb@3000000 {
812 snps,quirk-fra !! 817 compatible = "snps,dwc3";
813 snps,dis_rxdet !! 818 reg = <0x0 0x3000000 0x0 0x10000>;
814 usb3-lpm-capab !! 819 interrupts = <0 61 0x4>;
815 snps,incr-burs !! 820 dr_mode = "host";
816 status = "disa !! 821 snps,quirk-frame-length-adjustment = <0x20>;
817 }; !! 822 snps,dis_rxdet_inp3_quirk;
818 !! 823 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
819 usb1: usb@3000000 { !! 824 status = "disabled";
820 compatible = " !! 825 };
821 reg = <0x0 0x3 !! 826
822 interrupts = < !! 827 usb2: usb@3100000 {
823 dr_mode = "hos !! 828 compatible = "snps,dwc3";
824 snps,quirk-fra !! 829 reg = <0x0 0x3100000 0x0 0x10000>;
825 snps,dis_rxdet !! 830 interrupts = <0 63 0x4>;
826 usb3-lpm-capab !! 831 dr_mode = "host";
827 snps,incr-burs !! 832 snps,quirk-frame-length-adjustment = <0x20>;
828 status = "disa !! 833 snps,dis_rxdet_inp3_quirk;
829 }; !! 834 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
830 !! 835 status = "disabled";
831 usb2: usb@3100000 { !! 836 };
832 compatible = " !! 837
833 reg = <0x0 0x3 !! 838 sata: sata@3200000 {
834 interrupts = < !! 839 compatible = "fsl,ls1043a-ahci";
835 dr_mode = "hos !! 840 reg = <0x0 0x3200000 0x0 0x10000>,
836 snps,quirk-fra !! 841 <0x0 0x20140520 0x0 0x4>;
837 snps,dis_rxdet !! 842 reg-names = "ahci", "sata-ecc";
838 usb3-lpm-capab !! 843 interrupts = <0 69 0x4>;
839 snps,incr-burs !! 844 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
840 status = "disa !! 845 QORIQ_CLK_PLL_DIV(1)>;
841 }; !! 846 dma-coherent;
842 <<
843 sata: sata@3200000 { <<
844 compatible = " <<
845 reg = <0x0 0x3 <<
846 <0x0 0 <<
847 reg-names = "a <<
848 interrupts = < <<
849 clocks = <&clo <<
850 <<
851 dma-coherent; <<
852 }; <<
853 }; 847 };
854 848
855 msi1: msi-controller1@1571000 849 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 850 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 851 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 852 msi-controller;
859 interrupts = <GIC_SPI !! 853 interrupts = <0 116 0x4>;
860 }; 854 };
861 855
862 msi2: msi-controller2@1572000 856 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 857 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 858 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 859 msi-controller;
866 interrupts = <GIC_SPI !! 860 interrupts = <0 126 0x4>;
867 }; 861 };
868 862
869 msi3: msi-controller3@1573000 863 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 864 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 865 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 866 msi-controller;
873 interrupts = <GIC_SPI !! 867 interrupts = <0 160 0x4>;
874 }; 868 };
875 869
876 pcie1: pcie@3400000 { 870 pcie1: pcie@3400000 {
877 compatible = "fsl,ls10 871 compatible = "fsl,ls1043a-pcie";
878 reg = <0x00 0x03400000 !! 872 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
879 <0x40 0x00000000 !! 873 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 874 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 875 interrupts = <0 118 0x4>, /* controller interrupt */
882 <GIC_SPI !! 876 <0 117 0x4>; /* PME interrupt */
883 interrupt-names = "pme !! 877 interrupt-names = "intr", "pme";
884 #address-cells = <3>; 878 #address-cells = <3>;
885 #size-cells = <2>; 879 #size-cells = <2>;
886 device_type = "pci"; 880 device_type = "pci";
>> 881 dma-coherent;
887 num-viewport = <6>; 882 num-viewport = <6>;
888 bus-range = <0x0 0xff> 883 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 884 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 885 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 886 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 887 #interrupt-cells = <1>;
893 interrupt-map-mask = < 888 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 889 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 890 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 891 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 892 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg <<
899 big-endian; <<
900 status = "disabled"; 893 status = "disabled";
901 }; 894 };
902 895
903 pcie2: pcie@3500000 { 896 pcie2: pcie@3500000 {
904 compatible = "fsl,ls10 897 compatible = "fsl,ls1043a-pcie";
905 reg = <0x00 0x03500000 !! 898 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
906 <0x48 0x00000000 !! 899 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 900 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 901 interrupts = <0 128 0x4>,
909 <GIC_SPI !! 902 <0 127 0x4>;
910 interrupt-names = "pme !! 903 interrupt-names = "intr", "pme";
911 #address-cells = <3>; 904 #address-cells = <3>;
912 #size-cells = <2>; 905 #size-cells = <2>;
913 device_type = "pci"; 906 device_type = "pci";
>> 907 dma-coherent;
914 num-viewport = <6>; 908 num-viewport = <6>;
915 bus-range = <0x0 0xff> 909 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 910 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 911 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 912 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 913 #interrupt-cells = <1>;
920 interrupt-map-mask = < 914 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 915 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 916 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 917 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 918 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg <<
926 big-endian; <<
927 status = "disabled"; 919 status = "disabled";
928 }; 920 };
929 921
930 pcie3: pcie@3600000 { 922 pcie3: pcie@3600000 {
931 compatible = "fsl,ls10 923 compatible = "fsl,ls1043a-pcie";
932 reg = <0x00 0x03600000 !! 924 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
933 <0x50 0x00000000 !! 925 0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 926 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 927 interrupts = <0 162 0x4>,
936 <GIC_SPI !! 928 <0 161 0x4>;
937 interrupt-names = "pme !! 929 interrupt-names = "intr", "pme";
938 #address-cells = <3>; 930 #address-cells = <3>;
939 #size-cells = <2>; 931 #size-cells = <2>;
940 device_type = "pci"; 932 device_type = "pci";
>> 933 dma-coherent;
941 num-viewport = <6>; 934 num-viewport = <6>;
942 bus-range = <0x0 0xff> 935 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 936 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 937 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 938 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 939 #interrupt-cells = <1>;
947 interrupt-map-mask = < 940 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 941 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 942 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 943 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 944 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg <<
953 big-endian; <<
954 status = "disabled"; 945 status = "disabled";
955 }; 946 };
956 947
957 qdma: dma-controller@8380000 { 948 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls10 !! 949 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
959 reg = <0x0 0x8380000 0 950 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
960 <0x0 0x8390000 0 951 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
961 <0x0 0x83a0000 0 952 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
962 interrupts = <GIC_SPI 953 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 954 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 955 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 956 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 957 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "qdm 958 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", 959 "qdma-queue1", "qdma-queue2", "qdma-queue3";
969 #dma-cells = <1>; <<
970 dma-channels = <8>; 960 dma-channels = <8>;
971 block-number = <1>; 961 block-number = <1>;
972 block-offset = <0x1000 962 block-offset = <0x10000>;
973 fsl,dma-queues = <2>; 963 fsl,dma-queues = <2>;
974 status-sizes = <64>; 964 status-sizes = <64>;
975 queue-sizes = <64 64>; 965 queue-sizes = <64 64>;
976 big-endian; 966 big-endian;
977 }; 967 };
978 968
979 rcpm: wakeup-controller@1ee214 !! 969 rcpm: power-controller@1ee2140 {
980 compatible = "fsl,ls10 970 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
981 reg = <0x0 0x1ee2140 0 971 reg = <0x0 0x1ee2140 0x0 0x4>;
982 #fsl,rcpm-wakeup-cells 972 #fsl,rcpm-wakeup-cells = <1>;
983 }; 973 };
984 974
985 ftm_alarm0: rtc@29d0000 { !! 975 ftm_alarm0: timer@29d0000 {
986 compatible = "fsl,ls10 976 compatible = "fsl,ls1043a-ftm-alarm";
987 reg = <0x0 0x29d0000 0 977 reg = <0x0 0x29d0000 0x0 0x10000>;
988 fsl,rcpm-wakeup = <&rc 978 fsl,rcpm-wakeup = <&rcpm 0x20000>;
989 interrupts = <GIC_SPI 979 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
990 big-endian; 980 big-endian;
991 }; 981 };
992 }; 982 };
993 983
994 firmware { 984 firmware {
995 optee { 985 optee {
996 compatible = "linaro,o 986 compatible = "linaro,optee-tz";
997 method = "smc"; 987 method = "smc";
998 }; 988 };
999 }; 989 };
1000 990
1001 }; 991 };
1002 992
1003 #include "qoriq-qman-portals.dtsi" 993 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 994 #include "qoriq-bman-portals.dtsi"
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