1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 * 4 *
5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP 6 * Copyright 2018, 2020 NXP
7 * 7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */ 9 */
10 10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 15
16 / { 16 / {
17 compatible = "fsl,ls1043a"; 17 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
23 crypto = &crypto; 23 crypto = &crypto;
24 fman0 = &fman0; 24 fman0 = &fman0;
25 ethernet0 = &enet0; 25 ethernet0 = &enet0;
26 ethernet1 = &enet1; 26 ethernet1 = &enet1;
27 ethernet2 = &enet2; 27 ethernet2 = &enet2;
28 ethernet3 = &enet3; 28 ethernet3 = &enet3;
29 ethernet4 = &enet4; 29 ethernet4 = &enet4;
30 ethernet5 = &enet5; 30 ethernet5 = &enet5;
31 ethernet6 = &enet6; 31 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; 32 rtc1 = &ftm_alarm0;
33 }; 33 };
34 34
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 38
39 /* 39 /*
40 * We expect the enable-method 40 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 41 * is dependent on the SoC FW, which will fill this in.
42 * 42 *
43 * Currently supported enable- 43 * Currently supported enable-method is psci v0.2
44 */ 44 */
45 cpu0: cpu@0 { 45 cpu0: cpu@0 {
46 device_type = "cpu"; 46 device_type = "cpu";
47 compatible = "arm,cort 47 compatible = "arm,cortex-a53";
48 reg = <0x0>; 48 reg = <0x0>;
49 clocks = <&clockgen QO 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
50 next-level-cache = <&l 50 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>; 52 #cooling-cells = <2>;
53 }; 53 };
54 54
55 cpu1: cpu@1 { 55 cpu1: cpu@1 {
56 device_type = "cpu"; 56 device_type = "cpu";
57 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
58 reg = <0x1>; 58 reg = <0x1>;
59 clocks = <&clockgen QO 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 next-level-cache = <&l 60 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>; 62 #cooling-cells = <2>;
63 }; 63 };
64 64
65 cpu2: cpu@2 { 65 cpu2: cpu@2 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
68 reg = <0x2>; 68 reg = <0x2>;
69 clocks = <&clockgen QO 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
70 next-level-cache = <&l 70 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP 71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 72 #cooling-cells = <2>;
73 }; 73 };
74 74
75 cpu3: cpu@3 { 75 cpu3: cpu@3 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 reg = <0x3>; 78 reg = <0x3>;
79 clocks = <&clockgen QO 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
80 next-level-cache = <&l 80 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP 81 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>; 82 #cooling-cells = <2>;
83 }; 83 };
84 84
85 l2: l2-cache { 85 l2: l2-cache {
86 compatible = "cache"; 86 compatible = "cache";
87 cache-level = <2>; 87 cache-level = <2>;
88 cache-unified; <<
89 }; 88 };
90 }; 89 };
91 90
92 idle-states { 91 idle-states {
93 /* 92 /*
94 * PSCI node is not added defa 93 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to u 94 * parts if it determines to use PSCI.
96 */ 95 */
97 entry-method = "psci"; 96 entry-method = "psci";
98 97
99 CPU_PH20: cpu-ph20 { 98 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle 99 compatible = "arm,idle-state";
101 idle-state-name = "PH2 100 idle-state-name = "PH20";
102 arm,psci-suspend-param 101 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <10 102 entry-latency-us = <1000>;
104 exit-latency-us = <100 103 exit-latency-us = <1000>;
105 min-residency-us = <30 104 min-residency-us = <3000>;
106 }; 105 };
107 }; 106 };
108 107
109 memory@80000000 { 108 memory@80000000 {
110 device_type = "memory"; 109 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 110 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 111 /* DRAM space 1, size: 2GiB DRAM */
113 }; 112 };
114 113
115 reserved-memory { 114 reserved-memory {
116 #address-cells = <2>; 115 #address-cells = <2>;
117 #size-cells = <2>; 116 #size-cells = <2>;
118 ranges; 117 ranges;
119 118
120 bman_fbpr: bman-fbpr { 119 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 120 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 121 size = <0 0x1000000>;
123 alignment = <0 0x10000 122 alignment = <0 0x1000000>;
124 no-map; 123 no-map;
125 }; 124 };
126 125
127 qman_fqd: qman-fqd { 126 qman_fqd: qman-fqd {
128 compatible = "shared-d 127 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 128 size = <0 0x400000>;
130 alignment = <0 0x40000 129 alignment = <0 0x400000>;
131 no-map; 130 no-map;
132 }; 131 };
133 132
134 qman_pfdr: qman-pfdr { 133 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 134 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 135 size = <0 0x2000000>;
137 alignment = <0 0x20000 136 alignment = <0 0x2000000>;
138 no-map; 137 no-map;
139 }; 138 };
140 }; 139 };
141 140
142 sysclk: sysclk { 141 sysclk: sysclk {
143 compatible = "fixed-clock"; 142 compatible = "fixed-clock";
144 #clock-cells = <0>; 143 #clock-cells = <0>;
145 clock-frequency = <100000000>; 144 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 145 clock-output-names = "sysclk";
147 }; 146 };
148 147
149 reboot { 148 reboot {
150 compatible = "syscon-reboot"; 149 compatible = "syscon-reboot";
151 regmap = <&dcfg>; 150 regmap = <&dcfg>;
152 offset = <0xb0>; 151 offset = <0xb0>;
153 mask = <0x02>; 152 mask = <0x02>;
154 }; 153 };
155 154
156 thermal-zones { 155 thermal-zones {
157 ddr-thermal { !! 156 ddr-controller {
158 polling-delay-passive 157 polling-delay-passive = <1000>;
159 polling-delay = <5000> 158 polling-delay = <5000>;
160 thermal-sensors = <&tm 159 thermal-sensors = <&tmu 0>;
161 160
162 trips { 161 trips {
163 ddr-ctrler-ale 162 ddr-ctrler-alert {
164 temper 163 temperature = <85000>;
165 hyster 164 hysteresis = <2000>;
166 type = 165 type = "passive";
167 }; 166 };
168 167
169 ddr-ctrler-cri 168 ddr-ctrler-crit {
170 temper 169 temperature = <95000>;
171 hyster 170 hysteresis = <2000>;
172 type = 171 type = "critical";
173 }; 172 };
174 }; 173 };
175 }; 174 };
176 175
177 serdes-thermal { !! 176 serdes {
178 polling-delay-passive 177 polling-delay-passive = <1000>;
179 polling-delay = <5000> 178 polling-delay = <5000>;
180 thermal-sensors = <&tm 179 thermal-sensors = <&tmu 1>;
181 180
182 trips { 181 trips {
183 serdes-alert { 182 serdes-alert {
184 temper 183 temperature = <85000>;
185 hyster 184 hysteresis = <2000>;
186 type = 185 type = "passive";
187 }; 186 };
188 187
189 serdes-crit { 188 serdes-crit {
190 temper 189 temperature = <95000>;
191 hyster 190 hysteresis = <2000>;
192 type = 191 type = "critical";
193 }; 192 };
194 }; 193 };
195 }; 194 };
196 195
197 fman-thermal { !! 196 fman {
198 polling-delay-passive 197 polling-delay-passive = <1000>;
199 polling-delay = <5000> 198 polling-delay = <5000>;
200 thermal-sensors = <&tm 199 thermal-sensors = <&tmu 2>;
201 200
202 trips { 201 trips {
203 fman-alert { 202 fman-alert {
204 temper 203 temperature = <85000>;
205 hyster 204 hysteresis = <2000>;
206 type = 205 type = "passive";
207 }; 206 };
208 207
209 fman-crit { 208 fman-crit {
210 temper 209 temperature = <95000>;
211 hyster 210 hysteresis = <2000>;
212 type = 211 type = "critical";
213 }; 212 };
214 }; 213 };
215 }; 214 };
216 215
217 cluster-thermal { !! 216 core-cluster {
218 polling-delay-passive 217 polling-delay-passive = <1000>;
219 polling-delay = <5000> 218 polling-delay = <5000>;
220 thermal-sensors = <&tm 219 thermal-sensors = <&tmu 3>;
221 220
222 trips { 221 trips {
223 core_cluster_a 222 core_cluster_alert: core-cluster-alert {
224 temper 223 temperature = <85000>;
225 hyster 224 hysteresis = <2000>;
226 type = 225 type = "passive";
227 }; 226 };
228 227
229 core_cluster_c 228 core_cluster_crit: core-cluster-crit {
230 temper 229 temperature = <95000>;
231 hyster 230 hysteresis = <2000>;
232 type = 231 type = "critical";
233 }; 232 };
234 }; 233 };
235 234
236 cooling-maps { 235 cooling-maps {
237 map0 { 236 map0 {
238 trip = 237 trip = <&core_cluster_alert>;
239 coolin 238 cooling-device =
240 239 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
241 240 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
242 241 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
243 242 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 }; 243 };
245 }; 244 };
246 }; 245 };
247 246
248 sec-thermal { !! 247 sec {
249 polling-delay-passive 248 polling-delay-passive = <1000>;
250 polling-delay = <5000> 249 polling-delay = <5000>;
251 thermal-sensors = <&tm 250 thermal-sensors = <&tmu 4>;
252 251
253 trips { 252 trips {
254 sec-alert { 253 sec-alert {
255 temper 254 temperature = <85000>;
256 hyster 255 hysteresis = <2000>;
257 type = 256 type = "passive";
258 }; 257 };
259 258
260 sec-crit { 259 sec-crit {
261 temper 260 temperature = <95000>;
262 hyster 261 hysteresis = <2000>;
263 type = 262 type = "critical";
264 }; 263 };
265 }; 264 };
266 }; 265 };
267 }; 266 };
268 267
269 timer { 268 timer {
270 compatible = "arm,armv8-timer" 269 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 270 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 271 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 272 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 273 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 274 fsl,erratum-a008585;
276 }; 275 };
277 276
278 pmu { 277 pmu {
279 compatible = "arm,cortex-a53-p !! 278 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 279 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 280 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 281 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 282 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 283 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 284 <&cpu1>,
286 <&cpu2>, 285 <&cpu2>,
287 <&cpu3>; 286 <&cpu3>;
288 }; 287 };
289 288
290 gic: interrupt-controller@1400000 { 289 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 290 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 291 #interrupt-cells = <3>;
293 interrupt-controller; 292 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 293 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 294 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 295 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 296 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 297 interrupts = <1 9 0xf08>;
299 }; 298 };
300 299
301 soc: soc { 300 soc: soc {
302 compatible = "simple-bus"; 301 compatible = "simple-bus";
303 #address-cells = <2>; 302 #address-cells = <2>;
304 #size-cells = <2>; 303 #size-cells = <2>;
305 ranges; 304 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 305 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
307 dma-coherent; 306 dma-coherent;
308 307
309 clockgen: clocking@1ee1000 { 308 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 309 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 310 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 311 #clock-cells = <2>;
313 clocks = <&sysclk>; 312 clocks = <&sysclk>;
314 }; 313 };
315 314
316 scfg: scfg@1570000 { 315 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 316 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 317 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 318 big-endian;
320 #address-cells = <1>; 319 #address-cells = <1>;
321 #size-cells = <1>; 320 #size-cells = <1>;
322 ranges = <0x0 0x0 0x15 321 ranges = <0x0 0x0 0x1570000 0x10000>;
323 322
324 extirq: interrupt-cont 323 extirq: interrupt-controller@1ac {
325 compatible = " 324 compatible = "fsl,ls1043a-extirq";
326 #interrupt-cel 325 #interrupt-cells = <2>;
327 #address-cells 326 #address-cells = <0>;
328 interrupt-cont 327 interrupt-controller;
329 reg = <0x1ac 4 328 reg = <0x1ac 4>;
330 interrupt-map 329 interrupt-map =
331 <0 0 & 330 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 & 331 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 & 332 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 & 333 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 & 334 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 & 335 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 & 336 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 & 337 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 & 338 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 & 339 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 340 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 341 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map- 342 interrupt-map-mask = <0xf 0x0>;
344 }; 343 };
345 }; 344 };
346 345
347 crypto: crypto@1700000 { 346 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 347 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 348 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 349 fsl,sec-era = <3>;
351 #address-cells = <1>; 350 #address-cells = <1>;
352 #size-cells = <1>; 351 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 352 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 353 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 354 interrupts = <0 75 0x4>;
356 dma-coherent; 355 dma-coherent;
357 356
358 sec_jr0: jr@10000 { 357 sec_jr0: jr@10000 {
359 compatible = " 358 compatible = "fsl,sec-v5.4-job-ring",
360 " 359 "fsl,sec-v5.0-job-ring",
361 " 360 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 361 reg = <0x10000 0x10000>;
363 interrupts = < !! 362 interrupts = <0 71 0x4>;
364 }; 363 };
365 364
366 sec_jr1: jr@20000 { 365 sec_jr1: jr@20000 {
367 compatible = " 366 compatible = "fsl,sec-v5.4-job-ring",
368 " 367 "fsl,sec-v5.0-job-ring",
369 " 368 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 369 reg = <0x20000 0x10000>;
371 interrupts = < !! 370 interrupts = <0 72 0x4>;
372 }; 371 };
373 372
374 sec_jr2: jr@30000 { 373 sec_jr2: jr@30000 {
375 compatible = " 374 compatible = "fsl,sec-v5.4-job-ring",
376 " 375 "fsl,sec-v5.0-job-ring",
377 " 376 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 377 reg = <0x30000 0x10000>;
379 interrupts = < !! 378 interrupts = <0 73 0x4>;
380 }; 379 };
381 380
382 sec_jr3: jr@40000 { 381 sec_jr3: jr@40000 {
383 compatible = " 382 compatible = "fsl,sec-v5.4-job-ring",
384 " 383 "fsl,sec-v5.0-job-ring",
385 " 384 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 385 reg = <0x40000 0x10000>;
387 interrupts = < !! 386 interrupts = <0 74 0x4>;
388 }; 387 };
389 }; 388 };
390 389
391 sfp: efuse@1e80000 { 390 sfp: efuse@1e80000 {
392 compatible = "fsl,ls10 391 compatible = "fsl,ls1021a-sfp";
393 reg = <0x0 0x1e80000 0 392 reg = <0x0 0x1e80000 0x0 0x10000>;
394 clocks = <&clockgen QO 393 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
395 QO 394 QORIQ_CLK_PLL_DIV(4)>;
396 clock-names = "sfp"; 395 clock-names = "sfp";
397 }; 396 };
398 397
399 dcfg: dcfg@1ee0000 { 398 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 399 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 400 reg = <0x0 0x1ee0000 0x0 0x1000>;
402 big-endian; 401 big-endian;
403 }; 402 };
404 403
405 ifc: memory-controller@1530000 404 ifc: memory-controller@1530000 {
406 compatible = "fsl,ifc" 405 compatible = "fsl,ifc";
407 reg = <0x0 0x1530000 0 406 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 407 interrupts = <0 43 0x4>;
409 }; 408 };
410 409
411 qspi: spi@1550000 { 410 qspi: spi@1550000 {
412 compatible = "fsl,ls10 411 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 412 #address-cells = <1>;
414 #size-cells = <0>; 413 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 414 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 415 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 416 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 417 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 418 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO 419 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QO 420 QORIQ_CLK_PLL_DIV(1)>,
422 <&clockgen QO 421 <&clockgen QORIQ_CLK_PLATFORM_PLL
423 QO 422 QORIQ_CLK_PLL_DIV(1)>;
424 status = "disabled"; 423 status = "disabled";
425 }; 424 };
426 425
427 esdhc: mmc@1560000 { !! 426 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 427 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 428 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 429 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 430 clock-frequency = <0>;
432 voltage-ranges = <1800 431 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 432 sdhci,auto-cmd12;
>> 433 big-endian;
434 bus-width = <4>; 434 bus-width = <4>;
435 }; 435 };
436 436
437 ddr: memory-controller@1080000 437 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 438 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 439 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 440 interrupts = <0 144 0x4>;
>> 441 big-endian;
441 }; 442 };
442 443
443 tmu: tmu@1f00000 { 444 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 445 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 446 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 447 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 448 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration = !! 449 fsl,tmu-calibration = <0x00000000 0x00000023
449 <0x000 !! 450 0x00000001 0x0000002a
450 <0x000 !! 451 0x00000002 0x00000031
451 <0x000 !! 452 0x00000003 0x00000037
452 <0x000 !! 453 0x00000004 0x0000003e
453 <0x000 !! 454 0x00000005 0x00000044
454 <0x000 !! 455 0x00000006 0x0000004b
455 <0x000 !! 456 0x00000007 0x00000051
456 <0x000 !! 457 0x00000008 0x00000058
457 <0x000 !! 458 0x00000009 0x0000005e
458 <0x000 !! 459 0x0000000a 0x00000065
459 <0x000 !! 460 0x0000000b 0x0000006b
460 <0x000 !! 461
461 !! 462 0x00010000 0x00000023
462 <0x000 !! 463 0x00010001 0x0000002b
463 <0x000 !! 464 0x00010002 0x00000033
464 <0x000 !! 465 0x00010003 0x0000003b
465 <0x000 !! 466 0x00010004 0x00000043
466 <0x000 !! 467 0x00010005 0x0000004b
467 <0x000 !! 468 0x00010006 0x00000054
468 <0x000 !! 469 0x00010007 0x0000005c
469 <0x000 !! 470 0x00010008 0x00000064
470 <0x000 !! 471 0x00010009 0x0000006c
471 <0x000 !! 472
472 !! 473 0x00020000 0x00000021
473 <0x000 !! 474 0x00020001 0x0000002c
474 <0x000 !! 475 0x00020002 0x00000036
475 <0x000 !! 476 0x00020003 0x00000040
476 <0x000 !! 477 0x00020004 0x0000004b
477 <0x000 !! 478 0x00020005 0x00000055
478 <0x000 !! 479 0x00020006 0x0000005f
479 <0x000 !! 480
480 !! 481 0x00030000 0x00000013
481 <0x000 !! 482 0x00030001 0x0000001d
482 <0x000 !! 483 0x00030002 0x00000028
483 <0x000 !! 484 0x00030003 0x00000032
484 <0x000 !! 485 0x00030004 0x0000003d
485 <0x000 !! 486 0x00030005 0x00000047
486 <0x000 !! 487 0x00030006 0x00000052
487 <0x000 !! 488 0x00030007 0x0000005c>;
488 <0x000 <<
489 #thermal-sensor-cells 489 #thermal-sensor-cells = <1>;
490 }; 490 };
491 491
492 qman: qman@1880000 { 492 qman: qman@1880000 {
493 compatible = "fsl,qman 493 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 494 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 496 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 497 };
498 498
499 bman: bman@1890000 { 499 bman: bman@1890000 {
500 compatible = "fsl,bman 500 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 501 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 502 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 503 memory-region = <&bman_fbpr>;
504 }; 504 };
505 505
506 bportals: bman-portals-bus@508 !! 506 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 507 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 508 };
509 509
510 qportals: qman-portals-bus@500 !! 510 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 511 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 512 };
513 513
514 dspi0: spi@2100000 { 514 dspi0: spi@2100000 {
515 compatible = "fsl,ls10 515 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 516 #address-cells = <1>;
517 #size-cells = <0>; 517 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 518 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 519 interrupts = <0 64 0x4>;
>> 520 clock-names = "dspi";
>> 521 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
>> 522 QORIQ_CLK_PLL_DIV(1)>;
>> 523 spi-num-chipselects = <5>;
>> 524 big-endian;
>> 525 status = "disabled";
>> 526 };
>> 527
>> 528 dspi1: spi@2110000 {
>> 529 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
>> 530 #address-cells = <1>;
>> 531 #size-cells = <0>;
>> 532 reg = <0x0 0x2110000 0x0 0x10000>;
>> 533 interrupts = <0 65 0x4>;
520 clock-names = "dspi"; 534 clock-names = "dspi";
521 clocks = <&clockgen QO 535 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
522 QO 536 QORIQ_CLK_PLL_DIV(1)>;
523 spi-num-chipselects = 537 spi-num-chipselects = <5>;
524 big-endian; 538 big-endian;
525 status = "disabled"; 539 status = "disabled";
526 }; 540 };
527 541
528 i2c0: i2c@2180000 { 542 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 543 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
530 #address-cells = <1>; 544 #address-cells = <1>;
531 #size-cells = <0>; 545 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 546 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 547 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 548 clock-names = "i2c";
535 clocks = <&clockgen QO 549 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
536 QO 550 QORIQ_CLK_PLL_DIV(1)>;
537 dmas = <&edma0 1 38>, 551 dmas = <&edma0 1 38>,
538 <&edma0 1 39>; 552 <&edma0 1 39>;
539 dma-names = "rx", "tx" 553 dma-names = "rx", "tx";
540 status = "disabled"; 554 status = "disabled";
541 }; 555 };
542 556
543 i2c1: i2c@2190000 { 557 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 558 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
545 #address-cells = <1>; 559 #address-cells = <1>;
546 #size-cells = <0>; 560 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 561 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 562 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 563 clock-names = "i2c";
550 clocks = <&clockgen QO 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
551 QO 565 QORIQ_CLK_PLL_DIV(1)>;
552 scl-gpios = <&gpio4 2 566 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
553 status = "disabled"; 567 status = "disabled";
554 }; 568 };
555 569
556 i2c2: i2c@21a0000 { 570 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 571 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
558 #address-cells = <1>; 572 #address-cells = <1>;
559 #size-cells = <0>; 573 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 574 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 575 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 576 clock-names = "i2c";
563 clocks = <&clockgen QO 577 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564 QO 578 QORIQ_CLK_PLL_DIV(1)>;
565 scl-gpios = <&gpio4 10 579 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
566 status = "disabled"; 580 status = "disabled";
567 }; 581 };
568 582
569 i2c3: i2c@21b0000 { 583 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 584 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
571 #address-cells = <1>; 585 #address-cells = <1>;
572 #size-cells = <0>; 586 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 587 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 588 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 589 clock-names = "i2c";
576 clocks = <&clockgen QO 590 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
577 QO 591 QORIQ_CLK_PLL_DIV(1)>;
578 scl-gpios = <&gpio4 12 592 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 status = "disabled"; 593 status = "disabled";
580 }; 594 };
581 595
582 duart0: serial@21c0500 { 596 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 597 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 598 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 599 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO 600 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
587 QO 601 QORIQ_CLK_PLL_DIV(1)>;
588 }; 602 };
589 603
590 duart1: serial@21c0600 { 604 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 605 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 606 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 607 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO 608 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
595 QO 609 QORIQ_CLK_PLL_DIV(1)>;
596 }; 610 };
597 611
598 duart2: serial@21d0500 { 612 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 613 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 614 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 615 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO 616 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
603 QO 617 QORIQ_CLK_PLL_DIV(1)>;
604 }; 618 };
605 619
606 duart3: serial@21d0600 { 620 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 621 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 622 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 623 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO 624 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
611 QO 625 QORIQ_CLK_PLL_DIV(1)>;
612 }; 626 };
613 627
614 gpio1: gpio@2300000 { 628 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 629 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 630 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 631 interrupts = <0 66 0x4>;
618 gpio-controller; 632 gpio-controller;
619 #gpio-cells = <2>; 633 #gpio-cells = <2>;
620 interrupt-controller; 634 interrupt-controller;
621 #interrupt-cells = <2> 635 #interrupt-cells = <2>;
622 }; 636 };
623 637
624 gpio2: gpio@2310000 { 638 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 639 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 640 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 641 interrupts = <0 67 0x4>;
628 gpio-controller; 642 gpio-controller;
629 #gpio-cells = <2>; 643 #gpio-cells = <2>;
630 interrupt-controller; 644 interrupt-controller;
631 #interrupt-cells = <2> 645 #interrupt-cells = <2>;
632 }; 646 };
633 647
634 gpio3: gpio@2320000 { 648 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 649 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 650 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 651 interrupts = <0 68 0x4>;
638 gpio-controller; 652 gpio-controller;
639 #gpio-cells = <2>; 653 #gpio-cells = <2>;
640 interrupt-controller; 654 interrupt-controller;
641 #interrupt-cells = <2> 655 #interrupt-cells = <2>;
642 }; 656 };
643 657
644 gpio4: gpio@2330000 { 658 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 659 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 660 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 661 interrupts = <0 134 0x4>;
648 gpio-controller; 662 gpio-controller;
649 #gpio-cells = <2>; 663 #gpio-cells = <2>;
650 interrupt-controller; 664 interrupt-controller;
651 #interrupt-cells = <2> 665 #interrupt-cells = <2>;
652 }; 666 };
653 667
654 uqe: uqe-bus@2400000 { !! 668 uqe: uqe@2400000 {
655 #address-cells = <1>; 669 #address-cells = <1>;
656 #size-cells = <1>; 670 #size-cells = <1>;
657 compatible = "fsl,qe", 671 compatible = "fsl,qe", "simple-bus";
658 ranges = <0x0 0x0 0x24 672 ranges = <0x0 0x0 0x2400000 0x40000>;
659 reg = <0x0 0x2400000 0 673 reg = <0x0 0x2400000 0x0 0x480>;
660 brg-frequency = <10000 674 brg-frequency = <100000000>;
661 bus-frequency = <20000 675 bus-frequency = <200000000>;
662 fsl,qe-num-riscs = <1> 676 fsl,qe-num-riscs = <1>;
663 fsl,qe-num-snums = <28 677 fsl,qe-num-snums = <28>;
664 678
665 qeic: qeic@80 { 679 qeic: qeic@80 {
666 compatible = " 680 compatible = "fsl,qe-ic";
667 reg = <0x80 0x 681 reg = <0x80 0x80>;
>> 682 #address-cells = <0>;
668 interrupt-cont 683 interrupt-controller;
669 #interrupt-cel 684 #interrupt-cells = <1>;
670 interrupts = < 685 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
671 < 686 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
672 }; 687 };
673 688
674 si1: si@700 { 689 si1: si@700 {
>> 690 #address-cells = <1>;
>> 691 #size-cells = <0>;
675 compatible = " 692 compatible = "fsl,ls1043-qe-si",
676 693 "fsl,t1040-qe-si";
677 reg = <0x700 0 694 reg = <0x700 0x80>;
678 }; 695 };
679 696
680 siram1: siram@1000 { 697 siram1: siram@1000 {
>> 698 #address-cells = <1>;
>> 699 #size-cells = <1>;
681 compatible = " 700 compatible = "fsl,ls1043-qe-siram",
682 701 "fsl,t1040-qe-siram";
683 reg = <0x1000 702 reg = <0x1000 0x800>;
684 }; 703 };
685 704
686 ucc@2000 { 705 ucc@2000 {
687 cell-index = < 706 cell-index = <1>;
688 reg = <0x2000 707 reg = <0x2000 0x200>;
689 interrupts = < 708 interrupts = <32>;
690 interrupt-pare 709 interrupt-parent = <&qeic>;
691 }; 710 };
692 711
693 ucc@2200 { 712 ucc@2200 {
694 cell-index = < 713 cell-index = <3>;
695 reg = <0x2200 714 reg = <0x2200 0x200>;
696 interrupts = < 715 interrupts = <34>;
697 interrupt-pare 716 interrupt-parent = <&qeic>;
698 }; 717 };
699 718
700 muram@10000 { 719 muram@10000 {
701 #address-cells 720 #address-cells = <1>;
702 #size-cells = 721 #size-cells = <1>;
703 compatible = " 722 compatible = "fsl,qe-muram", "fsl,cpm-muram";
704 ranges = <0x0 723 ranges = <0x0 0x10000 0x6000>;
705 724
706 data-only@0 { 725 data-only@0 {
707 compat 726 compatible = "fsl,qe-muram-data",
708 "fsl,c 727 "fsl,cpm-muram-data";
709 reg = 728 reg = <0x0 0x6000>;
710 }; 729 };
711 }; 730 };
712 }; 731 };
713 732
714 lpuart0: serial@2950000 { 733 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 734 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 735 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 736 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO 737 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
719 clock-names = "ipg"; 738 clock-names = "ipg";
720 status = "disabled"; 739 status = "disabled";
721 }; 740 };
722 741
723 lpuart1: serial@2960000 { 742 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 743 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 744 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 745 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO 746 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
728 QO 747 QORIQ_CLK_PLL_DIV(1)>;
729 clock-names = "ipg"; 748 clock-names = "ipg";
730 status = "disabled"; 749 status = "disabled";
731 }; 750 };
732 751
733 lpuart2: serial@2970000 { 752 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 753 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 754 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 755 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO 756 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
738 QO 757 QORIQ_CLK_PLL_DIV(1)>;
739 clock-names = "ipg"; 758 clock-names = "ipg";
740 status = "disabled"; 759 status = "disabled";
741 }; 760 };
742 761
743 lpuart3: serial@2980000 { 762 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 763 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 764 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 765 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO 766 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
748 QO 767 QORIQ_CLK_PLL_DIV(1)>;
749 clock-names = "ipg"; 768 clock-names = "ipg";
750 status = "disabled"; 769 status = "disabled";
751 }; 770 };
752 771
753 lpuart4: serial@2990000 { 772 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 773 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 774 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 775 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO 776 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
758 QO 777 QORIQ_CLK_PLL_DIV(1)>;
759 clock-names = "ipg"; 778 clock-names = "ipg";
760 status = "disabled"; 779 status = "disabled";
761 }; 780 };
762 781
763 lpuart5: serial@29a0000 { 782 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 783 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 784 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 785 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO 786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
768 QO 787 QORIQ_CLK_PLL_DIV(1)>;
769 clock-names = "ipg"; 788 clock-names = "ipg";
770 status = "disabled"; 789 status = "disabled";
771 }; 790 };
772 791
773 wdog0: watchdog@2ad0000 { 792 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls10 793 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 794 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 795 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO 796 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
778 QO 797 QORIQ_CLK_PLL_DIV(1)>;
>> 798 clock-names = "wdog";
779 big-endian; 799 big-endian;
780 }; 800 };
781 801
782 edma0: dma-controller@2c00000 802 edma0: dma-controller@2c00000 {
783 #dma-cells = <2>; 803 #dma-cells = <2>;
784 compatible = "fsl,vf61 804 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 805 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 806 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 807 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 808 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 809 <0 103 0x4>;
790 interrupt-names = "edm 810 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 811 dma-channels = <32>;
792 big-endian; 812 big-endian;
793 clock-names = "dmamux0 813 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO 814 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
795 QO 815 QORIQ_CLK_PLL_DIV(1)>,
796 <&clockgen QO 816 <&clockgen QORIQ_CLK_PLATFORM_PLL
797 QO 817 QORIQ_CLK_PLL_DIV(1)>;
798 }; 818 };
799 819
800 aux_bus: bus { !! 820 aux_bus: aux_bus {
801 #address-cells = <2>; 821 #address-cells = <2>;
802 #size-cells = <2>; 822 #size-cells = <2>;
803 compatible = "simple-b 823 compatible = "simple-bus";
804 ranges; 824 ranges;
805 dma-ranges = <0x0 0x0 825 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
806 826
807 usb0: usb@2f00000 { 827 usb0: usb@2f00000 {
808 compatible = " 828 compatible = "snps,dwc3";
809 reg = <0x0 0x2 829 reg = <0x0 0x2f00000 0x0 0x10000>;
810 interrupts = < !! 830 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
811 dr_mode = "hos 831 dr_mode = "host";
812 snps,quirk-fra 832 snps,quirk-frame-length-adjustment = <0x20>;
813 snps,dis_rxdet 833 snps,dis_rxdet_inp3_quirk;
814 usb3-lpm-capab 834 usb3-lpm-capable;
815 snps,incr-burs 835 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
816 status = "disa 836 status = "disabled";
817 }; 837 };
818 838
819 usb1: usb@3000000 { 839 usb1: usb@3000000 {
820 compatible = " 840 compatible = "snps,dwc3";
821 reg = <0x0 0x3 841 reg = <0x0 0x3000000 0x0 0x10000>;
822 interrupts = < !! 842 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
823 dr_mode = "hos 843 dr_mode = "host";
824 snps,quirk-fra 844 snps,quirk-frame-length-adjustment = <0x20>;
825 snps,dis_rxdet 845 snps,dis_rxdet_inp3_quirk;
826 usb3-lpm-capab 846 usb3-lpm-capable;
827 snps,incr-burs 847 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
828 status = "disa 848 status = "disabled";
829 }; 849 };
830 850
831 usb2: usb@3100000 { 851 usb2: usb@3100000 {
832 compatible = " 852 compatible = "snps,dwc3";
833 reg = <0x0 0x3 853 reg = <0x0 0x3100000 0x0 0x10000>;
834 interrupts = < !! 854 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
835 dr_mode = "hos 855 dr_mode = "host";
836 snps,quirk-fra 856 snps,quirk-frame-length-adjustment = <0x20>;
837 snps,dis_rxdet 857 snps,dis_rxdet_inp3_quirk;
838 usb3-lpm-capab 858 usb3-lpm-capable;
839 snps,incr-burs 859 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
840 status = "disa 860 status = "disabled";
841 }; 861 };
842 862
843 sata: sata@3200000 { 863 sata: sata@3200000 {
844 compatible = " 864 compatible = "fsl,ls1043a-ahci";
845 reg = <0x0 0x3 865 reg = <0x0 0x3200000 0x0 0x10000>,
846 <0x0 0 866 <0x0 0x20140520 0x0 0x4>;
847 reg-names = "a 867 reg-names = "ahci", "sata-ecc";
848 interrupts = < !! 868 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clo 869 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
850 870 QORIQ_CLK_PLL_DIV(1)>;
851 dma-coherent; 871 dma-coherent;
852 }; 872 };
853 }; 873 };
854 874
855 msi1: msi-controller1@1571000 875 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 876 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 877 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 878 msi-controller;
859 interrupts = <GIC_SPI !! 879 interrupts = <0 116 0x4>;
860 }; 880 };
861 881
862 msi2: msi-controller2@1572000 882 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 883 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 884 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 885 msi-controller;
866 interrupts = <GIC_SPI !! 886 interrupts = <0 126 0x4>;
867 }; 887 };
868 888
869 msi3: msi-controller3@1573000 889 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 890 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 891 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 892 msi-controller;
873 interrupts = <GIC_SPI !! 893 interrupts = <0 160 0x4>;
874 }; 894 };
875 895
876 pcie1: pcie@3400000 { 896 pcie1: pcie@3400000 {
877 compatible = "fsl,ls10 897 compatible = "fsl,ls1043a-pcie";
878 reg = <0x00 0x03400000 898 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
879 <0x40 0x00000000 899 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 900 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 901 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI !! 902 <0 118 IRQ_TYPE_LEVEL_HIGH>;
883 interrupt-names = "pme 903 interrupt-names = "pme", "aer";
884 #address-cells = <3>; 904 #address-cells = <3>;
885 #size-cells = <2>; 905 #size-cells = <2>;
886 device_type = "pci"; 906 device_type = "pci";
887 num-viewport = <6>; 907 num-viewport = <6>;
888 bus-range = <0x0 0xff> 908 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 909 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 910 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 911 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 912 #interrupt-cells = <1>;
893 interrupt-map-mask = < 913 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 914 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 915 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 916 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 917 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg 918 fsl,pcie-scfg = <&scfg 0>;
899 big-endian; 919 big-endian;
900 status = "disabled"; 920 status = "disabled";
901 }; 921 };
902 922
903 pcie2: pcie@3500000 { 923 pcie2: pcie@3500000 {
904 compatible = "fsl,ls10 924 compatible = "fsl,ls1043a-pcie";
905 reg = <0x00 0x03500000 925 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
906 <0x48 0x00000000 926 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 927 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 928 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI !! 929 <0 128 IRQ_TYPE_LEVEL_HIGH>;
910 interrupt-names = "pme 930 interrupt-names = "pme", "aer";
911 #address-cells = <3>; 931 #address-cells = <3>;
912 #size-cells = <2>; 932 #size-cells = <2>;
913 device_type = "pci"; 933 device_type = "pci";
914 num-viewport = <6>; 934 num-viewport = <6>;
915 bus-range = <0x0 0xff> 935 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 936 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 937 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 938 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 939 #interrupt-cells = <1>;
920 interrupt-map-mask = < 940 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 941 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 942 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 943 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 944 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg 945 fsl,pcie-scfg = <&scfg 1>;
926 big-endian; 946 big-endian;
927 status = "disabled"; 947 status = "disabled";
928 }; 948 };
929 949
930 pcie3: pcie@3600000 { 950 pcie3: pcie@3600000 {
931 compatible = "fsl,ls10 951 compatible = "fsl,ls1043a-pcie";
932 reg = <0x00 0x03600000 952 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
933 <0x50 0x00000000 953 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 954 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 955 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI !! 956 <0 162 IRQ_TYPE_LEVEL_HIGH>;
937 interrupt-names = "pme 957 interrupt-names = "pme", "aer";
938 #address-cells = <3>; 958 #address-cells = <3>;
939 #size-cells = <2>; 959 #size-cells = <2>;
940 device_type = "pci"; 960 device_type = "pci";
941 num-viewport = <6>; 961 num-viewport = <6>;
942 bus-range = <0x0 0xff> 962 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 963 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 964 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 965 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 966 #interrupt-cells = <1>;
947 interrupt-map-mask = < 967 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 968 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 969 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 970 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 971 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg 972 fsl,pcie-scfg = <&scfg 2>;
953 big-endian; 973 big-endian;
954 status = "disabled"; 974 status = "disabled";
955 }; 975 };
956 976
957 qdma: dma-controller@8380000 { 977 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls10 !! 978 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
959 reg = <0x0 0x8380000 0 979 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
960 <0x0 0x8390000 0 980 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
961 <0x0 0x83a0000 0 981 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
962 interrupts = <GIC_SPI 982 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 983 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 984 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 985 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 986 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "qdm 987 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", 988 "qdma-queue1", "qdma-queue2", "qdma-queue3";
969 #dma-cells = <1>; <<
970 dma-channels = <8>; 989 dma-channels = <8>;
971 block-number = <1>; 990 block-number = <1>;
972 block-offset = <0x1000 991 block-offset = <0x10000>;
973 fsl,dma-queues = <2>; 992 fsl,dma-queues = <2>;
974 status-sizes = <64>; 993 status-sizes = <64>;
975 queue-sizes = <64 64>; 994 queue-sizes = <64 64>;
976 big-endian; 995 big-endian;
977 }; 996 };
978 997
979 rcpm: wakeup-controller@1ee214 !! 998 rcpm: power-controller@1ee2140 {
980 compatible = "fsl,ls10 999 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
981 reg = <0x0 0x1ee2140 0 1000 reg = <0x0 0x1ee2140 0x0 0x4>;
982 #fsl,rcpm-wakeup-cells 1001 #fsl,rcpm-wakeup-cells = <1>;
983 }; 1002 };
984 1003
985 ftm_alarm0: rtc@29d0000 { !! 1004 ftm_alarm0: timer@29d0000 {
986 compatible = "fsl,ls10 1005 compatible = "fsl,ls1043a-ftm-alarm";
987 reg = <0x0 0x29d0000 0 1006 reg = <0x0 0x29d0000 0x0 0x10000>;
988 fsl,rcpm-wakeup = <&rc 1007 fsl,rcpm-wakeup = <&rcpm 0x20000>;
989 interrupts = <GIC_SPI 1008 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
990 big-endian; 1009 big-endian;
991 }; 1010 };
992 }; 1011 };
993 1012
994 firmware { 1013 firmware {
995 optee { 1014 optee {
996 compatible = "linaro,o 1015 compatible = "linaro,optee-tz";
997 method = "smc"; 1016 method = "smc";
998 }; 1017 };
999 }; 1018 };
1000 1019
1001 }; 1020 };
1002 1021
1003 #include "qoriq-qman-portals.dtsi" 1022 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 1023 #include "qoriq-bman-portals.dtsi"
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