1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1043A family SoC.
4 * 4 *
5 * Copyright 2014-2015 Freescale Semiconductor 5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018, 2020 NXP 6 * Copyright 2018, 2020 NXP
7 * 7 *
8 * Mingkai Hu <Mingkai.hu@freescale.com> 8 * Mingkai Hu <Mingkai.hu@freescale.com>
9 */ 9 */
10 10
11 #include <dt-bindings/clock/fsl,qoriq-clockgen 11 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 #include <dt-bindings/interrupt-controller/arm 13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/gpio/gpio.h> 14 #include <dt-bindings/gpio/gpio.h>
15 15
16 / { 16 / {
17 compatible = "fsl,ls1043a"; 17 compatible = "fsl,ls1043a";
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
23 crypto = &crypto; 23 crypto = &crypto;
24 fman0 = &fman0; 24 fman0 = &fman0;
25 ethernet0 = &enet0; 25 ethernet0 = &enet0;
26 ethernet1 = &enet1; 26 ethernet1 = &enet1;
27 ethernet2 = &enet2; 27 ethernet2 = &enet2;
28 ethernet3 = &enet3; 28 ethernet3 = &enet3;
29 ethernet4 = &enet4; 29 ethernet4 = &enet4;
30 ethernet5 = &enet5; 30 ethernet5 = &enet5;
31 ethernet6 = &enet6; 31 ethernet6 = &enet6;
32 rtc1 = &ftm_alarm0; 32 rtc1 = &ftm_alarm0;
33 }; 33 };
34 34
35 cpus { 35 cpus {
36 #address-cells = <1>; 36 #address-cells = <1>;
37 #size-cells = <0>; 37 #size-cells = <0>;
38 38
39 /* 39 /*
40 * We expect the enable-method 40 * We expect the enable-method for cpu's to be "psci", but this
41 * is dependent on the SoC FW, 41 * is dependent on the SoC FW, which will fill this in.
42 * 42 *
43 * Currently supported enable- 43 * Currently supported enable-method is psci v0.2
44 */ 44 */
45 cpu0: cpu@0 { 45 cpu0: cpu@0 {
46 device_type = "cpu"; 46 device_type = "cpu";
47 compatible = "arm,cort 47 compatible = "arm,cortex-a53";
48 reg = <0x0>; 48 reg = <0x0>;
49 clocks = <&clockgen QO 49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
50 next-level-cache = <&l 50 next-level-cache = <&l2>;
51 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_PH20>;
52 #cooling-cells = <2>; 52 #cooling-cells = <2>;
53 }; 53 };
54 54
55 cpu1: cpu@1 { 55 cpu1: cpu@1 {
56 device_type = "cpu"; 56 device_type = "cpu";
57 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
58 reg = <0x1>; 58 reg = <0x1>;
59 clocks = <&clockgen QO 59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 next-level-cache = <&l 60 next-level-cache = <&l2>;
61 cpu-idle-states = <&CP 61 cpu-idle-states = <&CPU_PH20>;
62 #cooling-cells = <2>; 62 #cooling-cells = <2>;
63 }; 63 };
64 64
65 cpu2: cpu@2 { 65 cpu2: cpu@2 {
66 device_type = "cpu"; 66 device_type = "cpu";
67 compatible = "arm,cort 67 compatible = "arm,cortex-a53";
68 reg = <0x2>; 68 reg = <0x2>;
69 clocks = <&clockgen QO 69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
70 next-level-cache = <&l 70 next-level-cache = <&l2>;
71 cpu-idle-states = <&CP 71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 72 #cooling-cells = <2>;
73 }; 73 };
74 74
75 cpu3: cpu@3 { 75 cpu3: cpu@3 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 reg = <0x3>; 78 reg = <0x3>;
79 clocks = <&clockgen QO 79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
80 next-level-cache = <&l 80 next-level-cache = <&l2>;
81 cpu-idle-states = <&CP 81 cpu-idle-states = <&CPU_PH20>;
82 #cooling-cells = <2>; 82 #cooling-cells = <2>;
83 }; 83 };
84 84
85 l2: l2-cache { 85 l2: l2-cache {
86 compatible = "cache"; 86 compatible = "cache";
87 cache-level = <2>; 87 cache-level = <2>;
88 cache-unified; 88 cache-unified;
89 }; 89 };
90 }; 90 };
91 91
92 idle-states { 92 idle-states {
93 /* 93 /*
94 * PSCI node is not added defa 94 * PSCI node is not added default, U-boot will add missing
95 * parts if it determines to u 95 * parts if it determines to use PSCI.
96 */ 96 */
97 entry-method = "psci"; 97 entry-method = "psci";
98 98
99 CPU_PH20: cpu-ph20 { 99 CPU_PH20: cpu-ph20 {
100 compatible = "arm,idle 100 compatible = "arm,idle-state";
101 idle-state-name = "PH2 101 idle-state-name = "PH20";
102 arm,psci-suspend-param 102 arm,psci-suspend-param = <0x0>;
103 entry-latency-us = <10 103 entry-latency-us = <1000>;
104 exit-latency-us = <100 104 exit-latency-us = <1000>;
105 min-residency-us = <30 105 min-residency-us = <3000>;
106 }; 106 };
107 }; 107 };
108 108
109 memory@80000000 { 109 memory@80000000 {
110 device_type = "memory"; 110 device_type = "memory";
111 reg = <0x0 0x80000000 0 0x8000 111 reg = <0x0 0x80000000 0 0x80000000>;
112 /* DRAM space 1, size: 2 112 /* DRAM space 1, size: 2GiB DRAM */
113 }; 113 };
114 114
115 reserved-memory { 115 reserved-memory {
116 #address-cells = <2>; 116 #address-cells = <2>;
117 #size-cells = <2>; 117 #size-cells = <2>;
118 ranges; 118 ranges;
119 119
120 bman_fbpr: bman-fbpr { 120 bman_fbpr: bman-fbpr {
121 compatible = "shared-d 121 compatible = "shared-dma-pool";
122 size = <0 0x1000000>; 122 size = <0 0x1000000>;
123 alignment = <0 0x10000 123 alignment = <0 0x1000000>;
124 no-map; 124 no-map;
125 }; 125 };
126 126
127 qman_fqd: qman-fqd { 127 qman_fqd: qman-fqd {
128 compatible = "shared-d 128 compatible = "shared-dma-pool";
129 size = <0 0x400000>; 129 size = <0 0x400000>;
130 alignment = <0 0x40000 130 alignment = <0 0x400000>;
131 no-map; 131 no-map;
132 }; 132 };
133 133
134 qman_pfdr: qman-pfdr { 134 qman_pfdr: qman-pfdr {
135 compatible = "shared-d 135 compatible = "shared-dma-pool";
136 size = <0 0x2000000>; 136 size = <0 0x2000000>;
137 alignment = <0 0x20000 137 alignment = <0 0x2000000>;
138 no-map; 138 no-map;
139 }; 139 };
140 }; 140 };
141 141
142 sysclk: sysclk { 142 sysclk: sysclk {
143 compatible = "fixed-clock"; 143 compatible = "fixed-clock";
144 #clock-cells = <0>; 144 #clock-cells = <0>;
145 clock-frequency = <100000000>; 145 clock-frequency = <100000000>;
146 clock-output-names = "sysclk"; 146 clock-output-names = "sysclk";
147 }; 147 };
148 148
149 reboot { 149 reboot {
150 compatible = "syscon-reboot"; 150 compatible = "syscon-reboot";
151 regmap = <&dcfg>; 151 regmap = <&dcfg>;
152 offset = <0xb0>; 152 offset = <0xb0>;
153 mask = <0x02>; 153 mask = <0x02>;
154 }; 154 };
155 155
156 thermal-zones { 156 thermal-zones {
157 ddr-thermal { !! 157 ddr-controller {
158 polling-delay-passive 158 polling-delay-passive = <1000>;
159 polling-delay = <5000> 159 polling-delay = <5000>;
160 thermal-sensors = <&tm 160 thermal-sensors = <&tmu 0>;
161 161
162 trips { 162 trips {
163 ddr-ctrler-ale 163 ddr-ctrler-alert {
164 temper 164 temperature = <85000>;
165 hyster 165 hysteresis = <2000>;
166 type = 166 type = "passive";
167 }; 167 };
168 168
169 ddr-ctrler-cri 169 ddr-ctrler-crit {
170 temper 170 temperature = <95000>;
171 hyster 171 hysteresis = <2000>;
172 type = 172 type = "critical";
173 }; 173 };
174 }; 174 };
175 }; 175 };
176 176
177 serdes-thermal { !! 177 serdes {
178 polling-delay-passive 178 polling-delay-passive = <1000>;
179 polling-delay = <5000> 179 polling-delay = <5000>;
180 thermal-sensors = <&tm 180 thermal-sensors = <&tmu 1>;
181 181
182 trips { 182 trips {
183 serdes-alert { 183 serdes-alert {
184 temper 184 temperature = <85000>;
185 hyster 185 hysteresis = <2000>;
186 type = 186 type = "passive";
187 }; 187 };
188 188
189 serdes-crit { 189 serdes-crit {
190 temper 190 temperature = <95000>;
191 hyster 191 hysteresis = <2000>;
192 type = 192 type = "critical";
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 196
197 fman-thermal { !! 197 fman {
198 polling-delay-passive 198 polling-delay-passive = <1000>;
199 polling-delay = <5000> 199 polling-delay = <5000>;
200 thermal-sensors = <&tm 200 thermal-sensors = <&tmu 2>;
201 201
202 trips { 202 trips {
203 fman-alert { 203 fman-alert {
204 temper 204 temperature = <85000>;
205 hyster 205 hysteresis = <2000>;
206 type = 206 type = "passive";
207 }; 207 };
208 208
209 fman-crit { 209 fman-crit {
210 temper 210 temperature = <95000>;
211 hyster 211 hysteresis = <2000>;
212 type = 212 type = "critical";
213 }; 213 };
214 }; 214 };
215 }; 215 };
216 216
217 cluster-thermal { !! 217 core-cluster {
218 polling-delay-passive 218 polling-delay-passive = <1000>;
219 polling-delay = <5000> 219 polling-delay = <5000>;
220 thermal-sensors = <&tm 220 thermal-sensors = <&tmu 3>;
221 221
222 trips { 222 trips {
223 core_cluster_a 223 core_cluster_alert: core-cluster-alert {
224 temper 224 temperature = <85000>;
225 hyster 225 hysteresis = <2000>;
226 type = 226 type = "passive";
227 }; 227 };
228 228
229 core_cluster_c 229 core_cluster_crit: core-cluster-crit {
230 temper 230 temperature = <95000>;
231 hyster 231 hysteresis = <2000>;
232 type = 232 type = "critical";
233 }; 233 };
234 }; 234 };
235 235
236 cooling-maps { 236 cooling-maps {
237 map0 { 237 map0 {
238 trip = 238 trip = <&core_cluster_alert>;
239 coolin 239 cooling-device =
240 240 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
241 241 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
242 242 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
243 243 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
244 }; 244 };
245 }; 245 };
246 }; 246 };
247 247
248 sec-thermal { !! 248 sec {
249 polling-delay-passive 249 polling-delay-passive = <1000>;
250 polling-delay = <5000> 250 polling-delay = <5000>;
251 thermal-sensors = <&tm 251 thermal-sensors = <&tmu 4>;
252 252
253 trips { 253 trips {
254 sec-alert { 254 sec-alert {
255 temper 255 temperature = <85000>;
256 hyster 256 hysteresis = <2000>;
257 type = 257 type = "passive";
258 }; 258 };
259 259
260 sec-crit { 260 sec-crit {
261 temper 261 temperature = <95000>;
262 hyster 262 hysteresis = <2000>;
263 type = 263 type = "critical";
264 }; 264 };
265 }; 265 };
266 }; 266 };
267 }; 267 };
268 268
269 timer { 269 timer {
270 compatible = "arm,armv8-timer" 270 compatible = "arm,armv8-timer";
271 interrupts = <GIC_PPI 13 (GIC_ !! 271 interrupts = <1 13 0xf08>, /* Physical Secure PPI */
272 <GIC_PPI 14 (GIC_ !! 272 <1 14 0xf08>, /* Physical Non-Secure PPI */
273 <GIC_PPI 11 (GIC_ !! 273 <1 11 0xf08>, /* Virtual PPI */
274 <GIC_PPI 10 (GIC_ !! 274 <1 10 0xf08>; /* Hypervisor PPI */
275 fsl,erratum-a008585; 275 fsl,erratum-a008585;
276 }; 276 };
277 277
278 pmu { 278 pmu {
279 compatible = "arm,cortex-a53-p !! 279 compatible = "arm,armv8-pmuv3";
280 interrupts = <GIC_SPI 106 IRQ_ !! 280 interrupts = <0 106 0x4>,
281 <GIC_SPI 107 IRQ_ !! 281 <0 107 0x4>,
282 <GIC_SPI 95 IRQ_T !! 282 <0 95 0x4>,
283 <GIC_SPI 97 IRQ_T !! 283 <0 97 0x4>;
284 interrupt-affinity = <&cpu0>, 284 interrupt-affinity = <&cpu0>,
285 <&cpu1>, 285 <&cpu1>,
286 <&cpu2>, 286 <&cpu2>,
287 <&cpu3>; 287 <&cpu3>;
288 }; 288 };
289 289
290 gic: interrupt-controller@1400000 { 290 gic: interrupt-controller@1400000 {
291 compatible = "arm,gic-400"; 291 compatible = "arm,gic-400";
292 #interrupt-cells = <3>; 292 #interrupt-cells = <3>;
293 interrupt-controller; 293 interrupt-controller;
294 reg = <0x0 0x1401000 0 0x1000> 294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000> 295 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000> 296 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000> 297 <0x0 0x1406000 0 0x2000>; /* GICV */
298 interrupts = <GIC_PPI 9 (GIC_C !! 298 interrupts = <1 9 0xf08>;
299 }; 299 };
300 300
301 soc: soc { 301 soc: soc {
302 compatible = "simple-bus"; 302 compatible = "simple-bus";
303 #address-cells = <2>; 303 #address-cells = <2>;
304 #size-cells = <2>; 304 #size-cells = <2>;
305 ranges; 305 ranges;
306 dma-ranges = <0x0 0x0 0x0 0x0 306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
307 dma-coherent; 307 dma-coherent;
308 308
309 clockgen: clocking@1ee1000 { 309 clockgen: clocking@1ee1000 {
310 compatible = "fsl,ls10 310 compatible = "fsl,ls1043a-clockgen";
311 reg = <0x0 0x1ee1000 0 311 reg = <0x0 0x1ee1000 0x0 0x1000>;
312 #clock-cells = <2>; 312 #clock-cells = <2>;
313 clocks = <&sysclk>; 313 clocks = <&sysclk>;
314 }; 314 };
315 315
316 scfg: scfg@1570000 { 316 scfg: scfg@1570000 {
317 compatible = "fsl,ls10 317 compatible = "fsl,ls1043a-scfg", "syscon";
318 reg = <0x0 0x1570000 0 318 reg = <0x0 0x1570000 0x0 0x10000>;
319 big-endian; 319 big-endian;
320 #address-cells = <1>; 320 #address-cells = <1>;
321 #size-cells = <1>; 321 #size-cells = <1>;
322 ranges = <0x0 0x0 0x15 322 ranges = <0x0 0x0 0x1570000 0x10000>;
323 323
324 extirq: interrupt-cont 324 extirq: interrupt-controller@1ac {
325 compatible = " 325 compatible = "fsl,ls1043a-extirq";
326 #interrupt-cel 326 #interrupt-cells = <2>;
327 #address-cells 327 #address-cells = <0>;
328 interrupt-cont 328 interrupt-controller;
329 reg = <0x1ac 4 329 reg = <0x1ac 4>;
330 interrupt-map 330 interrupt-map =
331 <0 0 & 331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 & 332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 & 333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 & 334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 & 335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 & 336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 & 337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 & 338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 & 339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 & 340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map- 343 interrupt-map-mask = <0xf 0x0>;
344 }; 344 };
345 }; 345 };
346 346
347 crypto: crypto@1700000 { 347 crypto: crypto@1700000 {
348 compatible = "fsl,sec- 348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec- 349 "fsl,sec-v4.0";
350 fsl,sec-era = <3>; 350 fsl,sec-era = <3>;
351 #address-cells = <1>; 351 #address-cells = <1>;
352 #size-cells = <1>; 352 #size-cells = <1>;
353 ranges = <0x0 0x00 0x1 353 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 354 reg = <0x00 0x1700000 0x0 0x100000>;
355 interrupts = <GIC_SPI !! 355 interrupts = <0 75 0x4>;
356 dma-coherent; 356 dma-coherent;
357 357
358 sec_jr0: jr@10000 { 358 sec_jr0: jr@10000 {
359 compatible = " 359 compatible = "fsl,sec-v5.4-job-ring",
360 " 360 "fsl,sec-v5.0-job-ring",
361 " 361 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 362 reg = <0x10000 0x10000>;
363 interrupts = < !! 363 interrupts = <0 71 0x4>;
364 }; 364 };
365 365
366 sec_jr1: jr@20000 { 366 sec_jr1: jr@20000 {
367 compatible = " 367 compatible = "fsl,sec-v5.4-job-ring",
368 " 368 "fsl,sec-v5.0-job-ring",
369 " 369 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 370 reg = <0x20000 0x10000>;
371 interrupts = < !! 371 interrupts = <0 72 0x4>;
372 }; 372 };
373 373
374 sec_jr2: jr@30000 { 374 sec_jr2: jr@30000 {
375 compatible = " 375 compatible = "fsl,sec-v5.4-job-ring",
376 " 376 "fsl,sec-v5.0-job-ring",
377 " 377 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 378 reg = <0x30000 0x10000>;
379 interrupts = < !! 379 interrupts = <0 73 0x4>;
380 }; 380 };
381 381
382 sec_jr3: jr@40000 { 382 sec_jr3: jr@40000 {
383 compatible = " 383 compatible = "fsl,sec-v5.4-job-ring",
384 " 384 "fsl,sec-v5.0-job-ring",
385 " 385 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 386 reg = <0x40000 0x10000>;
387 interrupts = < !! 387 interrupts = <0 74 0x4>;
388 }; 388 };
389 }; 389 };
390 390
391 sfp: efuse@1e80000 { 391 sfp: efuse@1e80000 {
392 compatible = "fsl,ls10 392 compatible = "fsl,ls1021a-sfp";
393 reg = <0x0 0x1e80000 0 393 reg = <0x0 0x1e80000 0x0 0x10000>;
394 clocks = <&clockgen QO 394 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
395 QO 395 QORIQ_CLK_PLL_DIV(4)>;
396 clock-names = "sfp"; 396 clock-names = "sfp";
397 }; 397 };
398 398
399 dcfg: dcfg@1ee0000 { 399 dcfg: dcfg@1ee0000 {
400 compatible = "fsl,ls10 400 compatible = "fsl,ls1043a-dcfg", "syscon";
401 reg = <0x0 0x1ee0000 0 401 reg = <0x0 0x1ee0000 0x0 0x1000>;
402 big-endian; 402 big-endian;
403 }; 403 };
404 404
405 ifc: memory-controller@1530000 405 ifc: memory-controller@1530000 {
406 compatible = "fsl,ifc" 406 compatible = "fsl,ifc";
407 reg = <0x0 0x1530000 0 407 reg = <0x0 0x1530000 0x0 0x10000>;
408 interrupts = <GIC_SPI !! 408 interrupts = <0 43 0x4>;
409 }; 409 };
410 410
411 qspi: spi@1550000 { 411 qspi: spi@1550000 {
412 compatible = "fsl,ls10 412 compatible = "fsl,ls1043a-qspi", "fsl,ls1021a-qspi";
413 #address-cells = <1>; 413 #address-cells = <1>;
414 #size-cells = <0>; 414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0 415 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x4000000 416 <0x0 0x40000000 0x0 0x4000000>;
417 reg-names = "QuadSPI", 417 reg-names = "QuadSPI", "QuadSPI-memory";
418 interrupts = <GIC_SPI !! 418 interrupts = <0 99 0x4>;
419 clock-names = "qspi_en 419 clock-names = "qspi_en", "qspi";
420 clocks = <&clockgen QO 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
421 QO 421 QORIQ_CLK_PLL_DIV(1)>,
422 <&clockgen QO 422 <&clockgen QORIQ_CLK_PLATFORM_PLL
423 QO 423 QORIQ_CLK_PLL_DIV(1)>;
424 status = "disabled"; 424 status = "disabled";
425 }; 425 };
426 426
427 esdhc: mmc@1560000 { !! 427 esdhc: esdhc@1560000 {
428 compatible = "fsl,ls10 428 compatible = "fsl,ls1043a-esdhc", "fsl,esdhc";
429 reg = <0x0 0x1560000 0 429 reg = <0x0 0x1560000 0x0 0x10000>;
430 interrupts = <GIC_SPI !! 430 interrupts = <0 62 0x4>;
431 clock-frequency = <0>; 431 clock-frequency = <0>;
432 voltage-ranges = <1800 432 voltage-ranges = <1800 1800 3300 3300>;
433 sdhci,auto-cmd12; 433 sdhci,auto-cmd12;
>> 434 big-endian;
434 bus-width = <4>; 435 bus-width = <4>;
435 }; 436 };
436 437
437 ddr: memory-controller@1080000 438 ddr: memory-controller@1080000 {
438 compatible = "fsl,qori 439 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1080000 0 440 reg = <0x0 0x1080000 0x0 0x1000>;
440 interrupts = <GIC_SPI !! 441 interrupts = <0 144 0x4>;
>> 442 big-endian;
441 }; 443 };
442 444
443 tmu: tmu@1f00000 { 445 tmu: tmu@1f00000 {
444 compatible = "fsl,qori 446 compatible = "fsl,qoriq-tmu";
445 reg = <0x0 0x1f00000 0 447 reg = <0x0 0x1f00000 0x0 0x10000>;
446 interrupts = <GIC_SPI !! 448 interrupts = <0 33 0x4>;
447 fsl,tmu-range = <0xb00 449 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
448 fsl,tmu-calibration = !! 450 fsl,tmu-calibration = <0x00000000 0x00000023
449 <0x000 !! 451 0x00000001 0x0000002a
450 <0x000 !! 452 0x00000002 0x00000031
451 <0x000 !! 453 0x00000003 0x00000037
452 <0x000 !! 454 0x00000004 0x0000003e
453 <0x000 !! 455 0x00000005 0x00000044
454 <0x000 !! 456 0x00000006 0x0000004b
455 <0x000 !! 457 0x00000007 0x00000051
456 <0x000 !! 458 0x00000008 0x00000058
457 <0x000 !! 459 0x00000009 0x0000005e
458 <0x000 !! 460 0x0000000a 0x00000065
459 <0x000 !! 461 0x0000000b 0x0000006b
460 <0x000 !! 462
461 !! 463 0x00010000 0x00000023
462 <0x000 !! 464 0x00010001 0x0000002b
463 <0x000 !! 465 0x00010002 0x00000033
464 <0x000 !! 466 0x00010003 0x0000003b
465 <0x000 !! 467 0x00010004 0x00000043
466 <0x000 !! 468 0x00010005 0x0000004b
467 <0x000 !! 469 0x00010006 0x00000054
468 <0x000 !! 470 0x00010007 0x0000005c
469 <0x000 !! 471 0x00010008 0x00000064
470 <0x000 !! 472 0x00010009 0x0000006c
471 <0x000 !! 473
472 !! 474 0x00020000 0x00000021
473 <0x000 !! 475 0x00020001 0x0000002c
474 <0x000 !! 476 0x00020002 0x00000036
475 <0x000 !! 477 0x00020003 0x00000040
476 <0x000 !! 478 0x00020004 0x0000004b
477 <0x000 !! 479 0x00020005 0x00000055
478 <0x000 !! 480 0x00020006 0x0000005f
479 <0x000 !! 481
480 !! 482 0x00030000 0x00000013
481 <0x000 !! 483 0x00030001 0x0000001d
482 <0x000 !! 484 0x00030002 0x00000028
483 <0x000 !! 485 0x00030003 0x00000032
484 <0x000 !! 486 0x00030004 0x0000003d
485 <0x000 !! 487 0x00030005 0x00000047
486 <0x000 !! 488 0x00030006 0x00000052
487 <0x000 !! 489 0x00030007 0x0000005c>;
488 <0x000 <<
489 #thermal-sensor-cells 490 #thermal-sensor-cells = <1>;
490 }; 491 };
491 492
492 qman: qman@1880000 { 493 qman: qman@1880000 {
493 compatible = "fsl,qman 494 compatible = "fsl,qman";
494 reg = <0x0 0x1880000 0 495 reg = <0x0 0x1880000 0x0 0x10000>;
495 interrupts = <GIC_SPI 496 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
496 memory-region = <&qman 497 memory-region = <&qman_fqd &qman_pfdr>;
497 }; 498 };
498 499
499 bman: bman@1890000 { 500 bman: bman@1890000 {
500 compatible = "fsl,bman 501 compatible = "fsl,bman";
501 reg = <0x0 0x1890000 0 502 reg = <0x0 0x1890000 0x0 0x10000>;
502 interrupts = <GIC_SPI 503 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
503 memory-region = <&bman 504 memory-region = <&bman_fbpr>;
504 }; 505 };
505 506
506 bportals: bman-portals-bus@508 !! 507 bportals: bman-portals@508000000 {
507 ranges = <0x0 0x5 0x08 508 ranges = <0x0 0x5 0x08000000 0x8000000>;
508 }; 509 };
509 510
510 qportals: qman-portals-bus@500 !! 511 qportals: qman-portals@500000000 {
511 ranges = <0x0 0x5 0x00 512 ranges = <0x0 0x5 0x00000000 0x8000000>;
512 }; 513 };
513 514
514 dspi0: spi@2100000 { 515 dspi0: spi@2100000 {
515 compatible = "fsl,ls10 516 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
516 #address-cells = <1>; 517 #address-cells = <1>;
517 #size-cells = <0>; 518 #size-cells = <0>;
518 reg = <0x0 0x2100000 0 519 reg = <0x0 0x2100000 0x0 0x10000>;
519 interrupts = <GIC_SPI !! 520 interrupts = <0 64 0x4>;
520 clock-names = "dspi"; 521 clock-names = "dspi";
521 clocks = <&clockgen QO 522 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
522 QO 523 QORIQ_CLK_PLL_DIV(1)>;
523 spi-num-chipselects = 524 spi-num-chipselects = <5>;
524 big-endian; 525 big-endian;
525 status = "disabled"; 526 status = "disabled";
526 }; 527 };
527 528
528 i2c0: i2c@2180000 { 529 i2c0: i2c@2180000 {
529 compatible = "fsl,ls10 530 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
530 #address-cells = <1>; 531 #address-cells = <1>;
531 #size-cells = <0>; 532 #size-cells = <0>;
532 reg = <0x0 0x2180000 0 533 reg = <0x0 0x2180000 0x0 0x10000>;
533 interrupts = <GIC_SPI !! 534 interrupts = <0 56 0x4>;
534 clock-names = "ipg"; !! 535 clock-names = "i2c";
535 clocks = <&clockgen QO 536 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
536 QO 537 QORIQ_CLK_PLL_DIV(1)>;
537 dmas = <&edma0 1 38>, 538 dmas = <&edma0 1 38>,
538 <&edma0 1 39>; 539 <&edma0 1 39>;
539 dma-names = "rx", "tx" 540 dma-names = "rx", "tx";
540 status = "disabled"; 541 status = "disabled";
541 }; 542 };
542 543
543 i2c1: i2c@2190000 { 544 i2c1: i2c@2190000 {
544 compatible = "fsl,ls10 545 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
545 #address-cells = <1>; 546 #address-cells = <1>;
546 #size-cells = <0>; 547 #size-cells = <0>;
547 reg = <0x0 0x2190000 0 548 reg = <0x0 0x2190000 0x0 0x10000>;
548 interrupts = <GIC_SPI !! 549 interrupts = <0 57 0x4>;
549 clock-names = "ipg"; !! 550 clock-names = "i2c";
550 clocks = <&clockgen QO 551 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
551 QO 552 QORIQ_CLK_PLL_DIV(1)>;
552 scl-gpios = <&gpio4 2 553 scl-gpios = <&gpio4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
553 status = "disabled"; 554 status = "disabled";
554 }; 555 };
555 556
556 i2c2: i2c@21a0000 { 557 i2c2: i2c@21a0000 {
557 compatible = "fsl,ls10 558 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
558 #address-cells = <1>; 559 #address-cells = <1>;
559 #size-cells = <0>; 560 #size-cells = <0>;
560 reg = <0x0 0x21a0000 0 561 reg = <0x0 0x21a0000 0x0 0x10000>;
561 interrupts = <GIC_SPI !! 562 interrupts = <0 58 0x4>;
562 clock-names = "ipg"; !! 563 clock-names = "i2c";
563 clocks = <&clockgen QO 564 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
564 QO 565 QORIQ_CLK_PLL_DIV(1)>;
565 scl-gpios = <&gpio4 10 566 scl-gpios = <&gpio4 10 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
566 status = "disabled"; 567 status = "disabled";
567 }; 568 };
568 569
569 i2c3: i2c@21b0000 { 570 i2c3: i2c@21b0000 {
570 compatible = "fsl,ls10 571 compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c";
571 #address-cells = <1>; 572 #address-cells = <1>;
572 #size-cells = <0>; 573 #size-cells = <0>;
573 reg = <0x0 0x21b0000 0 574 reg = <0x0 0x21b0000 0x0 0x10000>;
574 interrupts = <GIC_SPI !! 575 interrupts = <0 59 0x4>;
575 clock-names = "ipg"; !! 576 clock-names = "i2c";
576 clocks = <&clockgen QO 577 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
577 QO 578 QORIQ_CLK_PLL_DIV(1)>;
578 scl-gpios = <&gpio4 12 579 scl-gpios = <&gpio4 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
579 status = "disabled"; 580 status = "disabled";
580 }; 581 };
581 582
582 duart0: serial@21c0500 { 583 duart0: serial@21c0500 {
583 compatible = "fsl,ns16 584 compatible = "fsl,ns16550", "ns16550a";
584 reg = <0x00 0x21c0500 585 reg = <0x00 0x21c0500 0x0 0x100>;
585 interrupts = <GIC_SPI !! 586 interrupts = <0 54 0x4>;
586 clocks = <&clockgen QO 587 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
587 QO 588 QORIQ_CLK_PLL_DIV(1)>;
588 }; 589 };
589 590
590 duart1: serial@21c0600 { 591 duart1: serial@21c0600 {
591 compatible = "fsl,ns16 592 compatible = "fsl,ns16550", "ns16550a";
592 reg = <0x00 0x21c0600 593 reg = <0x00 0x21c0600 0x0 0x100>;
593 interrupts = <GIC_SPI !! 594 interrupts = <0 54 0x4>;
594 clocks = <&clockgen QO 595 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
595 QO 596 QORIQ_CLK_PLL_DIV(1)>;
596 }; 597 };
597 598
598 duart2: serial@21d0500 { 599 duart2: serial@21d0500 {
599 compatible = "fsl,ns16 600 compatible = "fsl,ns16550", "ns16550a";
600 reg = <0x0 0x21d0500 0 601 reg = <0x0 0x21d0500 0x0 0x100>;
601 interrupts = <GIC_SPI !! 602 interrupts = <0 55 0x4>;
602 clocks = <&clockgen QO 603 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
603 QO 604 QORIQ_CLK_PLL_DIV(1)>;
604 }; 605 };
605 606
606 duart3: serial@21d0600 { 607 duart3: serial@21d0600 {
607 compatible = "fsl,ns16 608 compatible = "fsl,ns16550", "ns16550a";
608 reg = <0x0 0x21d0600 0 609 reg = <0x0 0x21d0600 0x0 0x100>;
609 interrupts = <GIC_SPI !! 610 interrupts = <0 55 0x4>;
610 clocks = <&clockgen QO 611 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
611 QO 612 QORIQ_CLK_PLL_DIV(1)>;
612 }; 613 };
613 614
614 gpio1: gpio@2300000 { 615 gpio1: gpio@2300000 {
615 compatible = "fsl,ls10 616 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
616 reg = <0x0 0x2300000 0 617 reg = <0x0 0x2300000 0x0 0x10000>;
617 interrupts = <GIC_SPI !! 618 interrupts = <0 66 0x4>;
618 gpio-controller; 619 gpio-controller;
619 #gpio-cells = <2>; 620 #gpio-cells = <2>;
620 interrupt-controller; 621 interrupt-controller;
621 #interrupt-cells = <2> 622 #interrupt-cells = <2>;
622 }; 623 };
623 624
624 gpio2: gpio@2310000 { 625 gpio2: gpio@2310000 {
625 compatible = "fsl,ls10 626 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
626 reg = <0x0 0x2310000 0 627 reg = <0x0 0x2310000 0x0 0x10000>;
627 interrupts = <GIC_SPI !! 628 interrupts = <0 67 0x4>;
628 gpio-controller; 629 gpio-controller;
629 #gpio-cells = <2>; 630 #gpio-cells = <2>;
630 interrupt-controller; 631 interrupt-controller;
631 #interrupt-cells = <2> 632 #interrupt-cells = <2>;
632 }; 633 };
633 634
634 gpio3: gpio@2320000 { 635 gpio3: gpio@2320000 {
635 compatible = "fsl,ls10 636 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
636 reg = <0x0 0x2320000 0 637 reg = <0x0 0x2320000 0x0 0x10000>;
637 interrupts = <GIC_SPI !! 638 interrupts = <0 68 0x4>;
638 gpio-controller; 639 gpio-controller;
639 #gpio-cells = <2>; 640 #gpio-cells = <2>;
640 interrupt-controller; 641 interrupt-controller;
641 #interrupt-cells = <2> 642 #interrupt-cells = <2>;
642 }; 643 };
643 644
644 gpio4: gpio@2330000 { 645 gpio4: gpio@2330000 {
645 compatible = "fsl,ls10 646 compatible = "fsl,ls1043a-gpio", "fsl,qoriq-gpio";
646 reg = <0x0 0x2330000 0 647 reg = <0x0 0x2330000 0x0 0x10000>;
647 interrupts = <GIC_SPI !! 648 interrupts = <0 134 0x4>;
648 gpio-controller; 649 gpio-controller;
649 #gpio-cells = <2>; 650 #gpio-cells = <2>;
650 interrupt-controller; 651 interrupt-controller;
651 #interrupt-cells = <2> 652 #interrupt-cells = <2>;
652 }; 653 };
653 654
654 uqe: uqe-bus@2400000 { !! 655 uqe: uqe@2400000 {
655 #address-cells = <1>; 656 #address-cells = <1>;
656 #size-cells = <1>; 657 #size-cells = <1>;
657 compatible = "fsl,qe", 658 compatible = "fsl,qe", "simple-bus";
658 ranges = <0x0 0x0 0x24 659 ranges = <0x0 0x0 0x2400000 0x40000>;
659 reg = <0x0 0x2400000 0 660 reg = <0x0 0x2400000 0x0 0x480>;
660 brg-frequency = <10000 661 brg-frequency = <100000000>;
661 bus-frequency = <20000 662 bus-frequency = <200000000>;
662 fsl,qe-num-riscs = <1> 663 fsl,qe-num-riscs = <1>;
663 fsl,qe-num-snums = <28 664 fsl,qe-num-snums = <28>;
664 665
665 qeic: qeic@80 { 666 qeic: qeic@80 {
666 compatible = " 667 compatible = "fsl,qe-ic";
667 reg = <0x80 0x 668 reg = <0x80 0x80>;
>> 669 #address-cells = <0>;
668 interrupt-cont 670 interrupt-controller;
669 #interrupt-cel 671 #interrupt-cells = <1>;
670 interrupts = < 672 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
671 < 673 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
672 }; 674 };
673 675
674 si1: si@700 { 676 si1: si@700 {
>> 677 #address-cells = <1>;
>> 678 #size-cells = <0>;
675 compatible = " 679 compatible = "fsl,ls1043-qe-si",
676 680 "fsl,t1040-qe-si";
677 reg = <0x700 0 681 reg = <0x700 0x80>;
678 }; 682 };
679 683
680 siram1: siram@1000 { 684 siram1: siram@1000 {
>> 685 #address-cells = <1>;
>> 686 #size-cells = <1>;
681 compatible = " 687 compatible = "fsl,ls1043-qe-siram",
682 688 "fsl,t1040-qe-siram";
683 reg = <0x1000 689 reg = <0x1000 0x800>;
684 }; 690 };
685 691
686 ucc@2000 { 692 ucc@2000 {
687 cell-index = < 693 cell-index = <1>;
688 reg = <0x2000 694 reg = <0x2000 0x200>;
689 interrupts = < 695 interrupts = <32>;
690 interrupt-pare 696 interrupt-parent = <&qeic>;
691 }; 697 };
692 698
693 ucc@2200 { 699 ucc@2200 {
694 cell-index = < 700 cell-index = <3>;
695 reg = <0x2200 701 reg = <0x2200 0x200>;
696 interrupts = < 702 interrupts = <34>;
697 interrupt-pare 703 interrupt-parent = <&qeic>;
698 }; 704 };
699 705
700 muram@10000 { 706 muram@10000 {
701 #address-cells 707 #address-cells = <1>;
702 #size-cells = 708 #size-cells = <1>;
703 compatible = " 709 compatible = "fsl,qe-muram", "fsl,cpm-muram";
704 ranges = <0x0 710 ranges = <0x0 0x10000 0x6000>;
705 711
706 data-only@0 { 712 data-only@0 {
707 compat 713 compatible = "fsl,qe-muram-data",
708 "fsl,c 714 "fsl,cpm-muram-data";
709 reg = 715 reg = <0x0 0x6000>;
710 }; 716 };
711 }; 717 };
712 }; 718 };
713 719
714 lpuart0: serial@2950000 { 720 lpuart0: serial@2950000 {
715 compatible = "fsl,ls10 721 compatible = "fsl,ls1021a-lpuart";
716 reg = <0x0 0x2950000 0 722 reg = <0x0 0x2950000 0x0 0x1000>;
717 interrupts = <GIC_SPI !! 723 interrupts = <0 48 0x4>;
718 clocks = <&clockgen QO 724 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
719 clock-names = "ipg"; 725 clock-names = "ipg";
720 status = "disabled"; 726 status = "disabled";
721 }; 727 };
722 728
723 lpuart1: serial@2960000 { 729 lpuart1: serial@2960000 {
724 compatible = "fsl,ls10 730 compatible = "fsl,ls1021a-lpuart";
725 reg = <0x0 0x2960000 0 731 reg = <0x0 0x2960000 0x0 0x1000>;
726 interrupts = <GIC_SPI !! 732 interrupts = <0 49 0x4>;
727 clocks = <&clockgen QO 733 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
728 QO 734 QORIQ_CLK_PLL_DIV(1)>;
729 clock-names = "ipg"; 735 clock-names = "ipg";
730 status = "disabled"; 736 status = "disabled";
731 }; 737 };
732 738
733 lpuart2: serial@2970000 { 739 lpuart2: serial@2970000 {
734 compatible = "fsl,ls10 740 compatible = "fsl,ls1021a-lpuart";
735 reg = <0x0 0x2970000 0 741 reg = <0x0 0x2970000 0x0 0x1000>;
736 interrupts = <GIC_SPI !! 742 interrupts = <0 50 0x4>;
737 clocks = <&clockgen QO 743 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
738 QO 744 QORIQ_CLK_PLL_DIV(1)>;
739 clock-names = "ipg"; 745 clock-names = "ipg";
740 status = "disabled"; 746 status = "disabled";
741 }; 747 };
742 748
743 lpuart3: serial@2980000 { 749 lpuart3: serial@2980000 {
744 compatible = "fsl,ls10 750 compatible = "fsl,ls1021a-lpuart";
745 reg = <0x0 0x2980000 0 751 reg = <0x0 0x2980000 0x0 0x1000>;
746 interrupts = <GIC_SPI !! 752 interrupts = <0 51 0x4>;
747 clocks = <&clockgen QO 753 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
748 QO 754 QORIQ_CLK_PLL_DIV(1)>;
749 clock-names = "ipg"; 755 clock-names = "ipg";
750 status = "disabled"; 756 status = "disabled";
751 }; 757 };
752 758
753 lpuart4: serial@2990000 { 759 lpuart4: serial@2990000 {
754 compatible = "fsl,ls10 760 compatible = "fsl,ls1021a-lpuart";
755 reg = <0x0 0x2990000 0 761 reg = <0x0 0x2990000 0x0 0x1000>;
756 interrupts = <GIC_SPI !! 762 interrupts = <0 52 0x4>;
757 clocks = <&clockgen QO 763 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
758 QO 764 QORIQ_CLK_PLL_DIV(1)>;
759 clock-names = "ipg"; 765 clock-names = "ipg";
760 status = "disabled"; 766 status = "disabled";
761 }; 767 };
762 768
763 lpuart5: serial@29a0000 { 769 lpuart5: serial@29a0000 {
764 compatible = "fsl,ls10 770 compatible = "fsl,ls1021a-lpuart";
765 reg = <0x0 0x29a0000 0 771 reg = <0x0 0x29a0000 0x0 0x1000>;
766 interrupts = <GIC_SPI !! 772 interrupts = <0 53 0x4>;
767 clocks = <&clockgen QO 773 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
768 QO 774 QORIQ_CLK_PLL_DIV(1)>;
769 clock-names = "ipg"; 775 clock-names = "ipg";
770 status = "disabled"; 776 status = "disabled";
771 }; 777 };
772 778
773 wdog0: watchdog@2ad0000 { 779 wdog0: watchdog@2ad0000 {
774 compatible = "fsl,ls10 780 compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt";
775 reg = <0x0 0x2ad0000 0 781 reg = <0x0 0x2ad0000 0x0 0x10000>;
776 interrupts = <GIC_SPI !! 782 interrupts = <0 83 0x4>;
777 clocks = <&clockgen QO 783 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
778 QO 784 QORIQ_CLK_PLL_DIV(1)>;
>> 785 clock-names = "wdog";
779 big-endian; 786 big-endian;
780 }; 787 };
781 788
782 edma0: dma-controller@2c00000 789 edma0: dma-controller@2c00000 {
783 #dma-cells = <2>; 790 #dma-cells = <2>;
784 compatible = "fsl,vf61 791 compatible = "fsl,vf610-edma";
785 reg = <0x0 0x2c00000 0 792 reg = <0x0 0x2c00000 0x0 0x10000>,
786 <0x0 0x2c10000 0 793 <0x0 0x2c10000 0x0 0x10000>,
787 <0x0 0x2c20000 0 794 <0x0 0x2c20000 0x0 0x10000>;
788 interrupts = <GIC_SPI !! 795 interrupts = <0 103 0x4>,
789 <GIC_SPI !! 796 <0 103 0x4>;
790 interrupt-names = "edm 797 interrupt-names = "edma-tx", "edma-err";
791 dma-channels = <32>; 798 dma-channels = <32>;
792 big-endian; 799 big-endian;
793 clock-names = "dmamux0 800 clock-names = "dmamux0", "dmamux1";
794 clocks = <&clockgen QO 801 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
795 QO 802 QORIQ_CLK_PLL_DIV(1)>,
796 <&clockgen QO 803 <&clockgen QORIQ_CLK_PLATFORM_PLL
797 QO 804 QORIQ_CLK_PLL_DIV(1)>;
798 }; 805 };
799 806
800 aux_bus: bus { !! 807 aux_bus: aux_bus {
801 #address-cells = <2>; 808 #address-cells = <2>;
802 #size-cells = <2>; 809 #size-cells = <2>;
803 compatible = "simple-b 810 compatible = "simple-bus";
804 ranges; 811 ranges;
805 dma-ranges = <0x0 0x0 812 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
806 813
807 usb0: usb@2f00000 { 814 usb0: usb@2f00000 {
808 compatible = " 815 compatible = "snps,dwc3";
809 reg = <0x0 0x2 816 reg = <0x0 0x2f00000 0x0 0x10000>;
810 interrupts = < !! 817 interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
811 dr_mode = "hos 818 dr_mode = "host";
812 snps,quirk-fra 819 snps,quirk-frame-length-adjustment = <0x20>;
813 snps,dis_rxdet 820 snps,dis_rxdet_inp3_quirk;
814 usb3-lpm-capab 821 usb3-lpm-capable;
815 snps,incr-burs 822 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
816 status = "disa 823 status = "disabled";
817 }; 824 };
818 825
819 usb1: usb@3000000 { 826 usb1: usb@3000000 {
820 compatible = " 827 compatible = "snps,dwc3";
821 reg = <0x0 0x3 828 reg = <0x0 0x3000000 0x0 0x10000>;
822 interrupts = < !! 829 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
823 dr_mode = "hos 830 dr_mode = "host";
824 snps,quirk-fra 831 snps,quirk-frame-length-adjustment = <0x20>;
825 snps,dis_rxdet 832 snps,dis_rxdet_inp3_quirk;
826 usb3-lpm-capab 833 usb3-lpm-capable;
827 snps,incr-burs 834 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
828 status = "disa 835 status = "disabled";
829 }; 836 };
830 837
831 usb2: usb@3100000 { 838 usb2: usb@3100000 {
832 compatible = " 839 compatible = "snps,dwc3";
833 reg = <0x0 0x3 840 reg = <0x0 0x3100000 0x0 0x10000>;
834 interrupts = < !! 841 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
835 dr_mode = "hos 842 dr_mode = "host";
836 snps,quirk-fra 843 snps,quirk-frame-length-adjustment = <0x20>;
837 snps,dis_rxdet 844 snps,dis_rxdet_inp3_quirk;
838 usb3-lpm-capab 845 usb3-lpm-capable;
839 snps,incr-burs 846 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
840 status = "disa 847 status = "disabled";
841 }; 848 };
842 849
843 sata: sata@3200000 { 850 sata: sata@3200000 {
844 compatible = " 851 compatible = "fsl,ls1043a-ahci";
845 reg = <0x0 0x3 852 reg = <0x0 0x3200000 0x0 0x10000>,
846 <0x0 0 853 <0x0 0x20140520 0x0 0x4>;
847 reg-names = "a 854 reg-names = "ahci", "sata-ecc";
848 interrupts = < !! 855 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
849 clocks = <&clo 856 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
850 857 QORIQ_CLK_PLL_DIV(1)>;
851 dma-coherent; 858 dma-coherent;
852 }; 859 };
853 }; 860 };
854 861
855 msi1: msi-controller1@1571000 862 msi1: msi-controller1@1571000 {
856 compatible = "fsl,ls10 863 compatible = "fsl,ls1043a-msi";
857 reg = <0x0 0x1571000 0 864 reg = <0x0 0x1571000 0x0 0x8>;
858 msi-controller; 865 msi-controller;
859 interrupts = <GIC_SPI !! 866 interrupts = <0 116 0x4>;
860 }; 867 };
861 868
862 msi2: msi-controller2@1572000 869 msi2: msi-controller2@1572000 {
863 compatible = "fsl,ls10 870 compatible = "fsl,ls1043a-msi";
864 reg = <0x0 0x1572000 0 871 reg = <0x0 0x1572000 0x0 0x8>;
865 msi-controller; 872 msi-controller;
866 interrupts = <GIC_SPI !! 873 interrupts = <0 126 0x4>;
867 }; 874 };
868 875
869 msi3: msi-controller3@1573000 876 msi3: msi-controller3@1573000 {
870 compatible = "fsl,ls10 877 compatible = "fsl,ls1043a-msi";
871 reg = <0x0 0x1573000 0 878 reg = <0x0 0x1573000 0x0 0x8>;
872 msi-controller; 879 msi-controller;
873 interrupts = <GIC_SPI !! 880 interrupts = <0 160 0x4>;
874 }; 881 };
875 882
876 pcie1: pcie@3400000 { 883 pcie1: pcie@3400000 {
877 compatible = "fsl,ls10 884 compatible = "fsl,ls1043a-pcie";
878 reg = <0x00 0x03400000 885 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
879 <0x40 0x00000000 886 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
880 reg-names = "regs", "c 887 reg-names = "regs", "config";
881 interrupts = <GIC_SPI !! 888 interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>,
882 <GIC_SPI !! 889 <0 118 IRQ_TYPE_LEVEL_HIGH>;
883 interrupt-names = "pme 890 interrupt-names = "pme", "aer";
884 #address-cells = <3>; 891 #address-cells = <3>;
885 #size-cells = <2>; 892 #size-cells = <2>;
886 device_type = "pci"; 893 device_type = "pci";
887 num-viewport = <6>; 894 num-viewport = <6>;
888 bus-range = <0x0 0xff> 895 bus-range = <0x0 0xff>;
889 ranges = <0x81000000 0 896 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
890 0x82000000 0 897 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 msi-parent = <&msi1>, 898 msi-parent = <&msi1>, <&msi2>, <&msi3>;
892 #interrupt-cells = <1> 899 #interrupt-cells = <1>;
893 interrupt-map-mask = < 900 interrupt-map-mask = <0 0 0 7>;
894 interrupt-map = <0000 901 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
895 <0000 902 <0000 0 0 2 &gic 0 111 0x4>,
896 <0000 903 <0000 0 0 3 &gic 0 112 0x4>,
897 <0000 904 <0000 0 0 4 &gic 0 113 0x4>;
898 fsl,pcie-scfg = <&scfg 905 fsl,pcie-scfg = <&scfg 0>;
899 big-endian; 906 big-endian;
900 status = "disabled"; 907 status = "disabled";
901 }; 908 };
902 909
903 pcie2: pcie@3500000 { 910 pcie2: pcie@3500000 {
904 compatible = "fsl,ls10 911 compatible = "fsl,ls1043a-pcie";
905 reg = <0x00 0x03500000 912 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
906 <0x48 0x00000000 913 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
907 reg-names = "regs", "c 914 reg-names = "regs", "config";
908 interrupts = <GIC_SPI !! 915 interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI !! 916 <0 128 IRQ_TYPE_LEVEL_HIGH>;
910 interrupt-names = "pme 917 interrupt-names = "pme", "aer";
911 #address-cells = <3>; 918 #address-cells = <3>;
912 #size-cells = <2>; 919 #size-cells = <2>;
913 device_type = "pci"; 920 device_type = "pci";
914 num-viewport = <6>; 921 num-viewport = <6>;
915 bus-range = <0x0 0xff> 922 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0 923 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0 924 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
918 msi-parent = <&msi1>, 925 msi-parent = <&msi1>, <&msi2>, <&msi3>;
919 #interrupt-cells = <1> 926 #interrupt-cells = <1>;
920 interrupt-map-mask = < 927 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 928 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
922 <0000 929 <0000 0 0 2 &gic 0 121 0x4>,
923 <0000 930 <0000 0 0 3 &gic 0 122 0x4>,
924 <0000 931 <0000 0 0 4 &gic 0 123 0x4>;
925 fsl,pcie-scfg = <&scfg 932 fsl,pcie-scfg = <&scfg 1>;
926 big-endian; 933 big-endian;
927 status = "disabled"; 934 status = "disabled";
928 }; 935 };
929 936
930 pcie3: pcie@3600000 { 937 pcie3: pcie@3600000 {
931 compatible = "fsl,ls10 938 compatible = "fsl,ls1043a-pcie";
932 reg = <0x00 0x03600000 939 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
933 <0x50 0x00000000 940 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
934 reg-names = "regs", "c 941 reg-names = "regs", "config";
935 interrupts = <GIC_SPI !! 942 interrupts = <0 161 IRQ_TYPE_LEVEL_HIGH>,
936 <GIC_SPI !! 943 <0 162 IRQ_TYPE_LEVEL_HIGH>;
937 interrupt-names = "pme 944 interrupt-names = "pme", "aer";
938 #address-cells = <3>; 945 #address-cells = <3>;
939 #size-cells = <2>; 946 #size-cells = <2>;
940 device_type = "pci"; 947 device_type = "pci";
941 num-viewport = <6>; 948 num-viewport = <6>;
942 bus-range = <0x0 0xff> 949 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0 950 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0 951 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
945 msi-parent = <&msi1>, 952 msi-parent = <&msi1>, <&msi2>, <&msi3>;
946 #interrupt-cells = <1> 953 #interrupt-cells = <1>;
947 interrupt-map-mask = < 954 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 955 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
949 <0000 956 <0000 0 0 2 &gic 0 155 0x4>,
950 <0000 957 <0000 0 0 3 &gic 0 156 0x4>,
951 <0000 958 <0000 0 0 4 &gic 0 157 0x4>;
952 fsl,pcie-scfg = <&scfg 959 fsl,pcie-scfg = <&scfg 2>;
953 big-endian; 960 big-endian;
954 status = "disabled"; 961 status = "disabled";
955 }; 962 };
956 963
957 qdma: dma-controller@8380000 { 964 qdma: dma-controller@8380000 {
958 compatible = "fsl,ls10 !! 965 compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma";
959 reg = <0x0 0x8380000 0 966 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
960 <0x0 0x8390000 0 967 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
961 <0x0 0x83a0000 0 968 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
962 interrupts = <GIC_SPI 969 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 970 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 971 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 972 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 973 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
967 interrupt-names = "qdm 974 interrupt-names = "qdma-error", "qdma-queue0",
968 "qdma-queue1", 975 "qdma-queue1", "qdma-queue2", "qdma-queue3";
969 #dma-cells = <1>; <<
970 dma-channels = <8>; 976 dma-channels = <8>;
971 block-number = <1>; 977 block-number = <1>;
972 block-offset = <0x1000 978 block-offset = <0x10000>;
973 fsl,dma-queues = <2>; 979 fsl,dma-queues = <2>;
974 status-sizes = <64>; 980 status-sizes = <64>;
975 queue-sizes = <64 64>; 981 queue-sizes = <64 64>;
976 big-endian; 982 big-endian;
977 }; 983 };
978 984
979 rcpm: wakeup-controller@1ee214 !! 985 rcpm: power-controller@1ee2140 {
980 compatible = "fsl,ls10 986 compatible = "fsl,ls1043a-rcpm", "fsl,qoriq-rcpm-2.1+";
981 reg = <0x0 0x1ee2140 0 987 reg = <0x0 0x1ee2140 0x0 0x4>;
982 #fsl,rcpm-wakeup-cells 988 #fsl,rcpm-wakeup-cells = <1>;
983 }; 989 };
984 990
985 ftm_alarm0: rtc@29d0000 { !! 991 ftm_alarm0: timer@29d0000 {
986 compatible = "fsl,ls10 992 compatible = "fsl,ls1043a-ftm-alarm";
987 reg = <0x0 0x29d0000 0 993 reg = <0x0 0x29d0000 0x0 0x10000>;
988 fsl,rcpm-wakeup = <&rc 994 fsl,rcpm-wakeup = <&rcpm 0x20000>;
989 interrupts = <GIC_SPI 995 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
990 big-endian; 996 big-endian;
991 }; 997 };
992 }; 998 };
993 999
994 firmware { 1000 firmware {
995 optee { 1001 optee {
996 compatible = "linaro,o 1002 compatible = "linaro,optee-tz";
997 method = "smc"; 1003 method = "smc";
998 }; 1004 };
999 }; 1005 };
1000 1006
1001 }; 1007 };
1002 1008
1003 #include "qoriq-qman-portals.dtsi" 1009 #include "qoriq-qman-portals.dtsi"
1004 #include "qoriq-bman-portals.dtsi" 1010 #include "qoriq-bman-portals.dtsi"
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.