1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Freescale Laye 3 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
4 * 4 *
5 * Copyright 2016 Freescale Semiconductor, Inc 5 * Copyright 2016 Freescale Semiconductor, Inc.
6 * Copyright 2019-2020 NXP <<
7 * 6 *
8 * Mingkai Hu <mingkai.hu@nxp.com> 7 * Mingkai Hu <mingkai.hu@nxp.com>
9 */ 8 */
10 9
11 /dts-v1/; 10 /dts-v1/;
12 11
13 #include "fsl-ls1046a.dtsi" 12 #include "fsl-ls1046a.dtsi"
14 13
15 / { 14 / {
16 model = "LS1046A RDB Board"; 15 model = "LS1046A RDB Board";
17 compatible = "fsl,ls1046a-rdb", "fsl,l 16 compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
18 17
19 aliases { 18 aliases {
20 serial0 = &duart0; 19 serial0 = &duart0;
21 serial1 = &duart1; 20 serial1 = &duart1;
22 serial2 = &duart2; 21 serial2 = &duart2;
23 serial3 = &duart3; 22 serial3 = &duart3;
24 }; 23 };
25 24
26 chosen { 25 chosen {
27 stdout-path = "serial0:115200n 26 stdout-path = "serial0:115200n8";
28 }; 27 };
29 }; 28 };
30 29
31 &duart0 { 30 &duart0 {
32 status = "okay"; 31 status = "okay";
33 }; 32 };
34 33
35 &duart1 { 34 &duart1 {
36 status = "okay"; 35 status = "okay";
37 }; 36 };
38 37
39 &esdhc { 38 &esdhc {
40 mmc-hs200-1_8v; 39 mmc-hs200-1_8v;
41 sd-uhs-sdr104; 40 sd-uhs-sdr104;
42 sd-uhs-sdr50; 41 sd-uhs-sdr50;
43 sd-uhs-sdr25; 42 sd-uhs-sdr25;
44 sd-uhs-sdr12; 43 sd-uhs-sdr12;
45 }; 44 };
46 45
47 &i2c0 { 46 &i2c0 {
48 status = "okay"; 47 status = "okay";
49 48
50 ina220@40 { 49 ina220@40 {
51 compatible = "ti,ina220"; 50 compatible = "ti,ina220";
52 reg = <0x40>; 51 reg = <0x40>;
53 shunt-resistor = <1000>; 52 shunt-resistor = <1000>;
54 }; 53 };
55 54
56 temp-sensor@4c { 55 temp-sensor@4c {
57 compatible = "adi,adt7461"; 56 compatible = "adi,adt7461";
58 reg = <0x4c>; 57 reg = <0x4c>;
59 }; 58 };
60 59
61 eeprom@52 { 60 eeprom@52 {
62 compatible = "onnn,cat24c05", !! 61 compatible = "atmel,24c512";
63 reg = <0x52>; 62 reg = <0x52>;
64 }; 63 };
>> 64
>> 65 eeprom@53 {
>> 66 compatible = "atmel,24c512";
>> 67 reg = <0x53>;
>> 68 };
65 }; 69 };
66 70
67 &i2c3 { 71 &i2c3 {
68 status = "okay"; 72 status = "okay";
69 73
70 rtc@51 { 74 rtc@51 {
71 compatible = "nxp,pcf2129"; 75 compatible = "nxp,pcf2129";
72 reg = <0x51>; 76 reg = <0x51>;
73 /* IRQ_RTC_B -> IRQ05, active <<
74 interrupts-extended = <&extirq <<
75 }; 77 };
76 }; 78 };
77 79
78 &ifc { 80 &ifc {
79 #address-cells = <2>; 81 #address-cells = <2>;
80 #size-cells = <1>; 82 #size-cells = <1>;
81 /* NAND Flashe and CPLD on board */ 83 /* NAND Flashe and CPLD on board */
82 ranges = <0x0 0x0 0x0 0x7e800000 0x000 84 ranges = <0x0 0x0 0x0 0x7e800000 0x00010000
83 0x2 0x0 0x0 0x7fb00000 0x000 85 0x2 0x0 0x0 0x7fb00000 0x00000100>;
84 status = "okay"; 86 status = "okay";
85 87
86 nand@0,0 { 88 nand@0,0 {
87 compatible = "fsl,ifc-nand"; 89 compatible = "fsl,ifc-nand";
88 #address-cells = <1>; 90 #address-cells = <1>;
89 #size-cells = <1>; 91 #size-cells = <1>;
90 reg = <0x0 0x0 0x10000>; 92 reg = <0x0 0x0 0x10000>;
91 }; 93 };
92 94
93 cpld: board-control@2,0 { 95 cpld: board-control@2,0 {
94 compatible = "fsl,ls1046ardb-c 96 compatible = "fsl,ls1046ardb-cpld";
95 reg = <0x2 0x0 0x0000100>; 97 reg = <0x2 0x0 0x0000100>;
96 }; 98 };
97 }; 99 };
98 100
99 &qspi { 101 &qspi {
100 status = "okay"; 102 status = "okay";
101 103
102 s25fs512s0: flash@0 { !! 104 qflash0: flash@0 {
103 compatible = "jedec,spi-nor"; !! 105 compatible = "spansion,m25p80";
104 #address-cells = <1>; 106 #address-cells = <1>;
105 #size-cells = <1>; 107 #size-cells = <1>;
106 spi-max-frequency = <50000000> !! 108 spi-max-frequency = <20000000>;
107 spi-rx-bus-width = <4>; 109 spi-rx-bus-width = <4>;
108 spi-tx-bus-width = <1>; !! 110 spi-tx-bus-width = <4>;
109 reg = <0>; 111 reg = <0>;
110 }; 112 };
111 113
112 s25fs512s1: flash@1 { !! 114 qflash1: flash@1 {
113 compatible = "jedec,spi-nor"; !! 115 compatible = "spansion,m25p80";
114 #address-cells = <1>; 116 #address-cells = <1>;
115 #size-cells = <1>; 117 #size-cells = <1>;
116 spi-max-frequency = <50000000> !! 118 spi-max-frequency = <20000000>;
117 spi-rx-bus-width = <4>; 119 spi-rx-bus-width = <4>;
118 spi-tx-bus-width = <1>; !! 120 spi-tx-bus-width = <4>;
119 reg = <1>; 121 reg = <1>;
120 }; 122 };
121 }; 123 };
122 124
123 &usb1 { 125 &usb1 {
124 dr_mode = "otg"; 126 dr_mode = "otg";
125 }; 127 };
126 128
127 #include "fsl-ls1046-post.dtsi" 129 #include "fsl-ls1046-post.dtsi"
128 130
129 &fman0 { 131 &fman0 {
130 ethernet@e4000 { 132 ethernet@e4000 {
131 phy-handle = <&rgmii_phy1>; 133 phy-handle = <&rgmii_phy1>;
132 phy-connection-type = "rgmii-i 134 phy-connection-type = "rgmii-id";
133 }; 135 };
134 136
135 ethernet@e6000 { 137 ethernet@e6000 {
136 phy-handle = <&rgmii_phy2>; 138 phy-handle = <&rgmii_phy2>;
137 phy-connection-type = "rgmii-i 139 phy-connection-type = "rgmii-id";
138 }; 140 };
139 141
140 ethernet@e8000 { 142 ethernet@e8000 {
141 phy-handle = <&sgmii_phy1>; 143 phy-handle = <&sgmii_phy1>;
142 phy-connection-type = "sgmii"; 144 phy-connection-type = "sgmii";
143 }; 145 };
144 146
145 ethernet@ea000 { 147 ethernet@ea000 {
146 phy-handle = <&sgmii_phy2>; 148 phy-handle = <&sgmii_phy2>;
147 phy-connection-type = "sgmii"; 149 phy-connection-type = "sgmii";
148 }; 150 };
149 151
150 ethernet@f0000 { /* 10GEC1 */ 152 ethernet@f0000 { /* 10GEC1 */
151 phy-handle = <&aqr106_phy>; 153 phy-handle = <&aqr106_phy>;
152 phy-connection-type = "xgmii"; 154 phy-connection-type = "xgmii";
153 }; 155 };
154 156
155 ethernet@f2000 { /* 10GEC2 */ 157 ethernet@f2000 { /* 10GEC2 */
156 phy-connection-type = "10gbase !! 158 fixed-link = <0 1 1000 0 0>;
157 managed = "in-band-status"; !! 159 phy-connection-type = "xgmii";
158 }; 160 };
159 161
160 mdio@fc000 { 162 mdio@fc000 {
161 rgmii_phy1: ethernet-phy@1 { 163 rgmii_phy1: ethernet-phy@1 {
162 reg = <0x1>; 164 reg = <0x1>;
163 }; 165 };
164 166
165 rgmii_phy2: ethernet-phy@2 { 167 rgmii_phy2: ethernet-phy@2 {
166 reg = <0x2>; 168 reg = <0x2>;
167 }; 169 };
168 170
169 sgmii_phy1: ethernet-phy@3 { 171 sgmii_phy1: ethernet-phy@3 {
170 reg = <0x3>; 172 reg = <0x3>;
171 }; 173 };
172 174
173 sgmii_phy2: ethernet-phy@4 { 175 sgmii_phy2: ethernet-phy@4 {
174 reg = <0x4>; 176 reg = <0x4>;
175 }; 177 };
176 }; 178 };
177 179
178 mdio@fd000 { 180 mdio@fd000 {
179 aqr106_phy: ethernet-phy@0 { 181 aqr106_phy: ethernet-phy@0 {
180 compatible = "ethernet 182 compatible = "ethernet-phy-ieee802.3-c45";
181 interrupts = <0 131 4> 183 interrupts = <0 131 4>;
182 reg = <0x0>; 184 reg = <0x0>;
183 }; 185 };
184 }; 186 };
185 }; 187 };
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