1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for NXP Layerscape
4 *
5 * Copyright 2017-2020 NXP
6 *
7 * Harninder Rai <harninder.rai@nxp.com>
8 *
9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen
11 #include <dt-bindings/interrupt-controller/arm
12 #include <dt-bindings/thermal/thermal.h>
13
14 / {
15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 crypto = &crypto;
22 rtc1 = &ftm_alarm0;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 /* We have 2 clusters having 4
30 cpu0: cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cort
33 reg = <0x0>;
34 clocks = <&clockgen QO
35 cpu-idle-states = <&CP
36 #cooling-cells = <2>;
37 };
38
39 cpu1: cpu@1 {
40 device_type = "cpu";
41 compatible = "arm,cort
42 reg = <0x1>;
43 clocks = <&clockgen QO
44 cpu-idle-states = <&CP
45 #cooling-cells = <2>;
46 };
47
48 cpu2: cpu@2 {
49 device_type = "cpu";
50 compatible = "arm,cort
51 reg = <0x2>;
52 clocks = <&clockgen QO
53 cpu-idle-states = <&CP
54 #cooling-cells = <2>;
55 };
56
57 cpu3: cpu@3 {
58 device_type = "cpu";
59 compatible = "arm,cort
60 reg = <0x3>;
61 clocks = <&clockgen QO
62 cpu-idle-states = <&CP
63 #cooling-cells = <2>;
64 };
65
66 cpu4: cpu@100 {
67 device_type = "cpu";
68 compatible = "arm,cort
69 reg = <0x100>;
70 clocks = <&clockgen QO
71 cpu-idle-states = <&CP
72 #cooling-cells = <2>;
73 };
74
75 cpu5: cpu@101 {
76 device_type = "cpu";
77 compatible = "arm,cort
78 reg = <0x101>;
79 clocks = <&clockgen QO
80 cpu-idle-states = <&CP
81 #cooling-cells = <2>;
82 };
83
84 cpu6: cpu@102 {
85 device_type = "cpu";
86 compatible = "arm,cort
87 reg = <0x102>;
88 clocks = <&clockgen QO
89 cpu-idle-states = <&CP
90 #cooling-cells = <2>;
91 };
92
93 cpu7: cpu@103 {
94 device_type = "cpu";
95 compatible = "arm,cort
96 reg = <0x103>;
97 clocks = <&clockgen QO
98 cpu-idle-states = <&CP
99 #cooling-cells = <2>;
100 };
101
102 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle
104 idle-state-name = "PH2
105 arm,psci-suspend-param
106 entry-latency-us = <10
107 exit-latency-us = <100
108 min-residency-us = <30
109 };
110 };
111
112 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>;
115 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x1000
117 <0x0 0x06100000 0 0x1000
118 <0x0 0x0c0c0000 0 0x2000
119 <0x0 0x0c0d0000 0 0x1000
120 <0x0 0x0c0e0000 0 0x2000
121 interrupts = <GIC_PPI 9 IRQ_TY
122 #address-cells = <2>;
123 #size-cells = <2>;
124 ranges;
125
126 its: msi-controller@6020000 {
127 compatible = "arm,gic-
128 msi-controller;
129 #msi-cells = <1>;
130 reg = <0x0 0x6020000 0
131 };
132 };
133
134 thermal-zones {
135 cluster-thermal {
136 polling-delay-passive
137 polling-delay = <5000>
138 thermal-sensors = <&tm
139
140 trips {
141 core_cluster_a
142 temper
143 hyster
144 type =
145 };
146
147 core-cluster-c
148 temper
149 hyster
150 type =
151 };
152 };
153
154 cooling-maps {
155 map0 {
156 trip =
157 coolin
158
159
160
161
162
163
164
165
166 };
167 };
168 };
169
170 soc-thermal {
171 polling-delay-passive
172 polling-delay = <5000>
173 thermal-sensors = <&tm
174
175 trips {
176 soc-crit {
177 temper
178 hyster
179 type =
180 };
181 };
182 };
183 };
184
185 timer {
186 compatible = "arm,armv8-timer"
187 interrupts = <GIC_PPI 13 IRQ_T
188 <GIC_PPI 14 IRQ_T
189 <GIC_PPI 11 IRQ_T
190 <GIC_PPI 10 IRQ_T
191 };
192
193 pmu {
194 compatible = "arm,cortex-a53-p
195 interrupts = <GIC_PPI 7 IRQ_TY
196 };
197
198 psci {
199 compatible = "arm,psci-0.2";
200 method = "smc";
201 };
202
203 sysclk: sysclk {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <100000000>;
207 clock-output-names = "sysclk";
208 };
209
210 reboot {
211 compatible = "syscon-reboot";
212 regmap = <&reset>;
213 offset = <0x0>;
214 mask = <0x02>;
215 };
216
217 soc {
218 compatible = "simple-bus";
219 #address-cells = <2>;
220 #size-cells = <2>;
221 ranges;
222 dma-ranges = <0x0 0x0 0x0 0x0
223
224 clockgen: clocking@1300000 {
225 compatible = "fsl,ls10
226 reg = <0 0x1300000 0 0
227 #clock-cells = <2>;
228 clocks = <&sysclk>;
229 };
230
231 dcfg: dcfg@1e00000 {
232 compatible = "fsl,ls10
233 reg = <0x0 0x1e00000 0
234 little-endian;
235 };
236
237 reset: syscon@1e60000 {
238 compatible = "fsl,ls10
239 reg = <0x0 0x1e60000 0
240 };
241
242 isc: syscon@1f70000 {
243 compatible = "fsl,ls10
244 reg = <0x0 0x1f70000 0
245 little-endian;
246 #address-cells = <1>;
247 #size-cells = <1>;
248 ranges = <0x0 0x0 0x1f
249
250 extirq: interrupt-cont
251 compatible = "
252 #interrupt-cel
253 #address-cells
254 interrupt-cont
255 reg = <0x14 4>
256 interrupt-map
257 <0 0 &
258 <1 0 &
259 <2 0 &
260 <3 0 &
261 <4 0 &
262 <5 0 &
263 <6 0 &
264 <7 0 &
265 <8 0 &
266 <9 0 &
267 <10 0
268 <11 0
269 interrupt-map-
270 };
271 };
272
273 sfp: efuse@1e80000 {
274 compatible = "fsl,ls10
275 reg = <0x0 0x1e80000 0
276 clocks = <&clockgen QO
277 QO
278 clock-names = "sfp";
279 };
280
281 tmu: tmu@1f80000 {
282 compatible = "fsl,qori
283 reg = <0x0 0x1f80000 0
284 interrupts = <GIC_SPI
285 fsl,tmu-range = <0xb00
286 fsl,tmu-calibration =
287 /* Calibration
288 <0x00000000 0x
289 <0x00000001 0x
290 <0x00000002 0x
291 <0x00000003 0x
292 <0x00000004 0x
293 <0x00000005 0x
294 <0x00000006 0x
295 <0x00000007 0x
296 <0x00000008 0x
297 <0x00000009 0x
298 <0x0000000a 0x
299 <0x0000000b 0x
300 /* Calibration
301 <0x00010000 0x
302 <0x00010001 0x
303 <0x00010002 0x
304 <0x00010003 0x
305 <0x00010004 0x
306 <0x00010005 0x
307 <0x00010006 0x
308 <0x00010007 0x
309 <0x00010008 0x
310 <0x00010009 0x
311 /* Calibration
312 <0x00020000 0x
313 <0x00020001 0x
314 <0x00020002 0x
315 <0x00020003 0x
316 <0x00020004 0x
317 <0x00020005 0x
318 <0x00020006 0x
319 /* Calibration
320 <0x00030000 0x
321 <0x00030001 0x
322 <0x00030002 0x
323 <0x00030003 0x
324 <0x00030004 0x
325 <0x00030005 0x
326 <0x00030006 0x
327 <0x00030007 0x
328 little-endian;
329 #thermal-sensor-cells
330 };
331
332 dspi: spi@2100000 {
333 compatible = "fsl,ls10
334 "fsl,ls10
335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <0x0 0x2100000 0
338 interrupts = <GIC_SPI
339 clock-names = "dspi";
340 clocks = <&clockgen QO
341 QO
342 spi-num-chipselects =
343 status = "disabled";
344 };
345
346 duart0: serial@21c0500 {
347 compatible = "fsl,ns16
348 reg = <0x0 0x21c0500 0
349 clocks = <&clockgen QO
350 QO
351 interrupts = <GIC_SPI
352 status = "disabled";
353 };
354
355 duart1: serial@21c0600 {
356 compatible = "fsl,ns16
357 reg = <0x0 0x21c0600 0
358 clocks = <&clockgen QO
359 QO
360 interrupts = <GIC_SPI
361 status = "disabled";
362 };
363
364 gpio0: gpio@2300000 {
365 compatible = "fsl,ls10
366 reg = <0x0 0x2300000 0
367 interrupts = <GIC_SPI
368 little-endian;
369 gpio-controller;
370 #gpio-cells = <2>;
371 interrupt-controller;
372 #interrupt-cells = <2>
373 };
374
375 gpio1: gpio@2310000 {
376 compatible = "fsl,ls10
377 reg = <0x0 0x2310000 0
378 interrupts = <GIC_SPI
379 little-endian;
380 gpio-controller;
381 #gpio-cells = <2>;
382 interrupt-controller;
383 #interrupt-cells = <2>
384 };
385
386 gpio2: gpio@2320000 {
387 compatible = "fsl,ls10
388 reg = <0x0 0x2320000 0
389 interrupts = <GIC_SPI
390 little-endian;
391 gpio-controller;
392 #gpio-cells = <2>;
393 interrupt-controller;
394 #interrupt-cells = <2>
395 };
396
397 gpio3: gpio@2330000 {
398 compatible = "fsl,ls10
399 reg = <0x0 0x2330000 0
400 interrupts = <GIC_SPI
401 little-endian;
402 gpio-controller;
403 #gpio-cells = <2>;
404 interrupt-controller;
405 #interrupt-cells = <2>
406 };
407
408 ifc: memory-controller@2240000
409 compatible = "fsl,ifc"
410 reg = <0x0 0x2240000 0
411 interrupts = <GIC_SPI
412 little-endian;
413 #address-cells = <2>;
414 #size-cells = <1>;
415 status = "disabled";
416 };
417
418 i2c0: i2c@2000000 {
419 compatible = "fsl,vf61
420 #address-cells = <1>;
421 #size-cells = <0>;
422 reg = <0x0 0x2000000 0
423 interrupts = <GIC_SPI
424 clocks = <&clockgen QO
425 QO
426 status = "disabled";
427 };
428
429 i2c1: i2c@2010000 {
430 compatible = "fsl,vf61
431 #address-cells = <1>;
432 #size-cells = <0>;
433 reg = <0x0 0x2010000 0
434 interrupts = <GIC_SPI
435 clocks = <&clockgen QO
436 QO
437 status = "disabled";
438 };
439
440 i2c2: i2c@2020000 {
441 compatible = "fsl,vf61
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0x0 0x2020000 0
445 interrupts = <GIC_SPI
446 clocks = <&clockgen QO
447 QO
448 status = "disabled";
449 };
450
451 i2c3: i2c@2030000 {
452 compatible = "fsl,vf61
453 #address-cells = <1>;
454 #size-cells = <0>;
455 reg = <0x0 0x2030000 0
456 interrupts = <GIC_SPI
457 clocks = <&clockgen QO
458 QO
459 status = "disabled";
460 };
461
462 qspi: spi@20c0000 {
463 compatible = "fsl,ls20
464 #address-cells = <1>;
465 #size-cells = <0>;
466 reg = <0x0 0x20c0000 0
467 <0x0 0x20000000
468 reg-names = "QuadSPI",
469 interrupts = <GIC_SPI
470 clock-names = "qspi_en
471 clocks = <&clockgen QO
472 QO
473 <&clockgen QO
474 QO
475 status = "disabled";
476 };
477
478 esdhc: mmc@2140000 {
479 compatible = "fsl,ls10
480 reg = <0x0 0x2140000 0
481 interrupts = <GIC_SPI
482 clock-frequency = <0>;
483 clocks = <&clockgen QO
484 voltage-ranges = <1800
485 sdhci,auto-cmd12;
486 little-endian;
487 bus-width = <4>;
488 status = "disabled";
489 };
490
491 usb0: usb@3100000 {
492 compatible = "snps,dwc
493 reg = <0x0 0x3100000 0
494 interrupts = <GIC_SPI
495 dr_mode = "host";
496 snps,quirk-frame-lengt
497 snps,dis_rxdet_inp3_qu
498 snps,incr-burst-type-a
499 status = "disabled";
500 };
501
502 usb1: usb@3110000 {
503 compatible = "snps,dwc
504 reg = <0x0 0x3110000 0
505 interrupts = <GIC_SPI
506 dr_mode = "host";
507 snps,quirk-frame-lengt
508 snps,dis_rxdet_inp3_qu
509 snps,incr-burst-type-a
510 status = "disabled";
511 };
512
513 sata: sata@3200000 {
514 compatible = "fsl,ls10
515 reg = <0x0 0x3200000 0
516 <0x7 0x100520
517 reg-names = "ahci", "s
518 interrupts = <GIC_SPI
519 clocks = <&clockgen QO
520 QO
521 dma-coherent;
522 status = "disabled";
523 };
524
525 crypto: crypto@8000000 {
526 compatible = "fsl,sec-
527 fsl,sec-era = <8>;
528 #address-cells = <1>;
529 #size-cells = <1>;
530 ranges = <0x0 0x00 0x8
531 reg = <0x00 0x8000000
532 interrupts = <GIC_SPI
533 dma-coherent;
534
535 sec_jr0: jr@10000 {
536 compatible = "
537 "
538 reg = <0x10000
539 interrupts = <
540 };
541
542 sec_jr1: jr@20000 {
543 compatible = "
544 "
545 reg = <0x20000
546 interrupts = <
547 };
548
549 sec_jr2: jr@30000 {
550 compatible = "
551 "
552 reg = <0x30000
553 interrupts = <
554 };
555
556 sec_jr3: jr@40000 {
557 compatible = "
558 "
559 reg = <0x40000
560 interrupts = <
561 };
562 };
563
564 pcie1: pcie@3400000 {
565 compatible = "fsl,ls10
566 reg = <0x00 0x03400000
567 <0x20 0x00000000
568 reg-names = "regs", "c
569 interrupts = <GIC_SPI
570 interrupt-names = "aer
571 #address-cells = <3>;
572 #size-cells = <2>;
573 device_type = "pci";
574 dma-coherent;
575 num-viewport = <256>;
576 bus-range = <0x0 0xff>
577 ranges = <0x81000000 0
578 0x82000000 0
579 msi-parent = <&its 0>;
580 #interrupt-cells = <1>
581 interrupt-map-mask = <
582 interrupt-map = <0000
583 <0000
584 <0000
585 <0000
586 iommu-map = <0 &smmu 0
587 status = "disabled";
588 };
589
590 pcie_ep1: pcie-ep@3400000 {
591 compatible = "fsl,ls10
592 reg = <0x00 0x03400000
593 <0x20 0x00000000
594 reg-names = "regs", "a
595 interrupts = <GIC_SPI
596 interrupt-names = "pme
597 num-ib-windows = <24>;
598 num-ob-windows = <256>
599 max-functions = /bits/
600 status = "disabled";
601 };
602
603 pcie2: pcie@3500000 {
604 compatible = "fsl,ls10
605 reg = <0x00 0x03500000
606 <0x28 0x00000000
607 reg-names = "regs", "c
608 interrupts = <GIC_SPI
609 interrupt-names = "aer
610 #address-cells = <3>;
611 #size-cells = <2>;
612 device_type = "pci";
613 dma-coherent;
614 num-viewport = <6>;
615 bus-range = <0x0 0xff>
616 ranges = <0x81000000 0
617 0x82000000 0
618 msi-parent = <&its 0>;
619 #interrupt-cells = <1>
620 interrupt-map-mask = <
621 interrupt-map = <0000
622 <0000
623 <0000
624 <0000
625 iommu-map = <0 &smmu 0
626 status = "disabled";
627 };
628
629 pcie_ep2: pcie-ep@3500000 {
630 compatible = "fsl,ls10
631 reg = <0x00 0x03500000
632 <0x28 0x00000000
633 reg-names = "regs", "a
634 interrupts = <GIC_SPI
635 interrupt-names = "pme
636 num-ib-windows = <6>;
637 num-ob-windows = <6>;
638 status = "disabled";
639 };
640
641 pcie3: pcie@3600000 {
642 compatible = "fsl,ls10
643 reg = <0x00 0x03600000
644 <0x30 0x00000000
645 reg-names = "regs", "c
646 interrupts = <GIC_SPI
647 interrupt-names = "aer
648 #address-cells = <3>;
649 #size-cells = <2>;
650 device_type = "pci";
651 dma-coherent;
652 num-viewport = <6>;
653 bus-range = <0x0 0xff>
654 ranges = <0x81000000 0
655 0x82000000 0
656 msi-parent = <&its 0>;
657 #interrupt-cells = <1>
658 interrupt-map-mask = <
659 interrupt-map = <0000
660 <0000
661 <0000
662 <0000
663 iommu-map = <0 &smmu 0
664 status = "disabled";
665 };
666
667 pcie_ep3: pcie-ep@3600000 {
668 compatible = "fsl,ls10
669 reg = <0x00 0x03600000
670 <0x30 0x00000000
671 reg-names = "regs", "a
672 interrupts = <GIC_SPI
673 interrupt-names = "pme
674 num-ib-windows = <6>;
675 num-ob-windows = <6>;
676 status = "disabled";
677 };
678
679 smmu: iommu@5000000 {
680 compatible = "arm,mmu-
681 reg = <0 0x5000000 0 0
682 #iommu-cells = <1>;
683 stream-match-mask = <0
684 dma-coherent;
685 #global-interrupts = <
686 // global
687 interrupts = <GIC_SPI
688 // combin
689 <GIC_SPI
690 // global
691 <GIC_SPI
692 // combin
693 <GIC_SPI
694 // perfor
695 <GIC_SPI
696 <GIC_SPI
697 <GIC_SPI
698 <GIC_SPI
699 <GIC_SPI
700 <GIC_SPI
701 <GIC_SPI
702 <GIC_SPI
703 // per co
704 <GIC_SPI
705 <GIC_SPI
706 <GIC_SPI
707 <GIC_SPI
708 <GIC_SPI
709 <GIC_SPI
710 <GIC_SPI
711 <GIC_SPI
712 <GIC_SPI
713 <GIC_SPI
714 <GIC_SPI
715 <GIC_SPI
716 <GIC_SPI
717 <GIC_SPI
718 <GIC_SPI
719 <GIC_SPI
720 <GIC_SPI
721 <GIC_SPI
722 <GIC_SPI
723 <GIC_SPI
724 <GIC_SPI
725 <GIC_SPI
726 <GIC_SPI
727 <GIC_SPI
728 <GIC_SPI
729 <GIC_SPI
730 <GIC_SPI
731 <GIC_SPI
732 <GIC_SPI
733 <GIC_SPI
734 <GIC_SPI
735 <GIC_SPI
736 <GIC_SPI
737 <GIC_SPI
738 <GIC_SPI
739 <GIC_SPI
740 <GIC_SPI
741 <GIC_SPI
742 <GIC_SPI
743 <GIC_SPI
744 <GIC_SPI
745 <GIC_SPI
746 <GIC_SPI
747 <GIC_SPI
748 <GIC_SPI
749 <GIC_SPI
750 <GIC_SPI
751 <GIC_SPI
752 <GIC_SPI
753 <GIC_SPI
754 <GIC_SPI
755 <GIC_SPI
756 <GIC_SPI
757 <GIC_SPI
758 <GIC_SPI
759 <GIC_SPI
760 <GIC_SPI
761 <GIC_SPI
762 <GIC_SPI
763 <GIC_SPI
764 <GIC_SPI
765 <GIC_SPI
766 <GIC_SPI
767 <GIC_SPI
768 };
769
770 console@8340020 {
771 compatible = "fsl,dpaa
772 reg = <0x00000000 0x08
773 };
774
775 ptp-timer@8b95000 {
776 compatible = "fsl,dpaa
777 reg = <0x0 0x8b95000 0
778 clocks = <&clockgen QO
779 QO
780 little-endian;
781 fsl,extts-fifo;
782 };
783
784 emdio1: mdio@8b96000 {
785 compatible = "fsl,fman
786 reg = <0x0 0x8b96000 0
787 little-endian;
788 #address-cells = <1>;
789 #size-cells = <0>;
790 clock-frequency = <250
791 clocks = <&clockgen QO
792 QO
793 status = "disabled";
794 };
795
796 emdio2: mdio@8b97000 {
797 compatible = "fsl,fman
798 reg = <0x0 0x8b97000 0
799 little-endian;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 clock-frequency = <250
803 clocks = <&clockgen QO
804 QO
805 status = "disabled";
806 };
807
808 pcs_mdio1: mdio@8c07000 {
809 compatible = "fsl,fman
810 reg = <0x0 0x8c07000 0
811 little-endian;
812 #address-cells = <1>;
813 #size-cells = <0>;
814 status = "disabled";
815
816 pcs1: ethernet-phy@0 {
817 reg = <0>;
818 };
819 };
820
821 pcs_mdio2: mdio@8c0b000 {
822 compatible = "fsl,fman
823 reg = <0x0 0x8c0b000 0
824 little-endian;
825 #address-cells = <1>;
826 #size-cells = <0>;
827 status = "disabled";
828
829 pcs2: ethernet-phy@0 {
830 reg = <0>;
831 };
832 };
833
834 pcs_mdio3: mdio@8c0f000 {
835 compatible = "fsl,fman
836 reg = <0x0 0x8c0f000 0
837 little-endian;
838 #address-cells = <1>;
839 #size-cells = <0>;
840 status = "disabled";
841
842 pcs3_0: ethernet-phy@0
843 reg = <0>;
844 };
845
846 pcs3_1: ethernet-phy@1
847 reg = <1>;
848 };
849
850 pcs3_2: ethernet-phy@2
851 reg = <2>;
852 };
853
854 pcs3_3: ethernet-phy@3
855 reg = <3>;
856 };
857 };
858
859 pcs_mdio7: mdio@8c1f000 {
860 compatible = "fsl,fman
861 reg = <0x0 0x8c1f000 0
862 little-endian;
863 #address-cells = <1>;
864 #size-cells = <0>;
865 status = "disabled";
866
867 pcs7_0: ethernet-phy@0
868 reg = <0>;
869 };
870
871 pcs7_1: ethernet-phy@1
872 reg = <1>;
873 };
874
875 pcs7_2: ethernet-phy@2
876 reg = <2>;
877 };
878
879 pcs7_3: ethernet-phy@3
880 reg = <3>;
881 };
882 };
883
884 cluster1_core0_watchdog: watch
885 compatible = "arm,sp80
886 reg = <0x0 0xc000000 0
887 clocks = <&clockgen QO
888 QO
889 <&clockgen QO
890 QO
891 clock-names = "wdog_cl
892 };
893
894 cluster1_core1_watchdog: watch
895 compatible = "arm,sp80
896 reg = <0x0 0xc010000 0
897 clocks = <&clockgen QO
898 QO
899 <&clockgen QO
900 QO
901 clock-names = "wdog_cl
902 };
903
904 cluster1_core2_watchdog: watch
905 compatible = "arm,sp80
906 reg = <0x0 0xc020000 0
907 clocks = <&clockgen QO
908 QO
909 <&clockgen QO
910 QO
911 clock-names = "wdog_cl
912 };
913
914 cluster1_core3_watchdog: watch
915 compatible = "arm,sp80
916 reg = <0x0 0xc030000 0
917 clocks = <&clockgen QO
918 QO
919 <&clockgen QO
920 QO
921 clock-names = "wdog_cl
922 };
923
924 cluster2_core0_watchdog: watch
925 compatible = "arm,sp80
926 reg = <0x0 0xc100000 0
927 clocks = <&clockgen QO
928 QO
929 <&clockgen QO
930 QO
931 clock-names = "wdog_cl
932 };
933
934 cluster2_core1_watchdog: watch
935 compatible = "arm,sp80
936 reg = <0x0 0xc110000 0
937 clocks = <&clockgen QO
938 QO
939 <&clockgen QO
940 QO
941 clock-names = "wdog_cl
942 };
943
944 cluster2_core2_watchdog: watch
945 compatible = "arm,sp80
946 reg = <0x0 0xc120000 0
947 clocks = <&clockgen QO
948 QO
949 <&clockgen QO
950 QO
951 clock-names = "wdog_cl
952 };
953
954 cluster2_core3_watchdog: watch
955 compatible = "arm,sp80
956 reg = <0x0 0xc130000 0
957 clocks = <&clockgen QO
958 QO
959 <&clockgen QO
960 QO
961 clock-names = "wdog_cl
962 };
963
964 fsl_mc: fsl-mc@80c000000 {
965 compatible = "fsl,qori
966 reg = <0x00000008 0x0c
967 <0x00000000 0x08
968 msi-parent = <&its 0>;
969 iommu-map = <0 &smmu 0
970 dma-coherent;
971 #address-cells = <3>;
972 #size-cells = <1>;
973
974 /*
975 * Region type 0x0 - M
976 * Region type 0x1 - Q
977 */
978 ranges = <0x0 0x0 0x0
979 0x1 0x0 0x0
980
981 dpmacs {
982 #address-cells
983 #size-cells =
984
985 dpmac1: ethern
986 compat
987 reg =
988 };
989
990 dpmac2: ethern
991 compat
992 reg =
993 };
994
995 dpmac3: ethern
996 compat
997 reg =
998 };
999
1000 dpmac4: ether
1001 compa
1002 reg =
1003 };
1004
1005 dpmac5: ether
1006 compa
1007 reg =
1008 };
1009
1010 dpmac6: ether
1011 compa
1012 reg =
1013 };
1014
1015 dpmac7: ether
1016 compa
1017 reg =
1018 };
1019
1020 dpmac8: ether
1021 compa
1022 reg =
1023 };
1024
1025 dpmac9: ether
1026 compa
1027 reg =
1028 };
1029
1030 dpmac10: ethe
1031 compa
1032 reg =
1033 };
1034 };
1035 };
1036
1037 rcpm: wakeup-controller@1e340
1038 compatible = "fsl,ls1
1039 reg = <0x0 0x1e34040
1040 #fsl,rcpm-wakeup-cell
1041 little-endian;
1042 };
1043
1044 ftm_alarm0: rtc@2800000 {
1045 compatible = "fsl,ls1
1046 reg = <0x0 0x2800000
1047 fsl,rcpm-wakeup = <&r
1048 interrupts = <GIC_SPI
1049 };
1050 };
1051
1052 firmware {
1053 optee {
1054 compatible = "linaro,
1055 method = "smc";
1056 };
1057 };
1058 };
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