1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 * 4 *
5 * Copyright 2017-2020 NXP !! 5 * Copyright 2017 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
11 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
13 12
14 / { 13 / {
15 compatible = "fsl,ls1088a"; 14 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
17 #address-cells = <2>; 16 #address-cells = <2>;
18 #size-cells = <2>; 17 #size-cells = <2>;
19 18
20 aliases { 19 aliases {
21 crypto = &crypto; 20 crypto = &crypto;
22 rtc1 = &ftm_alarm0; <<
23 }; 21 };
24 22
25 cpus { 23 cpus {
26 #address-cells = <1>; 24 #address-cells = <1>;
27 #size-cells = <0>; 25 #size-cells = <0>;
28 26
29 /* We have 2 clusters having 4 27 /* We have 2 clusters having 4 Cortex-A53 cores each */
30 cpu0: cpu@0 { 28 cpu0: cpu@0 {
31 device_type = "cpu"; 29 device_type = "cpu";
32 compatible = "arm,cort 30 compatible = "arm,cortex-a53";
33 reg = <0x0>; 31 reg = <0x0>;
34 clocks = <&clockgen QO !! 32 clocks = <&clockgen 1 0>;
35 cpu-idle-states = <&CP 33 cpu-idle-states = <&CPU_PH20>;
36 #cooling-cells = <2>; 34 #cooling-cells = <2>;
37 }; 35 };
38 36
39 cpu1: cpu@1 { 37 cpu1: cpu@1 {
40 device_type = "cpu"; 38 device_type = "cpu";
41 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
42 reg = <0x1>; 40 reg = <0x1>;
43 clocks = <&clockgen QO !! 41 clocks = <&clockgen 1 0>;
44 cpu-idle-states = <&CP 42 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>; 43 #cooling-cells = <2>;
46 }; 44 };
47 45
48 cpu2: cpu@2 { 46 cpu2: cpu@2 {
49 device_type = "cpu"; 47 device_type = "cpu";
50 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
51 reg = <0x2>; 49 reg = <0x2>;
52 clocks = <&clockgen QO !! 50 clocks = <&clockgen 1 0>;
53 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_PH20>;
54 #cooling-cells = <2>; 52 #cooling-cells = <2>;
55 }; 53 };
56 54
57 cpu3: cpu@3 { 55 cpu3: cpu@3 {
58 device_type = "cpu"; 56 device_type = "cpu";
59 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
60 reg = <0x3>; 58 reg = <0x3>;
61 clocks = <&clockgen QO !! 59 clocks = <&clockgen 1 0>;
62 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_PH20>;
63 #cooling-cells = <2>; 61 #cooling-cells = <2>;
64 }; 62 };
65 63
66 cpu4: cpu@100 { 64 cpu4: cpu@100 {
67 device_type = "cpu"; 65 device_type = "cpu";
68 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
69 reg = <0x100>; 67 reg = <0x100>;
70 clocks = <&clockgen QO !! 68 clocks = <&clockgen 1 1>;
71 cpu-idle-states = <&CP 69 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 70 #cooling-cells = <2>;
73 }; 71 };
74 72
75 cpu5: cpu@101 { 73 cpu5: cpu@101 {
76 device_type = "cpu"; 74 device_type = "cpu";
77 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
78 reg = <0x101>; 76 reg = <0x101>;
79 clocks = <&clockgen QO !! 77 clocks = <&clockgen 1 1>;
80 cpu-idle-states = <&CP 78 cpu-idle-states = <&CPU_PH20>;
81 #cooling-cells = <2>; 79 #cooling-cells = <2>;
82 }; 80 };
83 81
84 cpu6: cpu@102 { 82 cpu6: cpu@102 {
85 device_type = "cpu"; 83 device_type = "cpu";
86 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
87 reg = <0x102>; 85 reg = <0x102>;
88 clocks = <&clockgen QO !! 86 clocks = <&clockgen 1 1>;
89 cpu-idle-states = <&CP 87 cpu-idle-states = <&CPU_PH20>;
90 #cooling-cells = <2>; 88 #cooling-cells = <2>;
91 }; 89 };
92 90
93 cpu7: cpu@103 { 91 cpu7: cpu@103 {
94 device_type = "cpu"; 92 device_type = "cpu";
95 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
96 reg = <0x103>; 94 reg = <0x103>;
97 clocks = <&clockgen QO !! 95 clocks = <&clockgen 1 1>;
98 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_PH20>;
99 #cooling-cells = <2>; 97 #cooling-cells = <2>;
100 }; 98 };
101 99
102 CPU_PH20: cpu-ph20 { 100 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle 101 compatible = "arm,idle-state";
104 idle-state-name = "PH2 102 idle-state-name = "PH20";
105 arm,psci-suspend-param 103 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <10 104 entry-latency-us = <1000>;
107 exit-latency-us = <100 105 exit-latency-us = <1000>;
108 min-residency-us = <30 106 min-residency-us = <3000>;
109 }; 107 };
110 }; 108 };
111 109
112 gic: interrupt-controller@6000000 { 110 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3"; 111 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>; 112 #interrupt-cells = <3>;
115 interrupt-controller; 113 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x1000 114 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x1000 115 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000 116 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000 117 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x2000 118 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <GIC_PPI 9 IRQ_TY !! 119 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>; 120 #address-cells = <2>;
123 #size-cells = <2>; 121 #size-cells = <2>;
124 ranges; 122 ranges;
125 123
126 its: msi-controller@6020000 { !! 124 its: gic-its@6020000 {
127 compatible = "arm,gic- 125 compatible = "arm,gic-v3-its";
128 msi-controller; 126 msi-controller;
129 #msi-cells = <1>; <<
130 reg = <0x0 0x6020000 0 127 reg = <0x0 0x6020000 0 0x20000>;
131 }; 128 };
132 }; 129 };
133 130
134 thermal-zones { 131 thermal-zones {
135 cluster-thermal { !! 132 cpu_thermal: cpu-thermal {
136 polling-delay-passive 133 polling-delay-passive = <1000>;
137 polling-delay = <5000> 134 polling-delay = <5000>;
138 thermal-sensors = <&tm 135 thermal-sensors = <&tmu 0>;
139 136
140 trips { 137 trips {
141 core_cluster_a !! 138 cpu_alert: cpu-alert {
142 temper 139 temperature = <85000>;
143 hyster 140 hysteresis = <2000>;
144 type = 141 type = "passive";
145 }; 142 };
146 143
147 core-cluster-c !! 144 cpu_crit: cpu-crit {
148 temper 145 temperature = <95000>;
149 hyster 146 hysteresis = <2000>;
150 type = 147 type = "critical";
151 }; 148 };
152 }; 149 };
153 150
154 cooling-maps { 151 cooling-maps {
155 map0 { 152 map0 {
156 trip = !! 153 trip = <&cpu_alert>;
157 coolin 154 cooling-device =
158 !! 155 <&cpu0 THERMAL_NO_LIMIT
159 !! 156 THERMAL_NO_LIMIT>;
160 <<
161 <<
162 <<
163 <<
164 <<
165 <<
166 }; 157 };
167 }; <<
168 }; <<
169 <<
170 soc-thermal { <<
171 polling-delay-passive <<
172 polling-delay = <5000> <<
173 thermal-sensors = <&tm <<
174 158
175 trips { !! 159 map1 {
176 soc-crit { !! 160 trip = <&cpu_alert>;
177 temper !! 161 cooling-device =
178 hyster !! 162 <&cpu4 THERMAL_NO_LIMIT
179 type = !! 163 THERMAL_NO_LIMIT>;
180 }; 164 };
181 }; 165 };
182 }; 166 };
183 }; 167 };
184 168
185 timer { 169 timer {
186 compatible = "arm,armv8-timer" 170 compatible = "arm,armv8-timer";
187 interrupts = <GIC_PPI 13 IRQ_T !! 171 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
188 <GIC_PPI 14 IRQ_T !! 172 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
189 <GIC_PPI 11 IRQ_T !! 173 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
190 <GIC_PPI 10 IRQ_T !! 174 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
191 }; 175 };
192 176
193 pmu { !! 177 fsl_mc: fsl-mc@80c000000 {
194 compatible = "arm,cortex-a53-p !! 178 compatible = "fsl,qoriq-mc";
195 interrupts = <GIC_PPI 7 IRQ_TY !! 179 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
>> 180 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
>> 181 msi-parent = <&its>;
>> 182 #address-cells = <3>;
>> 183 #size-cells = <1>;
>> 184
>> 185 /*
>> 186 * Region type 0x0 - MC portals
>> 187 * Region type 0x1 - QBMAN portals
>> 188 */
>> 189 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
>> 190 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
>> 191
>> 192 dpmacs {
>> 193 #address-cells = <1>;
>> 194 #size-cells = <0>;
>> 195
>> 196 dpmac1: dpmac@1 {
>> 197 compatible = "fsl,qoriq-mc-dpmac";
>> 198 reg = <1>;
>> 199 };
>> 200
>> 201 dpmac2: dpmac@2 {
>> 202 compatible = "fsl,qoriq-mc-dpmac";
>> 203 reg = <2>;
>> 204 };
>> 205
>> 206 dpmac3: dpmac@3 {
>> 207 compatible = "fsl,qoriq-mc-dpmac";
>> 208 reg = <3>;
>> 209 };
>> 210
>> 211 dpmac4: dpmac@4 {
>> 212 compatible = "fsl,qoriq-mc-dpmac";
>> 213 reg = <4>;
>> 214 };
>> 215
>> 216 dpmac5: dpmac@5 {
>> 217 compatible = "fsl,qoriq-mc-dpmac";
>> 218 reg = <5>;
>> 219 };
>> 220
>> 221 dpmac6: dpmac@6 {
>> 222 compatible = "fsl,qoriq-mc-dpmac";
>> 223 reg = <6>;
>> 224 };
>> 225
>> 226 dpmac7: dpmac@7 {
>> 227 compatible = "fsl,qoriq-mc-dpmac";
>> 228 reg = <7>;
>> 229 };
>> 230
>> 231 dpmac8: dpmac@8 {
>> 232 compatible = "fsl,qoriq-mc-dpmac";
>> 233 reg = <8>;
>> 234 };
>> 235
>> 236 dpmac9: dpmac@9 {
>> 237 compatible = "fsl,qoriq-mc-dpmac";
>> 238 reg = <9>;
>> 239 };
>> 240
>> 241 dpmac10: dpmac@a {
>> 242 compatible = "fsl,qoriq-mc-dpmac";
>> 243 reg = <0xa>;
>> 244 };
>> 245 };
196 }; 246 };
197 247
198 psci { 248 psci {
199 compatible = "arm,psci-0.2"; 249 compatible = "arm,psci-0.2";
200 method = "smc"; 250 method = "smc";
201 }; 251 };
202 252
203 sysclk: sysclk { 253 sysclk: sysclk {
204 compatible = "fixed-clock"; 254 compatible = "fixed-clock";
205 #clock-cells = <0>; 255 #clock-cells = <0>;
206 clock-frequency = <100000000>; 256 clock-frequency = <100000000>;
207 clock-output-names = "sysclk"; 257 clock-output-names = "sysclk";
208 }; 258 };
209 259
210 reboot { <<
211 compatible = "syscon-reboot"; <<
212 regmap = <&reset>; <<
213 offset = <0x0>; <<
214 mask = <0x02>; <<
215 }; <<
216 <<
217 soc { 260 soc {
218 compatible = "simple-bus"; 261 compatible = "simple-bus";
219 #address-cells = <2>; 262 #address-cells = <2>;
220 #size-cells = <2>; 263 #size-cells = <2>;
221 ranges; 264 ranges;
222 dma-ranges = <0x0 0x0 0x0 0x0 <<
223 265
224 clockgen: clocking@1300000 { 266 clockgen: clocking@1300000 {
225 compatible = "fsl,ls10 267 compatible = "fsl,ls1088a-clockgen";
226 reg = <0 0x1300000 0 0 268 reg = <0 0x1300000 0 0xa0000>;
227 #clock-cells = <2>; 269 #clock-cells = <2>;
228 clocks = <&sysclk>; 270 clocks = <&sysclk>;
229 }; 271 };
230 272
231 dcfg: dcfg@1e00000 { 273 dcfg: dcfg@1e00000 {
232 compatible = "fsl,ls10 274 compatible = "fsl,ls1088a-dcfg", "syscon";
233 reg = <0x0 0x1e00000 0 275 reg = <0x0 0x1e00000 0x0 0x10000>;
234 little-endian; 276 little-endian;
235 }; 277 };
236 278
237 reset: syscon@1e60000 { <<
238 compatible = "fsl,ls10 <<
239 reg = <0x0 0x1e60000 0 <<
240 }; <<
241 <<
242 isc: syscon@1f70000 { <<
243 compatible = "fsl,ls10 <<
244 reg = <0x0 0x1f70000 0 <<
245 little-endian; <<
246 #address-cells = <1>; <<
247 #size-cells = <1>; <<
248 ranges = <0x0 0x0 0x1f <<
249 <<
250 extirq: interrupt-cont <<
251 compatible = " <<
252 #interrupt-cel <<
253 #address-cells <<
254 interrupt-cont <<
255 reg = <0x14 4> <<
256 interrupt-map <<
257 <0 0 & <<
258 <1 0 & <<
259 <2 0 & <<
260 <3 0 & <<
261 <4 0 & <<
262 <5 0 & <<
263 <6 0 & <<
264 <7 0 & <<
265 <8 0 & <<
266 <9 0 & <<
267 <10 0 <<
268 <11 0 <<
269 interrupt-map- <<
270 }; <<
271 }; <<
272 <<
273 sfp: efuse@1e80000 { <<
274 compatible = "fsl,ls10 <<
275 reg = <0x0 0x1e80000 0 <<
276 clocks = <&clockgen QO <<
277 QO <<
278 clock-names = "sfp"; <<
279 }; <<
280 <<
281 tmu: tmu@1f80000 { 279 tmu: tmu@1f80000 {
282 compatible = "fsl,qori 280 compatible = "fsl,qoriq-tmu";
283 reg = <0x0 0x1f80000 0 281 reg = <0x0 0x1f80000 0x0 0x10000>;
284 interrupts = <GIC_SPI !! 282 interrupts = <0 23 0x4>;
285 fsl,tmu-range = <0xb00 !! 283 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
286 fsl,tmu-calibration = 284 fsl,tmu-calibration =
287 /* Calibration 285 /* Calibration data group 1 */
288 <0x00000000 0x !! 286 <0x00000000 0x00000026
289 <0x00000001 0x !! 287 0x00000001 0x0000002d
290 <0x00000002 0x !! 288 0x00000002 0x00000032
291 <0x00000003 0x !! 289 0x00000003 0x00000039
292 <0x00000004 0x !! 290 0x00000004 0x0000003f
293 <0x00000005 0x !! 291 0x00000005 0x00000046
294 <0x00000006 0x !! 292 0x00000006 0x0000004d
295 <0x00000007 0x !! 293 0x00000007 0x00000054
296 <0x00000008 0x !! 294 0x00000008 0x0000005a
297 <0x00000009 0x !! 295 0x00000009 0x00000061
298 <0x0000000a 0x !! 296 0x0000000a 0x0000006a
299 <0x0000000b 0x !! 297 0x0000000b 0x00000071
300 /* Calibration 298 /* Calibration data group 2 */
301 <0x00010000 0x !! 299 0x00010000 0x00000025
302 <0x00010001 0x !! 300 0x00010001 0x0000002c
303 <0x00010002 0x !! 301 0x00010002 0x00000035
304 <0x00010003 0x !! 302 0x00010003 0x0000003d
305 <0x00010004 0x !! 303 0x00010004 0x00000045
306 <0x00010005 0x !! 304 0x00010005 0x0000004e
307 <0x00010006 0x !! 305 0x00010006 0x00000057
308 <0x00010007 0x !! 306 0x00010007 0x00000061
309 <0x00010008 0x !! 307 0x00010008 0x0000006b
310 <0x00010009 0x !! 308 0x00010009 0x00000076
311 /* Calibration 309 /* Calibration data group 3 */
312 <0x00020000 0x !! 310 0x00020000 0x00000029
313 <0x00020001 0x !! 311 0x00020001 0x00000033
314 <0x00020002 0x !! 312 0x00020002 0x0000003d
315 <0x00020003 0x !! 313 0x00020003 0x00000049
316 <0x00020004 0x !! 314 0x00020004 0x00000056
317 <0x00020005 0x !! 315 0x00020005 0x00000061
318 <0x00020006 0x !! 316 0x00020006 0x0000006d
319 /* Calibration 317 /* Calibration data group 4 */
320 <0x00030000 0x !! 318 0x00030000 0x00000021
321 <0x00030001 0x !! 319 0x00030001 0x0000002a
322 <0x00030002 0x !! 320 0x00030002 0x0000003c
323 <0x00030003 0x !! 321 0x00030003 0x0000004e>;
324 <0x00030004 0x <<
325 <0x00030005 0x <<
326 <0x00030006 0x <<
327 <0x00030007 0x <<
328 little-endian; 322 little-endian;
329 #thermal-sensor-cells 323 #thermal-sensor-cells = <1>;
330 }; 324 };
331 325
332 dspi: spi@2100000 { <<
333 compatible = "fsl,ls10 <<
334 "fsl,ls10 <<
335 #address-cells = <1>; <<
336 #size-cells = <0>; <<
337 reg = <0x0 0x2100000 0 <<
338 interrupts = <GIC_SPI <<
339 clock-names = "dspi"; <<
340 clocks = <&clockgen QO <<
341 QO <<
342 spi-num-chipselects = <<
343 status = "disabled"; <<
344 }; <<
345 <<
346 duart0: serial@21c0500 { 326 duart0: serial@21c0500 {
347 compatible = "fsl,ns16 327 compatible = "fsl,ns16550", "ns16550a";
348 reg = <0x0 0x21c0500 0 328 reg = <0x0 0x21c0500 0x0 0x100>;
349 clocks = <&clockgen QO !! 329 clocks = <&clockgen 4 3>;
350 QO !! 330 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
351 interrupts = <GIC_SPI <<
352 status = "disabled"; 331 status = "disabled";
353 }; 332 };
354 333
355 duart1: serial@21c0600 { 334 duart1: serial@21c0600 {
356 compatible = "fsl,ns16 335 compatible = "fsl,ns16550", "ns16550a";
357 reg = <0x0 0x21c0600 0 336 reg = <0x0 0x21c0600 0x0 0x100>;
358 clocks = <&clockgen QO !! 337 clocks = <&clockgen 4 3>;
359 QO !! 338 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
360 interrupts = <GIC_SPI <<
361 status = "disabled"; 339 status = "disabled";
362 }; 340 };
363 341
364 gpio0: gpio@2300000 { 342 gpio0: gpio@2300000 {
365 compatible = "fsl,ls10 !! 343 compatible = "fsl,qoriq-gpio";
366 reg = <0x0 0x2300000 0 344 reg = <0x0 0x2300000 0x0 0x10000>;
367 interrupts = <GIC_SPI !! 345 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
368 little-endian; <<
369 gpio-controller; 346 gpio-controller;
370 #gpio-cells = <2>; 347 #gpio-cells = <2>;
371 interrupt-controller; 348 interrupt-controller;
372 #interrupt-cells = <2> 349 #interrupt-cells = <2>;
373 }; 350 };
374 351
375 gpio1: gpio@2310000 { 352 gpio1: gpio@2310000 {
376 compatible = "fsl,ls10 !! 353 compatible = "fsl,qoriq-gpio";
377 reg = <0x0 0x2310000 0 354 reg = <0x0 0x2310000 0x0 0x10000>;
378 interrupts = <GIC_SPI !! 355 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
379 little-endian; <<
380 gpio-controller; 356 gpio-controller;
381 #gpio-cells = <2>; 357 #gpio-cells = <2>;
382 interrupt-controller; 358 interrupt-controller;
383 #interrupt-cells = <2> 359 #interrupt-cells = <2>;
384 }; 360 };
385 361
386 gpio2: gpio@2320000 { 362 gpio2: gpio@2320000 {
387 compatible = "fsl,ls10 !! 363 compatible = "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0 364 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI !! 365 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
390 little-endian; <<
391 gpio-controller; 366 gpio-controller;
392 #gpio-cells = <2>; 367 #gpio-cells = <2>;
393 interrupt-controller; 368 interrupt-controller;
394 #interrupt-cells = <2> 369 #interrupt-cells = <2>;
395 }; 370 };
396 371
397 gpio3: gpio@2330000 { 372 gpio3: gpio@2330000 {
398 compatible = "fsl,ls10 !! 373 compatible = "fsl,qoriq-gpio";
399 reg = <0x0 0x2330000 0 374 reg = <0x0 0x2330000 0x0 0x10000>;
400 interrupts = <GIC_SPI !! 375 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
401 little-endian; <<
402 gpio-controller; 376 gpio-controller;
403 #gpio-cells = <2>; 377 #gpio-cells = <2>;
404 interrupt-controller; 378 interrupt-controller;
405 #interrupt-cells = <2> 379 #interrupt-cells = <2>;
406 }; 380 };
407 381
408 ifc: memory-controller@2240000 !! 382 ifc: ifc@2240000 {
409 compatible = "fsl,ifc" !! 383 compatible = "fsl,ifc", "simple-bus";
410 reg = <0x0 0x2240000 0 384 reg = <0x0 0x2240000 0x0 0x20000>;
411 interrupts = <GIC_SPI !! 385 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
412 little-endian; 386 little-endian;
413 #address-cells = <2>; 387 #address-cells = <2>;
414 #size-cells = <1>; 388 #size-cells = <1>;
415 status = "disabled"; 389 status = "disabled";
416 }; 390 };
417 391
418 i2c0: i2c@2000000 { 392 i2c0: i2c@2000000 {
419 compatible = "fsl,vf61 393 compatible = "fsl,vf610-i2c";
420 #address-cells = <1>; 394 #address-cells = <1>;
421 #size-cells = <0>; 395 #size-cells = <0>;
422 reg = <0x0 0x2000000 0 396 reg = <0x0 0x2000000 0x0 0x10000>;
423 interrupts = <GIC_SPI !! 397 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen QO !! 398 clocks = <&clockgen 4 3>;
425 QO <<
426 status = "disabled"; 399 status = "disabled";
427 }; 400 };
428 401
429 i2c1: i2c@2010000 { 402 i2c1: i2c@2010000 {
430 compatible = "fsl,vf61 403 compatible = "fsl,vf610-i2c";
431 #address-cells = <1>; 404 #address-cells = <1>;
432 #size-cells = <0>; 405 #size-cells = <0>;
433 reg = <0x0 0x2010000 0 406 reg = <0x0 0x2010000 0x0 0x10000>;
434 interrupts = <GIC_SPI !! 407 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clockgen QO !! 408 clocks = <&clockgen 4 3>;
436 QO <<
437 status = "disabled"; 409 status = "disabled";
438 }; 410 };
439 411
440 i2c2: i2c@2020000 { 412 i2c2: i2c@2020000 {
441 compatible = "fsl,vf61 413 compatible = "fsl,vf610-i2c";
442 #address-cells = <1>; 414 #address-cells = <1>;
443 #size-cells = <0>; 415 #size-cells = <0>;
444 reg = <0x0 0x2020000 0 416 reg = <0x0 0x2020000 0x0 0x10000>;
445 interrupts = <GIC_SPI !! 417 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen QO !! 418 clocks = <&clockgen 4 3>;
447 QO <<
448 status = "disabled"; 419 status = "disabled";
449 }; 420 };
450 421
451 i2c3: i2c@2030000 { 422 i2c3: i2c@2030000 {
452 compatible = "fsl,vf61 423 compatible = "fsl,vf610-i2c";
453 #address-cells = <1>; 424 #address-cells = <1>;
454 #size-cells = <0>; 425 #size-cells = <0>;
455 reg = <0x0 0x2030000 0 426 reg = <0x0 0x2030000 0x0 0x10000>;
456 interrupts = <GIC_SPI !! 427 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clockgen QO !! 428 clocks = <&clockgen 4 3>;
458 QO <<
459 status = "disabled"; 429 status = "disabled";
460 }; 430 };
461 431
462 qspi: spi@20c0000 { !! 432 esdhc: esdhc@2140000 {
463 compatible = "fsl,ls20 <<
464 #address-cells = <1>; <<
465 #size-cells = <0>; <<
466 reg = <0x0 0x20c0000 0 <<
467 <0x0 0x20000000 <<
468 reg-names = "QuadSPI", <<
469 interrupts = <GIC_SPI <<
470 clock-names = "qspi_en <<
471 clocks = <&clockgen QO <<
472 QO <<
473 <&clockgen QO <<
474 QO <<
475 status = "disabled"; <<
476 }; <<
477 <<
478 esdhc: mmc@2140000 { <<
479 compatible = "fsl,ls10 433 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
480 reg = <0x0 0x2140000 0 434 reg = <0x0 0x2140000 0x0 0x10000>;
481 interrupts = <GIC_SPI !! 435 interrupts = <0 28 0x4>; /* Level high type */
482 clock-frequency = <0>; 436 clock-frequency = <0>;
483 clocks = <&clockgen QO <<
484 voltage-ranges = <1800 437 voltage-ranges = <1800 1800 3300 3300>;
485 sdhci,auto-cmd12; 438 sdhci,auto-cmd12;
486 little-endian; 439 little-endian;
487 bus-width = <4>; 440 bus-width = <4>;
488 status = "disabled"; 441 status = "disabled";
489 }; 442 };
490 443
491 usb0: usb@3100000 { !! 444 usb0: usb3@3100000 {
492 compatible = "snps,dwc 445 compatible = "snps,dwc3";
493 reg = <0x0 0x3100000 0 446 reg = <0x0 0x3100000 0x0 0x10000>;
494 interrupts = <GIC_SPI !! 447 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 dr_mode = "host"; 448 dr_mode = "host";
496 snps,quirk-frame-lengt 449 snps,quirk-frame-length-adjustment = <0x20>;
497 snps,dis_rxdet_inp3_qu 450 snps,dis_rxdet_inp3_quirk;
498 snps,incr-burst-type-a <<
499 status = "disabled"; 451 status = "disabled";
500 }; 452 };
501 453
502 usb1: usb@3110000 { !! 454 usb1: usb3@3110000 {
503 compatible = "snps,dwc 455 compatible = "snps,dwc3";
504 reg = <0x0 0x3110000 0 456 reg = <0x0 0x3110000 0x0 0x10000>;
505 interrupts = <GIC_SPI !! 457 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 dr_mode = "host"; 458 dr_mode = "host";
507 snps,quirk-frame-lengt 459 snps,quirk-frame-length-adjustment = <0x20>;
508 snps,dis_rxdet_inp3_qu 460 snps,dis_rxdet_inp3_quirk;
509 snps,incr-burst-type-a <<
510 status = "disabled"; 461 status = "disabled";
511 }; 462 };
512 463
513 sata: sata@3200000 { 464 sata: sata@3200000 {
514 compatible = "fsl,ls10 465 compatible = "fsl,ls1088a-ahci";
515 reg = <0x0 0x3200000 0 466 reg = <0x0 0x3200000 0x0 0x10000>,
516 <0x7 0x100520 467 <0x7 0x100520 0x0 0x4>;
517 reg-names = "ahci", "s 468 reg-names = "ahci", "sata-ecc";
518 interrupts = <GIC_SPI !! 469 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clockgen QO !! 470 clocks = <&clockgen 4 3>;
520 QO <<
521 dma-coherent; 471 dma-coherent;
522 status = "disabled"; 472 status = "disabled";
523 }; 473 };
524 474
525 crypto: crypto@8000000 { 475 crypto: crypto@8000000 {
526 compatible = "fsl,sec- 476 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
527 fsl,sec-era = <8>; 477 fsl,sec-era = <8>;
528 #address-cells = <1>; 478 #address-cells = <1>;
529 #size-cells = <1>; 479 #size-cells = <1>;
530 ranges = <0x0 0x00 0x8 480 ranges = <0x0 0x00 0x8000000 0x100000>;
531 reg = <0x00 0x8000000 481 reg = <0x00 0x8000000 0x0 0x100000>;
532 interrupts = <GIC_SPI 482 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
533 dma-coherent; 483 dma-coherent;
534 484
535 sec_jr0: jr@10000 { 485 sec_jr0: jr@10000 {
536 compatible = " 486 compatible = "fsl,sec-v5.0-job-ring",
537 " 487 "fsl,sec-v4.0-job-ring";
538 reg = <0x10000 !! 488 reg = <0x10000 0x10000>;
539 interrupts = < 489 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
540 }; 490 };
541 491
542 sec_jr1: jr@20000 { 492 sec_jr1: jr@20000 {
543 compatible = " 493 compatible = "fsl,sec-v5.0-job-ring",
544 " 494 "fsl,sec-v4.0-job-ring";
545 reg = <0x20000 !! 495 reg = <0x20000 0x10000>;
546 interrupts = < 496 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
547 }; 497 };
548 498
549 sec_jr2: jr@30000 { 499 sec_jr2: jr@30000 {
550 compatible = " 500 compatible = "fsl,sec-v5.0-job-ring",
551 " 501 "fsl,sec-v4.0-job-ring";
552 reg = <0x30000 !! 502 reg = <0x30000 0x10000>;
553 interrupts = < 503 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
554 }; 504 };
555 505
556 sec_jr3: jr@40000 { 506 sec_jr3: jr@40000 {
557 compatible = " 507 compatible = "fsl,sec-v5.0-job-ring",
558 " 508 "fsl,sec-v4.0-job-ring";
559 reg = <0x40000 !! 509 reg = <0x40000 0x10000>;
560 interrupts = < 510 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
561 }; 511 };
562 }; 512 };
563 513
564 pcie1: pcie@3400000 { !! 514 pcie@3400000 {
565 compatible = "fsl,ls10 !! 515 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
566 reg = <0x00 0x03400000 !! 516 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
567 <0x20 0x00000000 !! 517 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
568 reg-names = "regs", "c 518 reg-names = "regs", "config";
569 interrupts = <GIC_SPI !! 519 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
570 interrupt-names = "aer 520 interrupt-names = "aer";
571 #address-cells = <3>; 521 #address-cells = <3>;
572 #size-cells = <2>; 522 #size-cells = <2>;
573 device_type = "pci"; 523 device_type = "pci";
574 dma-coherent; 524 dma-coherent;
575 num-viewport = <256>; !! 525 num-lanes = <4>;
576 bus-range = <0x0 0xff> 526 bus-range = <0x0 0xff>;
577 ranges = <0x81000000 0 527 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
578 0x82000000 0 528 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
579 msi-parent = <&its 0>; !! 529 msi-parent = <&its>;
580 #interrupt-cells = <1> 530 #interrupt-cells = <1>;
581 interrupt-map-mask = < 531 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0000 532 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 533 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 534 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
585 <0000 535 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
586 iommu-map = <0 &smmu 0 <<
587 status = "disabled"; <<
588 }; 536 };
589 537
590 pcie_ep1: pcie-ep@3400000 { !! 538 pcie@3500000 {
591 compatible = "fsl,ls10 !! 539 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
592 reg = <0x00 0x03400000 !! 540 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
593 <0x20 0x00000000 !! 541 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
594 reg-names = "regs", "a <<
595 interrupts = <GIC_SPI <<
596 interrupt-names = "pme <<
597 num-ib-windows = <24>; <<
598 num-ob-windows = <256> <<
599 max-functions = /bits/ <<
600 status = "disabled"; <<
601 }; <<
602 <<
603 pcie2: pcie@3500000 { <<
604 compatible = "fsl,ls10 <<
605 reg = <0x00 0x03500000 <<
606 <0x28 0x00000000 <<
607 reg-names = "regs", "c 542 reg-names = "regs", "config";
608 interrupts = <GIC_SPI !! 543 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
609 interrupt-names = "aer 544 interrupt-names = "aer";
610 #address-cells = <3>; 545 #address-cells = <3>;
611 #size-cells = <2>; 546 #size-cells = <2>;
612 device_type = "pci"; 547 device_type = "pci";
613 dma-coherent; 548 dma-coherent;
614 num-viewport = <6>; !! 549 num-lanes = <4>;
615 bus-range = <0x0 0xff> 550 bus-range = <0x0 0xff>;
616 ranges = <0x81000000 0 551 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
617 0x82000000 0 552 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
618 msi-parent = <&its 0>; !! 553 msi-parent = <&its>;
619 #interrupt-cells = <1> 554 #interrupt-cells = <1>;
620 interrupt-map-mask = < 555 interrupt-map-mask = <0 0 0 7>;
621 interrupt-map = <0000 556 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 557 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 558 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
624 <0000 559 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
625 iommu-map = <0 &smmu 0 <<
626 status = "disabled"; <<
627 }; 560 };
628 561
629 pcie_ep2: pcie-ep@3500000 { !! 562 pcie@3600000 {
630 compatible = "fsl,ls10 !! 563 compatible = "fsl,ls1088a-pcie", "snps,dw-pcie";
631 reg = <0x00 0x03500000 !! 564 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
632 <0x28 0x00000000 !! 565 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
633 reg-names = "regs", "a <<
634 interrupts = <GIC_SPI <<
635 interrupt-names = "pme <<
636 num-ib-windows = <6>; <<
637 num-ob-windows = <6>; <<
638 status = "disabled"; <<
639 }; <<
640 <<
641 pcie3: pcie@3600000 { <<
642 compatible = "fsl,ls10 <<
643 reg = <0x00 0x03600000 <<
644 <0x30 0x00000000 <<
645 reg-names = "regs", "c 566 reg-names = "regs", "config";
646 interrupts = <GIC_SPI !! 567 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
647 interrupt-names = "aer 568 interrupt-names = "aer";
648 #address-cells = <3>; 569 #address-cells = <3>;
649 #size-cells = <2>; 570 #size-cells = <2>;
650 device_type = "pci"; 571 device_type = "pci";
651 dma-coherent; 572 dma-coherent;
652 num-viewport = <6>; !! 573 num-lanes = <8>;
653 bus-range = <0x0 0xff> 574 bus-range = <0x0 0xff>;
654 ranges = <0x81000000 0 575 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
655 0x82000000 0 576 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
656 msi-parent = <&its 0>; !! 577 msi-parent = <&its>;
657 #interrupt-cells = <1> 578 #interrupt-cells = <1>;
658 interrupt-map-mask = < 579 interrupt-map-mask = <0 0 0 7>;
659 interrupt-map = <0000 580 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 581 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 582 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
662 <0000 583 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
663 iommu-map = <0 &smmu 0 <<
664 status = "disabled"; <<
665 }; <<
666 <<
667 pcie_ep3: pcie-ep@3600000 { <<
668 compatible = "fsl,ls10 <<
669 reg = <0x00 0x03600000 <<
670 <0x30 0x00000000 <<
671 reg-names = "regs", "a <<
672 interrupts = <GIC_SPI <<
673 interrupt-names = "pme <<
674 num-ib-windows = <6>; <<
675 num-ob-windows = <6>; <<
676 status = "disabled"; <<
677 }; 584 };
678 585
679 smmu: iommu@5000000 { !! 586 cluster1_core0_watchdog: wdt@c000000 {
680 compatible = "arm,mmu- <<
681 reg = <0 0x5000000 0 0 <<
682 #iommu-cells = <1>; <<
683 stream-match-mask = <0 <<
684 dma-coherent; <<
685 #global-interrupts = < <<
686 // global <<
687 interrupts = <GIC_SPI <<
688 // combin <<
689 <GIC_SPI <<
690 // global <<
691 <GIC_SPI <<
692 // combin <<
693 <GIC_SPI <<
694 // perfor <<
695 <GIC_SPI <<
696 <GIC_SPI <<
697 <GIC_SPI <<
698 <GIC_SPI <<
699 <GIC_SPI <<
700 <GIC_SPI <<
701 <GIC_SPI <<
702 <GIC_SPI <<
703 // per co <<
704 <GIC_SPI <<
705 <GIC_SPI <<
706 <GIC_SPI <<
707 <GIC_SPI <<
708 <GIC_SPI <<
709 <GIC_SPI <<
710 <GIC_SPI <<
711 <GIC_SPI <<
712 <GIC_SPI <<
713 <GIC_SPI <<
714 <GIC_SPI <<
715 <GIC_SPI <<
716 <GIC_SPI <<
717 <GIC_SPI <<
718 <GIC_SPI <<
719 <GIC_SPI <<
720 <GIC_SPI <<
721 <GIC_SPI <<
722 <GIC_SPI <<
723 <GIC_SPI <<
724 <GIC_SPI <<
725 <GIC_SPI <<
726 <GIC_SPI <<
727 <GIC_SPI <<
728 <GIC_SPI <<
729 <GIC_SPI <<
730 <GIC_SPI <<
731 <GIC_SPI <<
732 <GIC_SPI <<
733 <GIC_SPI <<
734 <GIC_SPI <<
735 <GIC_SPI <<
736 <GIC_SPI <<
737 <GIC_SPI <<
738 <GIC_SPI <<
739 <GIC_SPI <<
740 <GIC_SPI <<
741 <GIC_SPI <<
742 <GIC_SPI <<
743 <GIC_SPI <<
744 <GIC_SPI <<
745 <GIC_SPI <<
746 <GIC_SPI <<
747 <GIC_SPI <<
748 <GIC_SPI <<
749 <GIC_SPI <<
750 <GIC_SPI <<
751 <GIC_SPI <<
752 <GIC_SPI <<
753 <GIC_SPI <<
754 <GIC_SPI <<
755 <GIC_SPI <<
756 <GIC_SPI <<
757 <GIC_SPI <<
758 <GIC_SPI <<
759 <GIC_SPI <<
760 <GIC_SPI <<
761 <GIC_SPI <<
762 <GIC_SPI <<
763 <GIC_SPI <<
764 <GIC_SPI <<
765 <GIC_SPI <<
766 <GIC_SPI <<
767 <GIC_SPI <<
768 }; <<
769 <<
770 console@8340020 { <<
771 compatible = "fsl,dpaa <<
772 reg = <0x00000000 0x08 <<
773 }; <<
774 <<
775 ptp-timer@8b95000 { <<
776 compatible = "fsl,dpaa <<
777 reg = <0x0 0x8b95000 0 <<
778 clocks = <&clockgen QO <<
779 QO <<
780 little-endian; <<
781 fsl,extts-fifo; <<
782 }; <<
783 <<
784 emdio1: mdio@8b96000 { <<
785 compatible = "fsl,fman <<
786 reg = <0x0 0x8b96000 0 <<
787 little-endian; <<
788 #address-cells = <1>; <<
789 #size-cells = <0>; <<
790 clock-frequency = <250 <<
791 clocks = <&clockgen QO <<
792 QO <<
793 status = "disabled"; <<
794 }; <<
795 <<
796 emdio2: mdio@8b97000 { <<
797 compatible = "fsl,fman <<
798 reg = <0x0 0x8b97000 0 <<
799 little-endian; <<
800 #address-cells = <1>; <<
801 #size-cells = <0>; <<
802 clock-frequency = <250 <<
803 clocks = <&clockgen QO <<
804 QO <<
805 status = "disabled"; <<
806 }; <<
807 <<
808 pcs_mdio1: mdio@8c07000 { <<
809 compatible = "fsl,fman <<
810 reg = <0x0 0x8c07000 0 <<
811 little-endian; <<
812 #address-cells = <1>; <<
813 #size-cells = <0>; <<
814 status = "disabled"; <<
815 <<
816 pcs1: ethernet-phy@0 { <<
817 reg = <0>; <<
818 }; <<
819 }; <<
820 <<
821 pcs_mdio2: mdio@8c0b000 { <<
822 compatible = "fsl,fman <<
823 reg = <0x0 0x8c0b000 0 <<
824 little-endian; <<
825 #address-cells = <1>; <<
826 #size-cells = <0>; <<
827 status = "disabled"; <<
828 <<
829 pcs2: ethernet-phy@0 { <<
830 reg = <0>; <<
831 }; <<
832 }; <<
833 <<
834 pcs_mdio3: mdio@8c0f000 { <<
835 compatible = "fsl,fman <<
836 reg = <0x0 0x8c0f000 0 <<
837 little-endian; <<
838 #address-cells = <1>; <<
839 #size-cells = <0>; <<
840 status = "disabled"; <<
841 <<
842 pcs3_0: ethernet-phy@0 <<
843 reg = <0>; <<
844 }; <<
845 <<
846 pcs3_1: ethernet-phy@1 <<
847 reg = <1>; <<
848 }; <<
849 <<
850 pcs3_2: ethernet-phy@2 <<
851 reg = <2>; <<
852 }; <<
853 <<
854 pcs3_3: ethernet-phy@3 <<
855 reg = <3>; <<
856 }; <<
857 }; <<
858 <<
859 pcs_mdio7: mdio@8c1f000 { <<
860 compatible = "fsl,fman <<
861 reg = <0x0 0x8c1f000 0 <<
862 little-endian; <<
863 #address-cells = <1>; <<
864 #size-cells = <0>; <<
865 status = "disabled"; <<
866 <<
867 pcs7_0: ethernet-phy@0 <<
868 reg = <0>; <<
869 }; <<
870 <<
871 pcs7_1: ethernet-phy@1 <<
872 reg = <1>; <<
873 }; <<
874 <<
875 pcs7_2: ethernet-phy@2 <<
876 reg = <2>; <<
877 }; <<
878 <<
879 pcs7_3: ethernet-phy@3 <<
880 reg = <3>; <<
881 }; <<
882 }; <<
883 <<
884 cluster1_core0_watchdog: watch <<
885 compatible = "arm,sp80 587 compatible = "arm,sp805", "arm,primecell";
886 reg = <0x0 0xc000000 0 588 reg = <0x0 0xc000000 0x0 0x1000>;
887 clocks = <&clockgen QO !! 589 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
888 QO !! 590 clock-names = "apb_pclk", "wdog_clk";
889 <&clockgen QO <<
890 QO <<
891 clock-names = "wdog_cl <<
892 }; 591 };
893 592
894 cluster1_core1_watchdog: watch !! 593 cluster1_core1_watchdog: wdt@c010000 {
895 compatible = "arm,sp80 594 compatible = "arm,sp805", "arm,primecell";
896 reg = <0x0 0xc010000 0 595 reg = <0x0 0xc010000 0x0 0x1000>;
897 clocks = <&clockgen QO !! 596 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
898 QO !! 597 clock-names = "apb_pclk", "wdog_clk";
899 <&clockgen QO <<
900 QO <<
901 clock-names = "wdog_cl <<
902 }; 598 };
903 599
904 cluster1_core2_watchdog: watch !! 600 cluster1_core2_watchdog: wdt@c020000 {
905 compatible = "arm,sp80 601 compatible = "arm,sp805", "arm,primecell";
906 reg = <0x0 0xc020000 0 602 reg = <0x0 0xc020000 0x0 0x1000>;
907 clocks = <&clockgen QO !! 603 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
908 QO !! 604 clock-names = "apb_pclk", "wdog_clk";
909 <&clockgen QO <<
910 QO <<
911 clock-names = "wdog_cl <<
912 }; 605 };
913 606
914 cluster1_core3_watchdog: watch !! 607 cluster1_core3_watchdog: wdt@c030000 {
915 compatible = "arm,sp80 608 compatible = "arm,sp805", "arm,primecell";
916 reg = <0x0 0xc030000 0 609 reg = <0x0 0xc030000 0x0 0x1000>;
917 clocks = <&clockgen QO !! 610 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
918 QO !! 611 clock-names = "apb_pclk", "wdog_clk";
919 <&clockgen QO <<
920 QO <<
921 clock-names = "wdog_cl <<
922 }; 612 };
923 613
924 cluster2_core0_watchdog: watch !! 614 cluster2_core0_watchdog: wdt@c100000 {
925 compatible = "arm,sp80 615 compatible = "arm,sp805", "arm,primecell";
926 reg = <0x0 0xc100000 0 616 reg = <0x0 0xc100000 0x0 0x1000>;
927 clocks = <&clockgen QO !! 617 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
928 QO !! 618 clock-names = "apb_pclk", "wdog_clk";
929 <&clockgen QO <<
930 QO <<
931 clock-names = "wdog_cl <<
932 }; 619 };
933 620
934 cluster2_core1_watchdog: watch !! 621 cluster2_core1_watchdog: wdt@c110000 {
935 compatible = "arm,sp80 622 compatible = "arm,sp805", "arm,primecell";
936 reg = <0x0 0xc110000 0 623 reg = <0x0 0xc110000 0x0 0x1000>;
937 clocks = <&clockgen QO !! 624 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
938 QO !! 625 clock-names = "apb_pclk", "wdog_clk";
939 <&clockgen QO <<
940 QO <<
941 clock-names = "wdog_cl <<
942 }; 626 };
943 627
944 cluster2_core2_watchdog: watch !! 628 cluster2_core2_watchdog: wdt@c120000 {
945 compatible = "arm,sp80 629 compatible = "arm,sp805", "arm,primecell";
946 reg = <0x0 0xc120000 0 630 reg = <0x0 0xc120000 0x0 0x1000>;
947 clocks = <&clockgen QO !! 631 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
948 QO !! 632 clock-names = "apb_pclk", "wdog_clk";
949 <&clockgen QO <<
950 QO <<
951 clock-names = "wdog_cl <<
952 }; 633 };
953 634
954 cluster2_core3_watchdog: watch !! 635 cluster2_core3_watchdog: wdt@c130000 {
955 compatible = "arm,sp80 636 compatible = "arm,sp805", "arm,primecell";
956 reg = <0x0 0xc130000 0 637 reg = <0x0 0xc130000 0x0 0x1000>;
957 clocks = <&clockgen QO !! 638 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
958 QO !! 639 clock-names = "apb_pclk", "wdog_clk";
959 <&clockgen QO <<
960 QO <<
961 clock-names = "wdog_cl <<
962 }; <<
963 <<
964 fsl_mc: fsl-mc@80c000000 { <<
965 compatible = "fsl,qori <<
966 reg = <0x00000008 0x0c <<
967 <0x00000000 0x08 <<
968 msi-parent = <&its 0>; <<
969 iommu-map = <0 &smmu 0 <<
970 dma-coherent; <<
971 #address-cells = <3>; <<
972 #size-cells = <1>; <<
973 <<
974 /* <<
975 * Region type 0x0 - M <<
976 * Region type 0x1 - Q <<
977 */ <<
978 ranges = <0x0 0x0 0x0 <<
979 0x1 0x0 0x0 <<
980 <<
981 dpmacs { <<
982 #address-cells <<
983 #size-cells = <<
984 <<
985 dpmac1: ethern <<
986 compat <<
987 reg = <<
988 }; <<
989 <<
990 dpmac2: ethern <<
991 compat <<
992 reg = <<
993 }; <<
994 <<
995 dpmac3: ethern <<
996 compat <<
997 reg = <<
998 }; <<
999 <<
1000 dpmac4: ether <<
1001 compa <<
1002 reg = <<
1003 }; <<
1004 <<
1005 dpmac5: ether <<
1006 compa <<
1007 reg = <<
1008 }; <<
1009 <<
1010 dpmac6: ether <<
1011 compa <<
1012 reg = <<
1013 }; <<
1014 <<
1015 dpmac7: ether <<
1016 compa <<
1017 reg = <<
1018 }; <<
1019 <<
1020 dpmac8: ether <<
1021 compa <<
1022 reg = <<
1023 }; <<
1024 <<
1025 dpmac9: ether <<
1026 compa <<
1027 reg = <<
1028 }; <<
1029 <<
1030 dpmac10: ethe <<
1031 compa <<
1032 reg = <<
1033 }; <<
1034 }; <<
1035 }; <<
1036 <<
1037 rcpm: wakeup-controller@1e340 <<
1038 compatible = "fsl,ls1 <<
1039 reg = <0x0 0x1e34040 <<
1040 #fsl,rcpm-wakeup-cell <<
1041 little-endian; <<
1042 }; <<
1043 <<
1044 ftm_alarm0: rtc@2800000 { <<
1045 compatible = "fsl,ls1 <<
1046 reg = <0x0 0x2800000 <<
1047 fsl,rcpm-wakeup = <&r <<
1048 interrupts = <GIC_SPI <<
1049 }; 640 };
1050 }; 641 };
1051 642
1052 firmware { 643 firmware {
1053 optee { 644 optee {
1054 compatible = "linaro, 645 compatible = "linaro,optee-tz";
1055 method = "smc"; 646 method = "smc";
1056 }; 647 };
1057 }; 648 };
>> 649
1058 }; 650 };
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