1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 * 4 *
5 * Copyright 2017-2020 NXP 5 * Copyright 2017-2020 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "fsl,ls1088a"; 15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 crypto = &crypto; 21 crypto = &crypto;
22 rtc1 = &ftm_alarm0; 22 rtc1 = &ftm_alarm0;
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 /* We have 2 clusters having 4 29 /* We have 2 clusters having 4 Cortex-A53 cores each */
30 cpu0: cpu@0 { 30 cpu0: cpu@0 {
31 device_type = "cpu"; 31 device_type = "cpu";
32 compatible = "arm,cort 32 compatible = "arm,cortex-a53";
33 reg = <0x0>; 33 reg = <0x0>;
34 clocks = <&clockgen QO 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 cpu-idle-states = <&CP 35 cpu-idle-states = <&CPU_PH20>;
36 #cooling-cells = <2>; 36 #cooling-cells = <2>;
37 }; 37 };
38 38
39 cpu1: cpu@1 { 39 cpu1: cpu@1 {
40 device_type = "cpu"; 40 device_type = "cpu";
41 compatible = "arm,cort 41 compatible = "arm,cortex-a53";
42 reg = <0x1>; 42 reg = <0x1>;
43 clocks = <&clockgen QO 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
44 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>; 45 #cooling-cells = <2>;
46 }; 46 };
47 47
48 cpu2: cpu@2 { 48 cpu2: cpu@2 {
49 device_type = "cpu"; 49 device_type = "cpu";
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 reg = <0x2>; 51 reg = <0x2>;
52 clocks = <&clockgen QO 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 cpu-idle-states = <&CP 53 cpu-idle-states = <&CPU_PH20>;
54 #cooling-cells = <2>; 54 #cooling-cells = <2>;
55 }; 55 };
56 56
57 cpu3: cpu@3 { 57 cpu3: cpu@3 {
58 device_type = "cpu"; 58 device_type = "cpu";
59 compatible = "arm,cort 59 compatible = "arm,cortex-a53";
60 reg = <0x3>; 60 reg = <0x3>;
61 clocks = <&clockgen QO 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 cpu-idle-states = <&CP 62 cpu-idle-states = <&CPU_PH20>;
63 #cooling-cells = <2>; 63 #cooling-cells = <2>;
64 }; 64 };
65 65
66 cpu4: cpu@100 { 66 cpu4: cpu@100 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cort 68 compatible = "arm,cortex-a53";
69 reg = <0x100>; 69 reg = <0x100>;
70 clocks = <&clockgen QO 70 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
71 cpu-idle-states = <&CP 71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 72 #cooling-cells = <2>;
73 }; 73 };
74 74
75 cpu5: cpu@101 { 75 cpu5: cpu@101 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 reg = <0x101>; 78 reg = <0x101>;
79 clocks = <&clockgen QO 79 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
80 cpu-idle-states = <&CP 80 cpu-idle-states = <&CPU_PH20>;
81 #cooling-cells = <2>; 81 #cooling-cells = <2>;
82 }; 82 };
83 83
84 cpu6: cpu@102 { 84 cpu6: cpu@102 {
85 device_type = "cpu"; 85 device_type = "cpu";
86 compatible = "arm,cort 86 compatible = "arm,cortex-a53";
87 reg = <0x102>; 87 reg = <0x102>;
88 clocks = <&clockgen QO 88 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
89 cpu-idle-states = <&CP 89 cpu-idle-states = <&CPU_PH20>;
90 #cooling-cells = <2>; 90 #cooling-cells = <2>;
91 }; 91 };
92 92
93 cpu7: cpu@103 { 93 cpu7: cpu@103 {
94 device_type = "cpu"; 94 device_type = "cpu";
95 compatible = "arm,cort 95 compatible = "arm,cortex-a53";
96 reg = <0x103>; 96 reg = <0x103>;
97 clocks = <&clockgen QO 97 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
98 cpu-idle-states = <&CP 98 cpu-idle-states = <&CPU_PH20>;
99 #cooling-cells = <2>; 99 #cooling-cells = <2>;
100 }; 100 };
101 101
102 CPU_PH20: cpu-ph20 { 102 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle 103 compatible = "arm,idle-state";
104 idle-state-name = "PH2 104 idle-state-name = "PH20";
105 arm,psci-suspend-param 105 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <10 106 entry-latency-us = <1000>;
107 exit-latency-us = <100 107 exit-latency-us = <1000>;
108 min-residency-us = <30 108 min-residency-us = <3000>;
109 }; 109 };
110 }; 110 };
111 111
112 gic: interrupt-controller@6000000 { 112 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3"; 113 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 interrupt-controller; 115 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x1000 116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x1000 117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x2000 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <GIC_PPI 9 IRQ_TY !! 121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>; 122 #address-cells = <2>;
123 #size-cells = <2>; 123 #size-cells = <2>;
124 ranges; 124 ranges;
125 125
126 its: msi-controller@6020000 { !! 126 its: gic-its@6020000 {
127 compatible = "arm,gic- 127 compatible = "arm,gic-v3-its";
128 msi-controller; 128 msi-controller;
129 #msi-cells = <1>; <<
130 reg = <0x0 0x6020000 0 129 reg = <0x0 0x6020000 0 0x20000>;
131 }; 130 };
132 }; 131 };
133 132
134 thermal-zones { 133 thermal-zones {
135 cluster-thermal { !! 134 core-cluster {
136 polling-delay-passive 135 polling-delay-passive = <1000>;
137 polling-delay = <5000> 136 polling-delay = <5000>;
138 thermal-sensors = <&tm 137 thermal-sensors = <&tmu 0>;
139 138
140 trips { 139 trips {
141 core_cluster_a 140 core_cluster_alert: core-cluster-alert {
142 temper 141 temperature = <85000>;
143 hyster 142 hysteresis = <2000>;
144 type = 143 type = "passive";
145 }; 144 };
146 145
147 core-cluster-c 146 core-cluster-crit {
148 temper 147 temperature = <95000>;
149 hyster 148 hysteresis = <2000>;
150 type = 149 type = "critical";
151 }; 150 };
152 }; 151 };
153 152
154 cooling-maps { 153 cooling-maps {
155 map0 { 154 map0 {
156 trip = 155 trip = <&core_cluster_alert>;
157 coolin 156 cooling-device =
158 157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163 162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
165 164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
166 }; 165 };
167 }; 166 };
168 }; 167 };
169 168
170 soc-thermal { !! 169 soc {
171 polling-delay-passive 170 polling-delay-passive = <1000>;
172 polling-delay = <5000> 171 polling-delay = <5000>;
173 thermal-sensors = <&tm 172 thermal-sensors = <&tmu 1>;
174 173
175 trips { 174 trips {
176 soc-crit { 175 soc-crit {
177 temper 176 temperature = <95000>;
178 hyster 177 hysteresis = <2000>;
179 type = 178 type = "critical";
180 }; 179 };
181 }; 180 };
182 }; 181 };
183 }; 182 };
184 183
185 timer { 184 timer {
186 compatible = "arm,armv8-timer" 185 compatible = "arm,armv8-timer";
187 interrupts = <GIC_PPI 13 IRQ_T !! 186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
188 <GIC_PPI 14 IRQ_T !! 187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
189 <GIC_PPI 11 IRQ_T !! 188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
190 <GIC_PPI 10 IRQ_T !! 189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
191 }; <<
192 <<
193 pmu { <<
194 compatible = "arm,cortex-a53-p <<
195 interrupts = <GIC_PPI 7 IRQ_TY <<
196 }; 190 };
197 191
198 psci { 192 psci {
199 compatible = "arm,psci-0.2"; 193 compatible = "arm,psci-0.2";
200 method = "smc"; 194 method = "smc";
201 }; 195 };
202 196
203 sysclk: sysclk { 197 sysclk: sysclk {
204 compatible = "fixed-clock"; 198 compatible = "fixed-clock";
205 #clock-cells = <0>; 199 #clock-cells = <0>;
206 clock-frequency = <100000000>; 200 clock-frequency = <100000000>;
207 clock-output-names = "sysclk"; 201 clock-output-names = "sysclk";
208 }; 202 };
209 203
210 reboot { <<
211 compatible = "syscon-reboot"; <<
212 regmap = <&reset>; <<
213 offset = <0x0>; <<
214 mask = <0x02>; <<
215 }; <<
216 <<
217 soc { 204 soc {
218 compatible = "simple-bus"; 205 compatible = "simple-bus";
219 #address-cells = <2>; 206 #address-cells = <2>;
220 #size-cells = <2>; 207 #size-cells = <2>;
221 ranges; 208 ranges;
222 dma-ranges = <0x0 0x0 0x0 0x0 209 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
223 210
224 clockgen: clocking@1300000 { 211 clockgen: clocking@1300000 {
225 compatible = "fsl,ls10 212 compatible = "fsl,ls1088a-clockgen";
226 reg = <0 0x1300000 0 0 213 reg = <0 0x1300000 0 0xa0000>;
227 #clock-cells = <2>; 214 #clock-cells = <2>;
228 clocks = <&sysclk>; 215 clocks = <&sysclk>;
229 }; 216 };
230 217
231 dcfg: dcfg@1e00000 { 218 dcfg: dcfg@1e00000 {
232 compatible = "fsl,ls10 219 compatible = "fsl,ls1088a-dcfg", "syscon";
233 reg = <0x0 0x1e00000 0 220 reg = <0x0 0x1e00000 0x0 0x10000>;
234 little-endian; 221 little-endian;
235 }; 222 };
236 223
237 reset: syscon@1e60000 { <<
238 compatible = "fsl,ls10 <<
239 reg = <0x0 0x1e60000 0 <<
240 }; <<
241 <<
242 isc: syscon@1f70000 { 224 isc: syscon@1f70000 {
243 compatible = "fsl,ls10 225 compatible = "fsl,ls1088a-isc", "syscon";
244 reg = <0x0 0x1f70000 0 226 reg = <0x0 0x1f70000 0x0 0x10000>;
245 little-endian; 227 little-endian;
246 #address-cells = <1>; 228 #address-cells = <1>;
247 #size-cells = <1>; 229 #size-cells = <1>;
248 ranges = <0x0 0x0 0x1f 230 ranges = <0x0 0x0 0x1f70000 0x10000>;
249 231
250 extirq: interrupt-cont 232 extirq: interrupt-controller@14 {
251 compatible = " 233 compatible = "fsl,ls1088a-extirq";
252 #interrupt-cel 234 #interrupt-cells = <2>;
253 #address-cells 235 #address-cells = <0>;
254 interrupt-cont 236 interrupt-controller;
255 reg = <0x14 4> 237 reg = <0x14 4>;
256 interrupt-map 238 interrupt-map =
257 <0 0 & 239 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <1 0 & 240 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <2 0 & 241 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <3 0 & 242 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <4 0 & 243 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
262 <5 0 & 244 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
263 <6 0 & 245 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
264 <7 0 & 246 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
265 <8 0 & 247 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
266 <9 0 & 248 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
267 <10 0 249 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
268 <11 0 250 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-map- !! 251 interrupt-map-mask = <0xffffffff 0x0>;
270 }; 252 };
271 }; 253 };
272 254
273 sfp: efuse@1e80000 { <<
274 compatible = "fsl,ls10 <<
275 reg = <0x0 0x1e80000 0 <<
276 clocks = <&clockgen QO <<
277 QO <<
278 clock-names = "sfp"; <<
279 }; <<
280 <<
281 tmu: tmu@1f80000 { 255 tmu: tmu@1f80000 {
282 compatible = "fsl,qori 256 compatible = "fsl,qoriq-tmu";
283 reg = <0x0 0x1f80000 0 257 reg = <0x0 0x1f80000 0x0 0x10000>;
284 interrupts = <GIC_SPI !! 258 interrupts = <0 23 0x4>;
285 fsl,tmu-range = <0xb00 259 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
286 fsl,tmu-calibration = 260 fsl,tmu-calibration =
287 /* Calibration 261 /* Calibration data group 1 */
288 <0x00000000 0x !! 262 <0x00000000 0x00000023
289 <0x00000001 0x !! 263 0x00000001 0x0000002a
290 <0x00000002 0x !! 264 0x00000002 0x00000030
291 <0x00000003 0x !! 265 0x00000003 0x00000037
292 <0x00000004 0x !! 266 0x00000004 0x0000003d
293 <0x00000005 0x !! 267 0x00000005 0x00000044
294 <0x00000006 0x !! 268 0x00000006 0x0000004a
295 <0x00000007 0x !! 269 0x00000007 0x00000051
296 <0x00000008 0x !! 270 0x00000008 0x00000057
297 <0x00000009 0x !! 271 0x00000009 0x0000005e
298 <0x0000000a 0x !! 272 0x0000000a 0x00000064
299 <0x0000000b 0x !! 273 0x0000000b 0x0000006b
300 /* Calibration 274 /* Calibration data group 2 */
301 <0x00010000 0x !! 275 0x00010000 0x00000022
302 <0x00010001 0x !! 276 0x00010001 0x0000002a
303 <0x00010002 0x !! 277 0x00010002 0x00000032
304 <0x00010003 0x !! 278 0x00010003 0x0000003a
305 <0x00010004 0x !! 279 0x00010004 0x00000042
306 <0x00010005 0x !! 280 0x00010005 0x0000004a
307 <0x00010006 0x !! 281 0x00010006 0x00000052
308 <0x00010007 0x !! 282 0x00010007 0x0000005a
309 <0x00010008 0x !! 283 0x00010008 0x00000062
310 <0x00010009 0x !! 284 0x00010009 0x0000006a
311 /* Calibration 285 /* Calibration data group 3 */
312 <0x00020000 0x !! 286 0x00020000 0x00000021
313 <0x00020001 0x !! 287 0x00020001 0x0000002b
314 <0x00020002 0x !! 288 0x00020002 0x00000035
315 <0x00020003 0x !! 289 0x00020003 0x00000040
316 <0x00020004 0x !! 290 0x00020004 0x0000004a
317 <0x00020005 0x !! 291 0x00020005 0x00000054
318 <0x00020006 0x !! 292 0x00020006 0x0000005e
319 /* Calibration 293 /* Calibration data group 4 */
320 <0x00030000 0x !! 294 0x00030000 0x00000010
321 <0x00030001 0x !! 295 0x00030001 0x0000001c
322 <0x00030002 0x !! 296 0x00030002 0x00000027
323 <0x00030003 0x !! 297 0x00030003 0x00000032
324 <0x00030004 0x !! 298 0x00030004 0x0000003e
325 <0x00030005 0x !! 299 0x00030005 0x00000049
326 <0x00030006 0x !! 300 0x00030006 0x00000054
327 <0x00030007 0x !! 301 0x00030007 0x00000060>;
328 little-endian; 302 little-endian;
329 #thermal-sensor-cells 303 #thermal-sensor-cells = <1>;
330 }; 304 };
331 305
332 dspi: spi@2100000 { 306 dspi: spi@2100000 {
333 compatible = "fsl,ls10 307 compatible = "fsl,ls1088a-dspi",
334 "fsl,ls10 308 "fsl,ls1021a-v1.0-dspi";
335 #address-cells = <1>; 309 #address-cells = <1>;
336 #size-cells = <0>; 310 #size-cells = <0>;
337 reg = <0x0 0x2100000 0 311 reg = <0x0 0x2100000 0x0 0x10000>;
338 interrupts = <GIC_SPI 312 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
339 clock-names = "dspi"; 313 clock-names = "dspi";
340 clocks = <&clockgen QO 314 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
341 QO 315 QORIQ_CLK_PLL_DIV(2)>;
342 spi-num-chipselects = 316 spi-num-chipselects = <6>;
343 status = "disabled"; 317 status = "disabled";
344 }; 318 };
345 319
346 duart0: serial@21c0500 { 320 duart0: serial@21c0500 {
347 compatible = "fsl,ns16 321 compatible = "fsl,ns16550", "ns16550a";
348 reg = <0x0 0x21c0500 0 322 reg = <0x0 0x21c0500 0x0 0x100>;
349 clocks = <&clockgen QO 323 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
350 QO 324 QORIQ_CLK_PLL_DIV(4)>;
351 interrupts = <GIC_SPI !! 325 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
352 status = "disabled"; 326 status = "disabled";
353 }; 327 };
354 328
355 duart1: serial@21c0600 { 329 duart1: serial@21c0600 {
356 compatible = "fsl,ns16 330 compatible = "fsl,ns16550", "ns16550a";
357 reg = <0x0 0x21c0600 0 331 reg = <0x0 0x21c0600 0x0 0x100>;
358 clocks = <&clockgen QO 332 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
359 QO 333 QORIQ_CLK_PLL_DIV(4)>;
360 interrupts = <GIC_SPI !! 334 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
361 status = "disabled"; 335 status = "disabled";
362 }; 336 };
363 337
364 gpio0: gpio@2300000 { 338 gpio0: gpio@2300000 {
365 compatible = "fsl,ls10 339 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
366 reg = <0x0 0x2300000 0 340 reg = <0x0 0x2300000 0x0 0x10000>;
367 interrupts = <GIC_SPI !! 341 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
368 little-endian; 342 little-endian;
369 gpio-controller; 343 gpio-controller;
370 #gpio-cells = <2>; 344 #gpio-cells = <2>;
371 interrupt-controller; 345 interrupt-controller;
372 #interrupt-cells = <2> 346 #interrupt-cells = <2>;
373 }; 347 };
374 348
375 gpio1: gpio@2310000 { 349 gpio1: gpio@2310000 {
376 compatible = "fsl,ls10 350 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
377 reg = <0x0 0x2310000 0 351 reg = <0x0 0x2310000 0x0 0x10000>;
378 interrupts = <GIC_SPI !! 352 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
379 little-endian; 353 little-endian;
380 gpio-controller; 354 gpio-controller;
381 #gpio-cells = <2>; 355 #gpio-cells = <2>;
382 interrupt-controller; 356 interrupt-controller;
383 #interrupt-cells = <2> 357 #interrupt-cells = <2>;
384 }; 358 };
385 359
386 gpio2: gpio@2320000 { 360 gpio2: gpio@2320000 {
387 compatible = "fsl,ls10 361 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0 362 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI !! 363 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
390 little-endian; 364 little-endian;
391 gpio-controller; 365 gpio-controller;
392 #gpio-cells = <2>; 366 #gpio-cells = <2>;
393 interrupt-controller; 367 interrupt-controller;
394 #interrupt-cells = <2> 368 #interrupt-cells = <2>;
395 }; 369 };
396 370
397 gpio3: gpio@2330000 { 371 gpio3: gpio@2330000 {
398 compatible = "fsl,ls10 372 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
399 reg = <0x0 0x2330000 0 373 reg = <0x0 0x2330000 0x0 0x10000>;
400 interrupts = <GIC_SPI !! 374 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
401 little-endian; 375 little-endian;
402 gpio-controller; 376 gpio-controller;
403 #gpio-cells = <2>; 377 #gpio-cells = <2>;
404 interrupt-controller; 378 interrupt-controller;
405 #interrupt-cells = <2> 379 #interrupt-cells = <2>;
406 }; 380 };
407 381
408 ifc: memory-controller@2240000 !! 382 ifc: ifc@2240000 {
409 compatible = "fsl,ifc" !! 383 compatible = "fsl,ifc", "simple-bus";
410 reg = <0x0 0x2240000 0 384 reg = <0x0 0x2240000 0x0 0x20000>;
411 interrupts = <GIC_SPI !! 385 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
412 little-endian; 386 little-endian;
413 #address-cells = <2>; 387 #address-cells = <2>;
414 #size-cells = <1>; 388 #size-cells = <1>;
415 status = "disabled"; 389 status = "disabled";
416 }; 390 };
417 391
418 i2c0: i2c@2000000 { 392 i2c0: i2c@2000000 {
419 compatible = "fsl,vf61 393 compatible = "fsl,vf610-i2c";
420 #address-cells = <1>; 394 #address-cells = <1>;
421 #size-cells = <0>; 395 #size-cells = <0>;
422 reg = <0x0 0x2000000 0 396 reg = <0x0 0x2000000 0x0 0x10000>;
423 interrupts = <GIC_SPI !! 397 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen QO 398 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
425 QO 399 QORIQ_CLK_PLL_DIV(8)>;
426 status = "disabled"; 400 status = "disabled";
427 }; 401 };
428 402
429 i2c1: i2c@2010000 { 403 i2c1: i2c@2010000 {
430 compatible = "fsl,vf61 404 compatible = "fsl,vf610-i2c";
431 #address-cells = <1>; 405 #address-cells = <1>;
432 #size-cells = <0>; 406 #size-cells = <0>;
433 reg = <0x0 0x2010000 0 407 reg = <0x0 0x2010000 0x0 0x10000>;
434 interrupts = <GIC_SPI !! 408 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clockgen QO 409 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
436 QO 410 QORIQ_CLK_PLL_DIV(8)>;
437 status = "disabled"; 411 status = "disabled";
438 }; 412 };
439 413
440 i2c2: i2c@2020000 { 414 i2c2: i2c@2020000 {
441 compatible = "fsl,vf61 415 compatible = "fsl,vf610-i2c";
442 #address-cells = <1>; 416 #address-cells = <1>;
443 #size-cells = <0>; 417 #size-cells = <0>;
444 reg = <0x0 0x2020000 0 418 reg = <0x0 0x2020000 0x0 0x10000>;
445 interrupts = <GIC_SPI !! 419 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen QO 420 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
447 QO 421 QORIQ_CLK_PLL_DIV(8)>;
448 status = "disabled"; 422 status = "disabled";
449 }; 423 };
450 424
451 i2c3: i2c@2030000 { 425 i2c3: i2c@2030000 {
452 compatible = "fsl,vf61 426 compatible = "fsl,vf610-i2c";
453 #address-cells = <1>; 427 #address-cells = <1>;
454 #size-cells = <0>; 428 #size-cells = <0>;
455 reg = <0x0 0x2030000 0 429 reg = <0x0 0x2030000 0x0 0x10000>;
456 interrupts = <GIC_SPI !! 430 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clockgen QO 431 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
458 QO 432 QORIQ_CLK_PLL_DIV(8)>;
459 status = "disabled"; 433 status = "disabled";
460 }; 434 };
461 435
462 qspi: spi@20c0000 { 436 qspi: spi@20c0000 {
463 compatible = "fsl,ls20 437 compatible = "fsl,ls2080a-qspi";
464 #address-cells = <1>; 438 #address-cells = <1>;
465 #size-cells = <0>; 439 #size-cells = <0>;
466 reg = <0x0 0x20c0000 0 440 reg = <0x0 0x20c0000 0x0 0x10000>,
467 <0x0 0x20000000 441 <0x0 0x20000000 0x0 0x10000000>;
468 reg-names = "QuadSPI", 442 reg-names = "QuadSPI", "QuadSPI-memory";
469 interrupts = <GIC_SPI 443 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
470 clock-names = "qspi_en 444 clock-names = "qspi_en", "qspi";
471 clocks = <&clockgen QO 445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
472 QO 446 QORIQ_CLK_PLL_DIV(4)>,
473 <&clockgen QO 447 <&clockgen QORIQ_CLK_PLATFORM_PLL
474 QO 448 QORIQ_CLK_PLL_DIV(4)>;
475 status = "disabled"; 449 status = "disabled";
476 }; 450 };
477 451
478 esdhc: mmc@2140000 { !! 452 esdhc: esdhc@2140000 {
479 compatible = "fsl,ls10 453 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
480 reg = <0x0 0x2140000 0 454 reg = <0x0 0x2140000 0x0 0x10000>;
481 interrupts = <GIC_SPI !! 455 interrupts = <0 28 0x4>; /* Level high type */
482 clock-frequency = <0>; 456 clock-frequency = <0>;
483 clocks = <&clockgen QO 457 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
484 voltage-ranges = <1800 458 voltage-ranges = <1800 1800 3300 3300>;
485 sdhci,auto-cmd12; 459 sdhci,auto-cmd12;
486 little-endian; 460 little-endian;
487 bus-width = <4>; 461 bus-width = <4>;
488 status = "disabled"; 462 status = "disabled";
489 }; 463 };
490 464
491 usb0: usb@3100000 { 465 usb0: usb@3100000 {
492 compatible = "snps,dwc 466 compatible = "snps,dwc3";
493 reg = <0x0 0x3100000 0 467 reg = <0x0 0x3100000 0x0 0x10000>;
494 interrupts = <GIC_SPI !! 468 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 dr_mode = "host"; 469 dr_mode = "host";
496 snps,quirk-frame-lengt 470 snps,quirk-frame-length-adjustment = <0x20>;
497 snps,dis_rxdet_inp3_qu 471 snps,dis_rxdet_inp3_quirk;
498 snps,incr-burst-type-a 472 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
499 status = "disabled"; 473 status = "disabled";
500 }; 474 };
501 475
502 usb1: usb@3110000 { 476 usb1: usb@3110000 {
503 compatible = "snps,dwc 477 compatible = "snps,dwc3";
504 reg = <0x0 0x3110000 0 478 reg = <0x0 0x3110000 0x0 0x10000>;
505 interrupts = <GIC_SPI !! 479 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 dr_mode = "host"; 480 dr_mode = "host";
507 snps,quirk-frame-lengt 481 snps,quirk-frame-length-adjustment = <0x20>;
508 snps,dis_rxdet_inp3_qu 482 snps,dis_rxdet_inp3_quirk;
509 snps,incr-burst-type-a <<
510 status = "disabled"; 483 status = "disabled";
511 }; 484 };
512 485
513 sata: sata@3200000 { 486 sata: sata@3200000 {
514 compatible = "fsl,ls10 487 compatible = "fsl,ls1088a-ahci";
515 reg = <0x0 0x3200000 0 488 reg = <0x0 0x3200000 0x0 0x10000>,
516 <0x7 0x100520 489 <0x7 0x100520 0x0 0x4>;
517 reg-names = "ahci", "s 490 reg-names = "ahci", "sata-ecc";
518 interrupts = <GIC_SPI !! 491 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clockgen QO 492 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
520 QO 493 QORIQ_CLK_PLL_DIV(4)>;
521 dma-coherent; 494 dma-coherent;
522 status = "disabled"; 495 status = "disabled";
523 }; 496 };
524 497
525 crypto: crypto@8000000 { 498 crypto: crypto@8000000 {
526 compatible = "fsl,sec- 499 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
527 fsl,sec-era = <8>; 500 fsl,sec-era = <8>;
528 #address-cells = <1>; 501 #address-cells = <1>;
529 #size-cells = <1>; 502 #size-cells = <1>;
530 ranges = <0x0 0x00 0x8 503 ranges = <0x0 0x00 0x8000000 0x100000>;
531 reg = <0x00 0x8000000 504 reg = <0x00 0x8000000 0x0 0x100000>;
532 interrupts = <GIC_SPI 505 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
533 dma-coherent; 506 dma-coherent;
534 507
535 sec_jr0: jr@10000 { 508 sec_jr0: jr@10000 {
536 compatible = " 509 compatible = "fsl,sec-v5.0-job-ring",
537 " 510 "fsl,sec-v4.0-job-ring";
538 reg = <0x10000 !! 511 reg = <0x10000 0x10000>;
539 interrupts = < 512 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
540 }; 513 };
541 514
542 sec_jr1: jr@20000 { 515 sec_jr1: jr@20000 {
543 compatible = " 516 compatible = "fsl,sec-v5.0-job-ring",
544 " 517 "fsl,sec-v4.0-job-ring";
545 reg = <0x20000 !! 518 reg = <0x20000 0x10000>;
546 interrupts = < 519 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
547 }; 520 };
548 521
549 sec_jr2: jr@30000 { 522 sec_jr2: jr@30000 {
550 compatible = " 523 compatible = "fsl,sec-v5.0-job-ring",
551 " 524 "fsl,sec-v4.0-job-ring";
552 reg = <0x30000 !! 525 reg = <0x30000 0x10000>;
553 interrupts = < 526 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
554 }; 527 };
555 528
556 sec_jr3: jr@40000 { 529 sec_jr3: jr@40000 {
557 compatible = " 530 compatible = "fsl,sec-v5.0-job-ring",
558 " 531 "fsl,sec-v4.0-job-ring";
559 reg = <0x40000 !! 532 reg = <0x40000 0x10000>;
560 interrupts = < 533 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
561 }; 534 };
562 }; 535 };
563 536
564 pcie1: pcie@3400000 { 537 pcie1: pcie@3400000 {
565 compatible = "fsl,ls10 538 compatible = "fsl,ls1088a-pcie";
566 reg = <0x00 0x03400000 !! 539 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
567 <0x20 0x00000000 !! 540 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
568 reg-names = "regs", "c 541 reg-names = "regs", "config";
569 interrupts = <GIC_SPI !! 542 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
570 interrupt-names = "aer 543 interrupt-names = "aer";
571 #address-cells = <3>; 544 #address-cells = <3>;
572 #size-cells = <2>; 545 #size-cells = <2>;
573 device_type = "pci"; 546 device_type = "pci";
574 dma-coherent; 547 dma-coherent;
575 num-viewport = <256>; 548 num-viewport = <256>;
576 bus-range = <0x0 0xff> 549 bus-range = <0x0 0xff>;
577 ranges = <0x81000000 0 550 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
578 0x82000000 0 551 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
579 msi-parent = <&its 0>; !! 552 msi-parent = <&its>;
580 #interrupt-cells = <1> 553 #interrupt-cells = <1>;
581 interrupt-map-mask = < 554 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0000 555 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 556 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 557 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
585 <0000 558 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
586 iommu-map = <0 &smmu 0 559 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
587 status = "disabled"; 560 status = "disabled";
588 }; 561 };
589 562
590 pcie_ep1: pcie-ep@3400000 { 563 pcie_ep1: pcie-ep@3400000 {
591 compatible = "fsl,ls10 !! 564 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
592 reg = <0x00 0x03400000 !! 565 reg = <0x00 0x03400000 0x0 0x00100000
593 <0x20 0x00000000 !! 566 0x20 0x00000000 0x8 0x00000000>;
594 reg-names = "regs", "a 567 reg-names = "regs", "addr_space";
595 interrupts = <GIC_SPI <<
596 interrupt-names = "pme <<
597 num-ib-windows = <24>; 568 num-ib-windows = <24>;
598 num-ob-windows = <256> 569 num-ob-windows = <256>;
599 max-functions = /bits/ 570 max-functions = /bits/ 8 <2>;
600 status = "disabled"; 571 status = "disabled";
601 }; 572 };
602 573
603 pcie2: pcie@3500000 { 574 pcie2: pcie@3500000 {
604 compatible = "fsl,ls10 575 compatible = "fsl,ls1088a-pcie";
605 reg = <0x00 0x03500000 !! 576 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
606 <0x28 0x00000000 !! 577 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
607 reg-names = "regs", "c 578 reg-names = "regs", "config";
608 interrupts = <GIC_SPI !! 579 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
609 interrupt-names = "aer 580 interrupt-names = "aer";
610 #address-cells = <3>; 581 #address-cells = <3>;
611 #size-cells = <2>; 582 #size-cells = <2>;
612 device_type = "pci"; 583 device_type = "pci";
613 dma-coherent; 584 dma-coherent;
614 num-viewport = <6>; 585 num-viewport = <6>;
615 bus-range = <0x0 0xff> 586 bus-range = <0x0 0xff>;
616 ranges = <0x81000000 0 587 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
617 0x82000000 0 588 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
618 msi-parent = <&its 0>; !! 589 msi-parent = <&its>;
619 #interrupt-cells = <1> 590 #interrupt-cells = <1>;
620 interrupt-map-mask = < 591 interrupt-map-mask = <0 0 0 7>;
621 interrupt-map = <0000 592 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 593 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 594 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
624 <0000 595 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
625 iommu-map = <0 &smmu 0 596 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
626 status = "disabled"; 597 status = "disabled";
627 }; 598 };
628 599
629 pcie_ep2: pcie-ep@3500000 { 600 pcie_ep2: pcie-ep@3500000 {
630 compatible = "fsl,ls10 !! 601 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
631 reg = <0x00 0x03500000 !! 602 reg = <0x00 0x03500000 0x0 0x00100000
632 <0x28 0x00000000 !! 603 0x28 0x00000000 0x8 0x00000000>;
633 reg-names = "regs", "a 604 reg-names = "regs", "addr_space";
634 interrupts = <GIC_SPI <<
635 interrupt-names = "pme <<
636 num-ib-windows = <6>; 605 num-ib-windows = <6>;
637 num-ob-windows = <6>; 606 num-ob-windows = <6>;
638 status = "disabled"; 607 status = "disabled";
639 }; 608 };
640 609
641 pcie3: pcie@3600000 { 610 pcie3: pcie@3600000 {
642 compatible = "fsl,ls10 611 compatible = "fsl,ls1088a-pcie";
643 reg = <0x00 0x03600000 !! 612 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
644 <0x30 0x00000000 !! 613 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
645 reg-names = "regs", "c 614 reg-names = "regs", "config";
646 interrupts = <GIC_SPI !! 615 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
647 interrupt-names = "aer 616 interrupt-names = "aer";
648 #address-cells = <3>; 617 #address-cells = <3>;
649 #size-cells = <2>; 618 #size-cells = <2>;
650 device_type = "pci"; 619 device_type = "pci";
651 dma-coherent; 620 dma-coherent;
652 num-viewport = <6>; 621 num-viewport = <6>;
653 bus-range = <0x0 0xff> 622 bus-range = <0x0 0xff>;
654 ranges = <0x81000000 0 623 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
655 0x82000000 0 624 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
656 msi-parent = <&its 0>; !! 625 msi-parent = <&its>;
657 #interrupt-cells = <1> 626 #interrupt-cells = <1>;
658 interrupt-map-mask = < 627 interrupt-map-mask = <0 0 0 7>;
659 interrupt-map = <0000 628 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 629 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 630 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
662 <0000 631 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
663 iommu-map = <0 &smmu 0 632 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
664 status = "disabled"; 633 status = "disabled";
665 }; 634 };
666 635
667 pcie_ep3: pcie-ep@3600000 { 636 pcie_ep3: pcie-ep@3600000 {
668 compatible = "fsl,ls10 !! 637 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
669 reg = <0x00 0x03600000 !! 638 reg = <0x00 0x03600000 0x0 0x00100000
670 <0x30 0x00000000 !! 639 0x30 0x00000000 0x8 0x00000000>;
671 reg-names = "regs", "a 640 reg-names = "regs", "addr_space";
672 interrupts = <GIC_SPI <<
673 interrupt-names = "pme <<
674 num-ib-windows = <6>; 641 num-ib-windows = <6>;
675 num-ob-windows = <6>; 642 num-ob-windows = <6>;
676 status = "disabled"; 643 status = "disabled";
677 }; 644 };
678 645
679 smmu: iommu@5000000 { 646 smmu: iommu@5000000 {
680 compatible = "arm,mmu- 647 compatible = "arm,mmu-500";
681 reg = <0 0x5000000 0 0 648 reg = <0 0x5000000 0 0x800000>;
682 #iommu-cells = <1>; 649 #iommu-cells = <1>;
683 stream-match-mask = <0 650 stream-match-mask = <0x7C00>;
684 dma-coherent; <<
685 #global-interrupts = < 651 #global-interrupts = <12>;
686 // global 652 // global secure fault
687 interrupts = <GIC_SPI 653 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
688 // combin 654 // combined secure
689 <GIC_SPI 655 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
690 // global 656 // global non-secure fault
691 <GIC_SPI 657 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
692 // combin 658 // combined non-secure
693 <GIC_SPI 659 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
694 // perfor 660 // performance counter interrupts 0-7
695 <GIC_SPI 661 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 662 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 663 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 664 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 665 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 666 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 667 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 668 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
703 // per co 669 // per context interrupt, 64 interrupts
704 <GIC_SPI 670 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 671 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 672 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 673 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 674 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 675 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 676 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 677 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 678 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 679 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 680 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 681 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 682 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 683 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 684 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 685 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 686 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 687 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 688 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 689 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 690 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 691 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 692 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 693 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 694 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 695 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 696 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 697 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 698 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 699 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 700 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 701 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 702 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 703 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 704 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 705 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 706 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 707 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 708 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 709 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 710 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 711 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 712 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 713 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 714 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 715 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 716 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 717 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 718 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 719 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 720 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 721 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 722 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 723 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 724 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 725 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 726 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 727 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 728 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 729 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 730 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 731 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 732 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 733 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
768 }; 734 };
769 735
770 console@8340020 { 736 console@8340020 {
771 compatible = "fsl,dpaa 737 compatible = "fsl,dpaa2-console";
772 reg = <0x00000000 0x08 738 reg = <0x00000000 0x08340020 0 0x2>;
773 }; 739 };
774 740
775 ptp-timer@8b95000 { 741 ptp-timer@8b95000 {
776 compatible = "fsl,dpaa 742 compatible = "fsl,dpaa2-ptp";
777 reg = <0x0 0x8b95000 0 743 reg = <0x0 0x8b95000 0x0 0x100>;
778 clocks = <&clockgen QO 744 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
779 QO 745 QORIQ_CLK_PLL_DIV(1)>;
780 little-endian; 746 little-endian;
781 fsl,extts-fifo; 747 fsl,extts-fifo;
782 }; 748 };
783 749
784 emdio1: mdio@8b96000 { 750 emdio1: mdio@8b96000 {
785 compatible = "fsl,fman 751 compatible = "fsl,fman-memac-mdio";
786 reg = <0x0 0x8b96000 0 752 reg = <0x0 0x8b96000 0x0 0x1000>;
787 little-endian; 753 little-endian;
788 #address-cells = <1>; 754 #address-cells = <1>;
789 #size-cells = <0>; 755 #size-cells = <0>;
790 clock-frequency = <250 <<
791 clocks = <&clockgen QO <<
792 QO <<
793 status = "disabled"; 756 status = "disabled";
794 }; 757 };
795 758
796 emdio2: mdio@8b97000 { 759 emdio2: mdio@8b97000 {
797 compatible = "fsl,fman 760 compatible = "fsl,fman-memac-mdio";
798 reg = <0x0 0x8b97000 0 761 reg = <0x0 0x8b97000 0x0 0x1000>;
799 little-endian; 762 little-endian;
800 #address-cells = <1>; 763 #address-cells = <1>;
801 #size-cells = <0>; 764 #size-cells = <0>;
802 clock-frequency = <250 <<
803 clocks = <&clockgen QO <<
804 QO <<
805 status = "disabled"; 765 status = "disabled";
806 }; 766 };
807 767
808 pcs_mdio1: mdio@8c07000 { <<
809 compatible = "fsl,fman <<
810 reg = <0x0 0x8c07000 0 <<
811 little-endian; <<
812 #address-cells = <1>; <<
813 #size-cells = <0>; <<
814 status = "disabled"; <<
815 <<
816 pcs1: ethernet-phy@0 { <<
817 reg = <0>; <<
818 }; <<
819 }; <<
820 <<
821 pcs_mdio2: mdio@8c0b000 { 768 pcs_mdio2: mdio@8c0b000 {
822 compatible = "fsl,fman 769 compatible = "fsl,fman-memac-mdio";
823 reg = <0x0 0x8c0b000 0 770 reg = <0x0 0x8c0b000 0x0 0x1000>;
824 little-endian; 771 little-endian;
825 #address-cells = <1>; 772 #address-cells = <1>;
826 #size-cells = <0>; 773 #size-cells = <0>;
827 status = "disabled"; 774 status = "disabled";
828 775
829 pcs2: ethernet-phy@0 { 776 pcs2: ethernet-phy@0 {
830 reg = <0>; 777 reg = <0>;
831 }; 778 };
832 }; 779 };
833 780
834 pcs_mdio3: mdio@8c0f000 { 781 pcs_mdio3: mdio@8c0f000 {
835 compatible = "fsl,fman 782 compatible = "fsl,fman-memac-mdio";
836 reg = <0x0 0x8c0f000 0 783 reg = <0x0 0x8c0f000 0x0 0x1000>;
837 little-endian; 784 little-endian;
838 #address-cells = <1>; 785 #address-cells = <1>;
839 #size-cells = <0>; 786 #size-cells = <0>;
840 status = "disabled"; 787 status = "disabled";
841 788
842 pcs3_0: ethernet-phy@0 789 pcs3_0: ethernet-phy@0 {
843 reg = <0>; 790 reg = <0>;
844 }; 791 };
845 792
846 pcs3_1: ethernet-phy@1 793 pcs3_1: ethernet-phy@1 {
847 reg = <1>; 794 reg = <1>;
848 }; 795 };
849 796
850 pcs3_2: ethernet-phy@2 797 pcs3_2: ethernet-phy@2 {
851 reg = <2>; 798 reg = <2>;
852 }; 799 };
853 800
854 pcs3_3: ethernet-phy@3 801 pcs3_3: ethernet-phy@3 {
855 reg = <3>; 802 reg = <3>;
856 }; 803 };
857 }; 804 };
858 805
859 pcs_mdio7: mdio@8c1f000 { 806 pcs_mdio7: mdio@8c1f000 {
860 compatible = "fsl,fman 807 compatible = "fsl,fman-memac-mdio";
861 reg = <0x0 0x8c1f000 0 808 reg = <0x0 0x8c1f000 0x0 0x1000>;
862 little-endian; 809 little-endian;
863 #address-cells = <1>; 810 #address-cells = <1>;
864 #size-cells = <0>; 811 #size-cells = <0>;
865 status = "disabled"; 812 status = "disabled";
866 813
867 pcs7_0: ethernet-phy@0 814 pcs7_0: ethernet-phy@0 {
868 reg = <0>; 815 reg = <0>;
869 }; 816 };
870 817
871 pcs7_1: ethernet-phy@1 818 pcs7_1: ethernet-phy@1 {
872 reg = <1>; 819 reg = <1>;
873 }; 820 };
874 821
875 pcs7_2: ethernet-phy@2 822 pcs7_2: ethernet-phy@2 {
876 reg = <2>; 823 reg = <2>;
877 }; 824 };
878 825
879 pcs7_3: ethernet-phy@3 826 pcs7_3: ethernet-phy@3 {
880 reg = <3>; 827 reg = <3>;
881 }; 828 };
882 }; 829 };
883 830
884 cluster1_core0_watchdog: watch !! 831 cluster1_core0_watchdog: wdt@c000000 {
885 compatible = "arm,sp80 !! 832 compatible = "arm,sp805-wdt", "arm,primecell";
886 reg = <0x0 0xc000000 0 833 reg = <0x0 0xc000000 0x0 0x1000>;
887 clocks = <&clockgen QO 834 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
888 QO 835 QORIQ_CLK_PLL_DIV(16)>,
889 <&clockgen QO 836 <&clockgen QORIQ_CLK_PLATFORM_PLL
890 QO 837 QORIQ_CLK_PLL_DIV(16)>;
891 clock-names = "wdog_cl 838 clock-names = "wdog_clk", "apb_pclk";
892 }; 839 };
893 840
894 cluster1_core1_watchdog: watch !! 841 cluster1_core1_watchdog: wdt@c010000 {
895 compatible = "arm,sp80 !! 842 compatible = "arm,sp805-wdt", "arm,primecell";
896 reg = <0x0 0xc010000 0 843 reg = <0x0 0xc010000 0x0 0x1000>;
897 clocks = <&clockgen QO 844 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
898 QO 845 QORIQ_CLK_PLL_DIV(16)>,
899 <&clockgen QO 846 <&clockgen QORIQ_CLK_PLATFORM_PLL
900 QO 847 QORIQ_CLK_PLL_DIV(16)>;
901 clock-names = "wdog_cl 848 clock-names = "wdog_clk", "apb_pclk";
902 }; 849 };
903 850
904 cluster1_core2_watchdog: watch !! 851 cluster1_core2_watchdog: wdt@c020000 {
905 compatible = "arm,sp80 !! 852 compatible = "arm,sp805-wdt", "arm,primecell";
906 reg = <0x0 0xc020000 0 853 reg = <0x0 0xc020000 0x0 0x1000>;
907 clocks = <&clockgen QO 854 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
908 QO 855 QORIQ_CLK_PLL_DIV(16)>,
909 <&clockgen QO 856 <&clockgen QORIQ_CLK_PLATFORM_PLL
910 QO 857 QORIQ_CLK_PLL_DIV(16)>;
911 clock-names = "wdog_cl 858 clock-names = "wdog_clk", "apb_pclk";
912 }; 859 };
913 860
914 cluster1_core3_watchdog: watch !! 861 cluster1_core3_watchdog: wdt@c030000 {
915 compatible = "arm,sp80 !! 862 compatible = "arm,sp805-wdt", "arm,primecell";
916 reg = <0x0 0xc030000 0 863 reg = <0x0 0xc030000 0x0 0x1000>;
917 clocks = <&clockgen QO 864 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
918 QO 865 QORIQ_CLK_PLL_DIV(16)>,
919 <&clockgen QO 866 <&clockgen QORIQ_CLK_PLATFORM_PLL
920 QO 867 QORIQ_CLK_PLL_DIV(16)>;
921 clock-names = "wdog_cl 868 clock-names = "wdog_clk", "apb_pclk";
922 }; 869 };
923 870
924 cluster2_core0_watchdog: watch !! 871 cluster2_core0_watchdog: wdt@c100000 {
925 compatible = "arm,sp80 !! 872 compatible = "arm,sp805-wdt", "arm,primecell";
926 reg = <0x0 0xc100000 0 873 reg = <0x0 0xc100000 0x0 0x1000>;
927 clocks = <&clockgen QO 874 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
928 QO 875 QORIQ_CLK_PLL_DIV(16)>,
929 <&clockgen QO 876 <&clockgen QORIQ_CLK_PLATFORM_PLL
930 QO 877 QORIQ_CLK_PLL_DIV(16)>;
931 clock-names = "wdog_cl 878 clock-names = "wdog_clk", "apb_pclk";
932 }; 879 };
933 880
934 cluster2_core1_watchdog: watch !! 881 cluster2_core1_watchdog: wdt@c110000 {
935 compatible = "arm,sp80 !! 882 compatible = "arm,sp805-wdt", "arm,primecell";
936 reg = <0x0 0xc110000 0 883 reg = <0x0 0xc110000 0x0 0x1000>;
937 clocks = <&clockgen QO 884 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
938 QO 885 QORIQ_CLK_PLL_DIV(16)>,
939 <&clockgen QO 886 <&clockgen QORIQ_CLK_PLATFORM_PLL
940 QO 887 QORIQ_CLK_PLL_DIV(16)>;
941 clock-names = "wdog_cl 888 clock-names = "wdog_clk", "apb_pclk";
942 }; 889 };
943 890
944 cluster2_core2_watchdog: watch !! 891 cluster2_core2_watchdog: wdt@c120000 {
945 compatible = "arm,sp80 !! 892 compatible = "arm,sp805-wdt", "arm,primecell";
946 reg = <0x0 0xc120000 0 893 reg = <0x0 0xc120000 0x0 0x1000>;
947 clocks = <&clockgen QO 894 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
948 QO 895 QORIQ_CLK_PLL_DIV(16)>,
949 <&clockgen QO 896 <&clockgen QORIQ_CLK_PLATFORM_PLL
950 QO 897 QORIQ_CLK_PLL_DIV(16)>;
951 clock-names = "wdog_cl 898 clock-names = "wdog_clk", "apb_pclk";
952 }; 899 };
953 900
954 cluster2_core3_watchdog: watch !! 901 cluster2_core3_watchdog: wdt@c130000 {
955 compatible = "arm,sp80 !! 902 compatible = "arm,sp805-wdt", "arm,primecell";
956 reg = <0x0 0xc130000 0 903 reg = <0x0 0xc130000 0x0 0x1000>;
957 clocks = <&clockgen QO 904 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
958 QO 905 QORIQ_CLK_PLL_DIV(16)>,
959 <&clockgen QO 906 <&clockgen QORIQ_CLK_PLATFORM_PLL
960 QO 907 QORIQ_CLK_PLL_DIV(16)>;
961 clock-names = "wdog_cl 908 clock-names = "wdog_clk", "apb_pclk";
962 }; 909 };
963 910
964 fsl_mc: fsl-mc@80c000000 { 911 fsl_mc: fsl-mc@80c000000 {
965 compatible = "fsl,qori 912 compatible = "fsl,qoriq-mc";
966 reg = <0x00000008 0x0c 913 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
967 <0x00000000 0x08 914 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
968 msi-parent = <&its 0>; !! 915 msi-parent = <&its>;
969 iommu-map = <0 &smmu 0 916 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
970 dma-coherent; 917 dma-coherent;
971 #address-cells = <3>; 918 #address-cells = <3>;
972 #size-cells = <1>; 919 #size-cells = <1>;
973 920
974 /* 921 /*
975 * Region type 0x0 - M 922 * Region type 0x0 - MC portals
976 * Region type 0x1 - Q 923 * Region type 0x1 - QBMAN portals
977 */ 924 */
978 ranges = <0x0 0x0 0x0 925 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
979 0x1 0x0 0x0 926 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
980 927
981 dpmacs { 928 dpmacs {
982 #address-cells 929 #address-cells = <1>;
983 #size-cells = 930 #size-cells = <0>;
984 931
985 dpmac1: ethern 932 dpmac1: ethernet@1 {
986 compat 933 compatible = "fsl,qoriq-mc-dpmac";
987 reg = 934 reg = <1>;
988 }; 935 };
989 936
990 dpmac2: ethern 937 dpmac2: ethernet@2 {
991 compat 938 compatible = "fsl,qoriq-mc-dpmac";
992 reg = 939 reg = <2>;
993 }; 940 };
994 941
995 dpmac3: ethern 942 dpmac3: ethernet@3 {
996 compat 943 compatible = "fsl,qoriq-mc-dpmac";
997 reg = 944 reg = <3>;
998 }; 945 };
999 946
1000 dpmac4: ether 947 dpmac4: ethernet@4 {
1001 compa 948 compatible = "fsl,qoriq-mc-dpmac";
1002 reg = 949 reg = <4>;
1003 }; 950 };
1004 951
1005 dpmac5: ether 952 dpmac5: ethernet@5 {
1006 compa 953 compatible = "fsl,qoriq-mc-dpmac";
1007 reg = 954 reg = <5>;
1008 }; 955 };
1009 956
1010 dpmac6: ether 957 dpmac6: ethernet@6 {
1011 compa 958 compatible = "fsl,qoriq-mc-dpmac";
1012 reg = 959 reg = <6>;
1013 }; 960 };
1014 961
1015 dpmac7: ether 962 dpmac7: ethernet@7 {
1016 compa 963 compatible = "fsl,qoriq-mc-dpmac";
1017 reg = 964 reg = <7>;
1018 }; 965 };
1019 966
1020 dpmac8: ether 967 dpmac8: ethernet@8 {
1021 compa 968 compatible = "fsl,qoriq-mc-dpmac";
1022 reg = 969 reg = <8>;
1023 }; 970 };
1024 971
1025 dpmac9: ether 972 dpmac9: ethernet@9 {
1026 compa 973 compatible = "fsl,qoriq-mc-dpmac";
1027 reg = 974 reg = <9>;
1028 }; 975 };
1029 976
1030 dpmac10: ethe 977 dpmac10: ethernet@a {
1031 compa 978 compatible = "fsl,qoriq-mc-dpmac";
1032 reg = 979 reg = <0xa>;
1033 }; 980 };
1034 }; 981 };
1035 }; 982 };
1036 983
1037 rcpm: wakeup-controller@1e340 !! 984 rcpm: power-controller@1e34040 {
1038 compatible = "fsl,ls1 985 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1039 reg = <0x0 0x1e34040 986 reg = <0x0 0x1e34040 0x0 0x18>;
1040 #fsl,rcpm-wakeup-cell 987 #fsl,rcpm-wakeup-cells = <6>;
1041 little-endian; 988 little-endian;
1042 }; 989 };
1043 990
1044 ftm_alarm0: rtc@2800000 { !! 991 ftm_alarm0: timer@2800000 {
1045 compatible = "fsl,ls1 992 compatible = "fsl,ls1088a-ftm-alarm";
1046 reg = <0x0 0x2800000 993 reg = <0x0 0x2800000 0x0 0x10000>;
1047 fsl,rcpm-wakeup = <&r 994 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1048 interrupts = <GIC_SPI 995 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1049 }; 996 };
1050 }; 997 };
1051 998
1052 firmware { 999 firmware {
1053 optee { 1000 optee {
1054 compatible = "linaro, 1001 compatible = "linaro,optee-tz";
1055 method = "smc"; 1002 method = "smc";
1056 }; 1003 };
1057 }; 1004 };
1058 }; 1005 };
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