1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 * 4 *
5 * Copyright 2017-2020 NXP !! 5 * Copyright 2017 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
11 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
13 12
14 / { 13 / {
15 compatible = "fsl,ls1088a"; 14 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
17 #address-cells = <2>; 16 #address-cells = <2>;
18 #size-cells = <2>; 17 #size-cells = <2>;
19 18
20 aliases { 19 aliases {
21 crypto = &crypto; 20 crypto = &crypto;
22 rtc1 = &ftm_alarm0; <<
23 }; 21 };
24 22
25 cpus { 23 cpus {
26 #address-cells = <1>; 24 #address-cells = <1>;
27 #size-cells = <0>; 25 #size-cells = <0>;
28 26
29 /* We have 2 clusters having 4 27 /* We have 2 clusters having 4 Cortex-A53 cores each */
30 cpu0: cpu@0 { 28 cpu0: cpu@0 {
31 device_type = "cpu"; 29 device_type = "cpu";
32 compatible = "arm,cort 30 compatible = "arm,cortex-a53";
33 reg = <0x0>; 31 reg = <0x0>;
34 clocks = <&clockgen QO !! 32 clocks = <&clockgen 1 0>;
35 cpu-idle-states = <&CP 33 cpu-idle-states = <&CPU_PH20>;
36 #cooling-cells = <2>; 34 #cooling-cells = <2>;
37 }; 35 };
38 36
39 cpu1: cpu@1 { 37 cpu1: cpu@1 {
40 device_type = "cpu"; 38 device_type = "cpu";
41 compatible = "arm,cort 39 compatible = "arm,cortex-a53";
42 reg = <0x1>; 40 reg = <0x1>;
43 clocks = <&clockgen QO !! 41 clocks = <&clockgen 1 0>;
44 cpu-idle-states = <&CP 42 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>; 43 #cooling-cells = <2>;
46 }; 44 };
47 45
48 cpu2: cpu@2 { 46 cpu2: cpu@2 {
49 device_type = "cpu"; 47 device_type = "cpu";
50 compatible = "arm,cort 48 compatible = "arm,cortex-a53";
51 reg = <0x2>; 49 reg = <0x2>;
52 clocks = <&clockgen QO !! 50 clocks = <&clockgen 1 0>;
53 cpu-idle-states = <&CP 51 cpu-idle-states = <&CPU_PH20>;
54 #cooling-cells = <2>; 52 #cooling-cells = <2>;
55 }; 53 };
56 54
57 cpu3: cpu@3 { 55 cpu3: cpu@3 {
58 device_type = "cpu"; 56 device_type = "cpu";
59 compatible = "arm,cort 57 compatible = "arm,cortex-a53";
60 reg = <0x3>; 58 reg = <0x3>;
61 clocks = <&clockgen QO !! 59 clocks = <&clockgen 1 0>;
62 cpu-idle-states = <&CP 60 cpu-idle-states = <&CPU_PH20>;
63 #cooling-cells = <2>; 61 #cooling-cells = <2>;
64 }; 62 };
65 63
66 cpu4: cpu@100 { 64 cpu4: cpu@100 {
67 device_type = "cpu"; 65 device_type = "cpu";
68 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
69 reg = <0x100>; 67 reg = <0x100>;
70 clocks = <&clockgen QO !! 68 clocks = <&clockgen 1 1>;
71 cpu-idle-states = <&CP 69 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 70 #cooling-cells = <2>;
73 }; 71 };
74 72
75 cpu5: cpu@101 { 73 cpu5: cpu@101 {
76 device_type = "cpu"; 74 device_type = "cpu";
77 compatible = "arm,cort 75 compatible = "arm,cortex-a53";
78 reg = <0x101>; 76 reg = <0x101>;
79 clocks = <&clockgen QO !! 77 clocks = <&clockgen 1 1>;
80 cpu-idle-states = <&CP 78 cpu-idle-states = <&CPU_PH20>;
81 #cooling-cells = <2>; 79 #cooling-cells = <2>;
82 }; 80 };
83 81
84 cpu6: cpu@102 { 82 cpu6: cpu@102 {
85 device_type = "cpu"; 83 device_type = "cpu";
86 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
87 reg = <0x102>; 85 reg = <0x102>;
88 clocks = <&clockgen QO !! 86 clocks = <&clockgen 1 1>;
89 cpu-idle-states = <&CP 87 cpu-idle-states = <&CPU_PH20>;
90 #cooling-cells = <2>; 88 #cooling-cells = <2>;
91 }; 89 };
92 90
93 cpu7: cpu@103 { 91 cpu7: cpu@103 {
94 device_type = "cpu"; 92 device_type = "cpu";
95 compatible = "arm,cort 93 compatible = "arm,cortex-a53";
96 reg = <0x103>; 94 reg = <0x103>;
97 clocks = <&clockgen QO !! 95 clocks = <&clockgen 1 1>;
98 cpu-idle-states = <&CP 96 cpu-idle-states = <&CPU_PH20>;
99 #cooling-cells = <2>; 97 #cooling-cells = <2>;
100 }; 98 };
101 99
102 CPU_PH20: cpu-ph20 { 100 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle 101 compatible = "arm,idle-state";
104 idle-state-name = "PH2 102 idle-state-name = "PH20";
105 arm,psci-suspend-param 103 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <10 104 entry-latency-us = <1000>;
107 exit-latency-us = <100 105 exit-latency-us = <1000>;
108 min-residency-us = <30 106 min-residency-us = <3000>;
109 }; 107 };
110 }; 108 };
111 109
112 gic: interrupt-controller@6000000 { 110 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3"; 111 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>; 112 #interrupt-cells = <3>;
115 interrupt-controller; 113 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x1000 114 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x1000 115 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000 116 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000 117 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x2000 118 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <GIC_PPI 9 IRQ_TY !! 119 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>; 120 #address-cells = <2>;
123 #size-cells = <2>; 121 #size-cells = <2>;
124 ranges; 122 ranges;
125 123
126 its: msi-controller@6020000 { !! 124 its: gic-its@6020000 {
127 compatible = "arm,gic- 125 compatible = "arm,gic-v3-its";
128 msi-controller; 126 msi-controller;
129 #msi-cells = <1>; <<
130 reg = <0x0 0x6020000 0 127 reg = <0x0 0x6020000 0 0x20000>;
131 }; 128 };
132 }; 129 };
133 130
134 thermal-zones { 131 thermal-zones {
135 cluster-thermal { !! 132 cpu_thermal: cpu-thermal {
136 polling-delay-passive 133 polling-delay-passive = <1000>;
137 polling-delay = <5000> 134 polling-delay = <5000>;
138 thermal-sensors = <&tm 135 thermal-sensors = <&tmu 0>;
139 136
140 trips { 137 trips {
141 core_cluster_a !! 138 cpu_alert: cpu-alert {
142 temper 139 temperature = <85000>;
143 hyster 140 hysteresis = <2000>;
144 type = 141 type = "passive";
145 }; 142 };
146 143
147 core-cluster-c !! 144 cpu_crit: cpu-crit {
148 temper 145 temperature = <95000>;
149 hyster 146 hysteresis = <2000>;
150 type = 147 type = "critical";
151 }; 148 };
152 }; 149 };
153 150
154 cooling-maps { 151 cooling-maps {
155 map0 { 152 map0 {
156 trip = !! 153 trip = <&cpu_alert>;
157 coolin 154 cooling-device =
158 155 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 156 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 157 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 158 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 159 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163 160 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 161 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
165 162 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
166 }; 163 };
167 }; 164 };
168 }; 165 };
169 <<
170 soc-thermal { <<
171 polling-delay-passive <<
172 polling-delay = <5000> <<
173 thermal-sensors = <&tm <<
174 <<
175 trips { <<
176 soc-crit { <<
177 temper <<
178 hyster <<
179 type = <<
180 }; <<
181 }; <<
182 }; <<
183 }; 166 };
184 167
185 timer { 168 timer {
186 compatible = "arm,armv8-timer" 169 compatible = "arm,armv8-timer";
187 interrupts = <GIC_PPI 13 IRQ_T !! 170 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
188 <GIC_PPI 14 IRQ_T !! 171 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
189 <GIC_PPI 11 IRQ_T !! 172 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
190 <GIC_PPI 10 IRQ_T !! 173 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
191 }; <<
192 <<
193 pmu { <<
194 compatible = "arm,cortex-a53-p <<
195 interrupts = <GIC_PPI 7 IRQ_TY <<
196 }; 174 };
197 175
198 psci { 176 psci {
199 compatible = "arm,psci-0.2"; 177 compatible = "arm,psci-0.2";
200 method = "smc"; 178 method = "smc";
201 }; 179 };
202 180
203 sysclk: sysclk { 181 sysclk: sysclk {
204 compatible = "fixed-clock"; 182 compatible = "fixed-clock";
205 #clock-cells = <0>; 183 #clock-cells = <0>;
206 clock-frequency = <100000000>; 184 clock-frequency = <100000000>;
207 clock-output-names = "sysclk"; 185 clock-output-names = "sysclk";
208 }; 186 };
209 187
210 reboot { <<
211 compatible = "syscon-reboot"; <<
212 regmap = <&reset>; <<
213 offset = <0x0>; <<
214 mask = <0x02>; <<
215 }; <<
216 <<
217 soc { 188 soc {
218 compatible = "simple-bus"; 189 compatible = "simple-bus";
219 #address-cells = <2>; 190 #address-cells = <2>;
220 #size-cells = <2>; 191 #size-cells = <2>;
221 ranges; 192 ranges;
222 dma-ranges = <0x0 0x0 0x0 0x0 193 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
223 194
224 clockgen: clocking@1300000 { 195 clockgen: clocking@1300000 {
225 compatible = "fsl,ls10 196 compatible = "fsl,ls1088a-clockgen";
226 reg = <0 0x1300000 0 0 197 reg = <0 0x1300000 0 0xa0000>;
227 #clock-cells = <2>; 198 #clock-cells = <2>;
228 clocks = <&sysclk>; 199 clocks = <&sysclk>;
229 }; 200 };
230 201
231 dcfg: dcfg@1e00000 { 202 dcfg: dcfg@1e00000 {
232 compatible = "fsl,ls10 203 compatible = "fsl,ls1088a-dcfg", "syscon";
233 reg = <0x0 0x1e00000 0 204 reg = <0x0 0x1e00000 0x0 0x10000>;
234 little-endian; 205 little-endian;
235 }; 206 };
236 207
237 reset: syscon@1e60000 { <<
238 compatible = "fsl,ls10 <<
239 reg = <0x0 0x1e60000 0 <<
240 }; <<
241 <<
242 isc: syscon@1f70000 { <<
243 compatible = "fsl,ls10 <<
244 reg = <0x0 0x1f70000 0 <<
245 little-endian; <<
246 #address-cells = <1>; <<
247 #size-cells = <1>; <<
248 ranges = <0x0 0x0 0x1f <<
249 <<
250 extirq: interrupt-cont <<
251 compatible = " <<
252 #interrupt-cel <<
253 #address-cells <<
254 interrupt-cont <<
255 reg = <0x14 4> <<
256 interrupt-map <<
257 <0 0 & <<
258 <1 0 & <<
259 <2 0 & <<
260 <3 0 & <<
261 <4 0 & <<
262 <5 0 & <<
263 <6 0 & <<
264 <7 0 & <<
265 <8 0 & <<
266 <9 0 & <<
267 <10 0 <<
268 <11 0 <<
269 interrupt-map- <<
270 }; <<
271 }; <<
272 <<
273 sfp: efuse@1e80000 { <<
274 compatible = "fsl,ls10 <<
275 reg = <0x0 0x1e80000 0 <<
276 clocks = <&clockgen QO <<
277 QO <<
278 clock-names = "sfp"; <<
279 }; <<
280 <<
281 tmu: tmu@1f80000 { 208 tmu: tmu@1f80000 {
282 compatible = "fsl,qori 209 compatible = "fsl,qoriq-tmu";
283 reg = <0x0 0x1f80000 0 210 reg = <0x0 0x1f80000 0x0 0x10000>;
284 interrupts = <GIC_SPI !! 211 interrupts = <0 23 0x4>;
285 fsl,tmu-range = <0xb00 !! 212 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
286 fsl,tmu-calibration = 213 fsl,tmu-calibration =
287 /* Calibration 214 /* Calibration data group 1 */
288 <0x00000000 0x !! 215 <0x00000000 0x00000026
289 <0x00000001 0x !! 216 0x00000001 0x0000002d
290 <0x00000002 0x !! 217 0x00000002 0x00000032
291 <0x00000003 0x !! 218 0x00000003 0x00000039
292 <0x00000004 0x !! 219 0x00000004 0x0000003f
293 <0x00000005 0x !! 220 0x00000005 0x00000046
294 <0x00000006 0x !! 221 0x00000006 0x0000004d
295 <0x00000007 0x !! 222 0x00000007 0x00000054
296 <0x00000008 0x !! 223 0x00000008 0x0000005a
297 <0x00000009 0x !! 224 0x00000009 0x00000061
298 <0x0000000a 0x !! 225 0x0000000a 0x0000006a
299 <0x0000000b 0x !! 226 0x0000000b 0x00000071
300 /* Calibration 227 /* Calibration data group 2 */
301 <0x00010000 0x !! 228 0x00010000 0x00000025
302 <0x00010001 0x !! 229 0x00010001 0x0000002c
303 <0x00010002 0x !! 230 0x00010002 0x00000035
304 <0x00010003 0x !! 231 0x00010003 0x0000003d
305 <0x00010004 0x !! 232 0x00010004 0x00000045
306 <0x00010005 0x !! 233 0x00010005 0x0000004e
307 <0x00010006 0x !! 234 0x00010006 0x00000057
308 <0x00010007 0x !! 235 0x00010007 0x00000061
309 <0x00010008 0x !! 236 0x00010008 0x0000006b
310 <0x00010009 0x !! 237 0x00010009 0x00000076
311 /* Calibration 238 /* Calibration data group 3 */
312 <0x00020000 0x !! 239 0x00020000 0x00000029
313 <0x00020001 0x !! 240 0x00020001 0x00000033
314 <0x00020002 0x !! 241 0x00020002 0x0000003d
315 <0x00020003 0x !! 242 0x00020003 0x00000049
316 <0x00020004 0x !! 243 0x00020004 0x00000056
317 <0x00020005 0x !! 244 0x00020005 0x00000061
318 <0x00020006 0x !! 245 0x00020006 0x0000006d
319 /* Calibration 246 /* Calibration data group 4 */
320 <0x00030000 0x !! 247 0x00030000 0x00000021
321 <0x00030001 0x !! 248 0x00030001 0x0000002a
322 <0x00030002 0x !! 249 0x00030002 0x0000003c
323 <0x00030003 0x !! 250 0x00030003 0x0000004e>;
324 <0x00030004 0x <<
325 <0x00030005 0x <<
326 <0x00030006 0x <<
327 <0x00030007 0x <<
328 little-endian; 251 little-endian;
329 #thermal-sensor-cells 252 #thermal-sensor-cells = <1>;
330 }; 253 };
331 254
332 dspi: spi@2100000 { 255 dspi: spi@2100000 {
333 compatible = "fsl,ls10 256 compatible = "fsl,ls1088a-dspi",
334 "fsl,ls10 257 "fsl,ls1021a-v1.0-dspi";
335 #address-cells = <1>; 258 #address-cells = <1>;
336 #size-cells = <0>; 259 #size-cells = <0>;
337 reg = <0x0 0x2100000 0 260 reg = <0x0 0x2100000 0x0 0x10000>;
338 interrupts = <GIC_SPI 261 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
339 clock-names = "dspi"; 262 clock-names = "dspi";
340 clocks = <&clockgen QO !! 263 clocks = <&clockgen 4 1>;
341 QO <<
342 spi-num-chipselects = 264 spi-num-chipselects = <6>;
343 status = "disabled"; 265 status = "disabled";
344 }; 266 };
345 267
346 duart0: serial@21c0500 { 268 duart0: serial@21c0500 {
347 compatible = "fsl,ns16 269 compatible = "fsl,ns16550", "ns16550a";
348 reg = <0x0 0x21c0500 0 270 reg = <0x0 0x21c0500 0x0 0x100>;
349 clocks = <&clockgen QO !! 271 clocks = <&clockgen 4 3>;
350 QO !! 272 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
351 interrupts = <GIC_SPI <<
352 status = "disabled"; 273 status = "disabled";
353 }; 274 };
354 275
355 duart1: serial@21c0600 { 276 duart1: serial@21c0600 {
356 compatible = "fsl,ns16 277 compatible = "fsl,ns16550", "ns16550a";
357 reg = <0x0 0x21c0600 0 278 reg = <0x0 0x21c0600 0x0 0x100>;
358 clocks = <&clockgen QO !! 279 clocks = <&clockgen 4 3>;
359 QO !! 280 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
360 interrupts = <GIC_SPI <<
361 status = "disabled"; 281 status = "disabled";
362 }; 282 };
363 283
364 gpio0: gpio@2300000 { 284 gpio0: gpio@2300000 {
365 compatible = "fsl,ls10 285 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
366 reg = <0x0 0x2300000 0 286 reg = <0x0 0x2300000 0x0 0x10000>;
367 interrupts = <GIC_SPI !! 287 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
368 little-endian; 288 little-endian;
369 gpio-controller; 289 gpio-controller;
370 #gpio-cells = <2>; 290 #gpio-cells = <2>;
371 interrupt-controller; 291 interrupt-controller;
372 #interrupt-cells = <2> 292 #interrupt-cells = <2>;
373 }; 293 };
374 294
375 gpio1: gpio@2310000 { 295 gpio1: gpio@2310000 {
376 compatible = "fsl,ls10 296 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
377 reg = <0x0 0x2310000 0 297 reg = <0x0 0x2310000 0x0 0x10000>;
378 interrupts = <GIC_SPI !! 298 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
379 little-endian; 299 little-endian;
380 gpio-controller; 300 gpio-controller;
381 #gpio-cells = <2>; 301 #gpio-cells = <2>;
382 interrupt-controller; 302 interrupt-controller;
383 #interrupt-cells = <2> 303 #interrupt-cells = <2>;
384 }; 304 };
385 305
386 gpio2: gpio@2320000 { 306 gpio2: gpio@2320000 {
387 compatible = "fsl,ls10 307 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0 308 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI !! 309 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
390 little-endian; 310 little-endian;
391 gpio-controller; 311 gpio-controller;
392 #gpio-cells = <2>; 312 #gpio-cells = <2>;
393 interrupt-controller; 313 interrupt-controller;
394 #interrupt-cells = <2> 314 #interrupt-cells = <2>;
395 }; 315 };
396 316
397 gpio3: gpio@2330000 { 317 gpio3: gpio@2330000 {
398 compatible = "fsl,ls10 318 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
399 reg = <0x0 0x2330000 0 319 reg = <0x0 0x2330000 0x0 0x10000>;
400 interrupts = <GIC_SPI !! 320 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
401 little-endian; 321 little-endian;
402 gpio-controller; 322 gpio-controller;
403 #gpio-cells = <2>; 323 #gpio-cells = <2>;
404 interrupt-controller; 324 interrupt-controller;
405 #interrupt-cells = <2> 325 #interrupt-cells = <2>;
406 }; 326 };
407 327
408 ifc: memory-controller@2240000 !! 328 ifc: ifc@2240000 {
409 compatible = "fsl,ifc" !! 329 compatible = "fsl,ifc", "simple-bus";
410 reg = <0x0 0x2240000 0 330 reg = <0x0 0x2240000 0x0 0x20000>;
411 interrupts = <GIC_SPI !! 331 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
412 little-endian; 332 little-endian;
413 #address-cells = <2>; 333 #address-cells = <2>;
414 #size-cells = <1>; 334 #size-cells = <1>;
415 status = "disabled"; 335 status = "disabled";
416 }; 336 };
417 337
418 i2c0: i2c@2000000 { 338 i2c0: i2c@2000000 {
419 compatible = "fsl,vf61 339 compatible = "fsl,vf610-i2c";
420 #address-cells = <1>; 340 #address-cells = <1>;
421 #size-cells = <0>; 341 #size-cells = <0>;
422 reg = <0x0 0x2000000 0 342 reg = <0x0 0x2000000 0x0 0x10000>;
423 interrupts = <GIC_SPI !! 343 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen QO !! 344 clocks = <&clockgen 4 7>;
425 QO <<
426 status = "disabled"; 345 status = "disabled";
427 }; 346 };
428 347
429 i2c1: i2c@2010000 { 348 i2c1: i2c@2010000 {
430 compatible = "fsl,vf61 349 compatible = "fsl,vf610-i2c";
431 #address-cells = <1>; 350 #address-cells = <1>;
432 #size-cells = <0>; 351 #size-cells = <0>;
433 reg = <0x0 0x2010000 0 352 reg = <0x0 0x2010000 0x0 0x10000>;
434 interrupts = <GIC_SPI !! 353 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clockgen QO !! 354 clocks = <&clockgen 4 7>;
436 QO <<
437 status = "disabled"; 355 status = "disabled";
438 }; 356 };
439 357
440 i2c2: i2c@2020000 { 358 i2c2: i2c@2020000 {
441 compatible = "fsl,vf61 359 compatible = "fsl,vf610-i2c";
442 #address-cells = <1>; 360 #address-cells = <1>;
443 #size-cells = <0>; 361 #size-cells = <0>;
444 reg = <0x0 0x2020000 0 362 reg = <0x0 0x2020000 0x0 0x10000>;
445 interrupts = <GIC_SPI !! 363 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen QO !! 364 clocks = <&clockgen 4 7>;
447 QO <<
448 status = "disabled"; 365 status = "disabled";
449 }; 366 };
450 367
451 i2c3: i2c@2030000 { 368 i2c3: i2c@2030000 {
452 compatible = "fsl,vf61 369 compatible = "fsl,vf610-i2c";
453 #address-cells = <1>; 370 #address-cells = <1>;
454 #size-cells = <0>; 371 #size-cells = <0>;
455 reg = <0x0 0x2030000 0 372 reg = <0x0 0x2030000 0x0 0x10000>;
456 interrupts = <GIC_SPI !! 373 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clockgen QO !! 374 clocks = <&clockgen 4 7>;
458 QO <<
459 status = "disabled"; 375 status = "disabled";
460 }; 376 };
461 377
462 qspi: spi@20c0000 { !! 378 esdhc: esdhc@2140000 {
463 compatible = "fsl,ls20 <<
464 #address-cells = <1>; <<
465 #size-cells = <0>; <<
466 reg = <0x0 0x20c0000 0 <<
467 <0x0 0x20000000 <<
468 reg-names = "QuadSPI", <<
469 interrupts = <GIC_SPI <<
470 clock-names = "qspi_en <<
471 clocks = <&clockgen QO <<
472 QO <<
473 <&clockgen QO <<
474 QO <<
475 status = "disabled"; <<
476 }; <<
477 <<
478 esdhc: mmc@2140000 { <<
479 compatible = "fsl,ls10 379 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
480 reg = <0x0 0x2140000 0 380 reg = <0x0 0x2140000 0x0 0x10000>;
481 interrupts = <GIC_SPI !! 381 interrupts = <0 28 0x4>; /* Level high type */
482 clock-frequency = <0>; 382 clock-frequency = <0>;
483 clocks = <&clockgen QO <<
484 voltage-ranges = <1800 383 voltage-ranges = <1800 1800 3300 3300>;
485 sdhci,auto-cmd12; 384 sdhci,auto-cmd12;
486 little-endian; 385 little-endian;
487 bus-width = <4>; 386 bus-width = <4>;
488 status = "disabled"; 387 status = "disabled";
489 }; 388 };
490 389
491 usb0: usb@3100000 { !! 390 usb0: usb3@3100000 {
492 compatible = "snps,dwc 391 compatible = "snps,dwc3";
493 reg = <0x0 0x3100000 0 392 reg = <0x0 0x3100000 0x0 0x10000>;
494 interrupts = <GIC_SPI !! 393 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 dr_mode = "host"; 394 dr_mode = "host";
496 snps,quirk-frame-lengt 395 snps,quirk-frame-length-adjustment = <0x20>;
497 snps,dis_rxdet_inp3_qu 396 snps,dis_rxdet_inp3_quirk;
498 snps,incr-burst-type-a 397 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
499 status = "disabled"; 398 status = "disabled";
500 }; 399 };
501 400
502 usb1: usb@3110000 { !! 401 usb1: usb3@3110000 {
503 compatible = "snps,dwc 402 compatible = "snps,dwc3";
504 reg = <0x0 0x3110000 0 403 reg = <0x0 0x3110000 0x0 0x10000>;
505 interrupts = <GIC_SPI !! 404 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 dr_mode = "host"; 405 dr_mode = "host";
507 snps,quirk-frame-lengt 406 snps,quirk-frame-length-adjustment = <0x20>;
508 snps,dis_rxdet_inp3_qu 407 snps,dis_rxdet_inp3_quirk;
509 snps,incr-burst-type-a <<
510 status = "disabled"; 408 status = "disabled";
511 }; 409 };
512 410
513 sata: sata@3200000 { 411 sata: sata@3200000 {
514 compatible = "fsl,ls10 412 compatible = "fsl,ls1088a-ahci";
515 reg = <0x0 0x3200000 0 413 reg = <0x0 0x3200000 0x0 0x10000>,
516 <0x7 0x100520 414 <0x7 0x100520 0x0 0x4>;
517 reg-names = "ahci", "s 415 reg-names = "ahci", "sata-ecc";
518 interrupts = <GIC_SPI !! 416 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clockgen QO !! 417 clocks = <&clockgen 4 3>;
520 QO <<
521 dma-coherent; 418 dma-coherent;
522 status = "disabled"; 419 status = "disabled";
523 }; 420 };
524 421
525 crypto: crypto@8000000 { 422 crypto: crypto@8000000 {
526 compatible = "fsl,sec- 423 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
527 fsl,sec-era = <8>; 424 fsl,sec-era = <8>;
528 #address-cells = <1>; 425 #address-cells = <1>;
529 #size-cells = <1>; 426 #size-cells = <1>;
530 ranges = <0x0 0x00 0x8 427 ranges = <0x0 0x00 0x8000000 0x100000>;
531 reg = <0x00 0x8000000 428 reg = <0x00 0x8000000 0x0 0x100000>;
532 interrupts = <GIC_SPI 429 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
533 dma-coherent; 430 dma-coherent;
534 431
535 sec_jr0: jr@10000 { 432 sec_jr0: jr@10000 {
536 compatible = " 433 compatible = "fsl,sec-v5.0-job-ring",
537 " 434 "fsl,sec-v4.0-job-ring";
538 reg = <0x10000 !! 435 reg = <0x10000 0x10000>;
539 interrupts = < 436 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
540 }; 437 };
541 438
542 sec_jr1: jr@20000 { 439 sec_jr1: jr@20000 {
543 compatible = " 440 compatible = "fsl,sec-v5.0-job-ring",
544 " 441 "fsl,sec-v4.0-job-ring";
545 reg = <0x20000 !! 442 reg = <0x20000 0x10000>;
546 interrupts = < 443 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
547 }; 444 };
548 445
549 sec_jr2: jr@30000 { 446 sec_jr2: jr@30000 {
550 compatible = " 447 compatible = "fsl,sec-v5.0-job-ring",
551 " 448 "fsl,sec-v4.0-job-ring";
552 reg = <0x30000 !! 449 reg = <0x30000 0x10000>;
553 interrupts = < 450 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
554 }; 451 };
555 452
556 sec_jr3: jr@40000 { 453 sec_jr3: jr@40000 {
557 compatible = " 454 compatible = "fsl,sec-v5.0-job-ring",
558 " 455 "fsl,sec-v4.0-job-ring";
559 reg = <0x40000 !! 456 reg = <0x40000 0x10000>;
560 interrupts = < 457 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
561 }; 458 };
562 }; 459 };
563 460
564 pcie1: pcie@3400000 { !! 461 pcie@3400000 {
565 compatible = "fsl,ls10 462 compatible = "fsl,ls1088a-pcie";
566 reg = <0x00 0x03400000 !! 463 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
567 <0x20 0x00000000 !! 464 0x20 0x00000000 0x0 0x00002000>; /* configuration space */
568 reg-names = "regs", "c 465 reg-names = "regs", "config";
569 interrupts = <GIC_SPI !! 466 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
570 interrupt-names = "aer 467 interrupt-names = "aer";
571 #address-cells = <3>; 468 #address-cells = <3>;
572 #size-cells = <2>; 469 #size-cells = <2>;
573 device_type = "pci"; 470 device_type = "pci";
574 dma-coherent; 471 dma-coherent;
575 num-viewport = <256>; 472 num-viewport = <256>;
576 bus-range = <0x0 0xff> 473 bus-range = <0x0 0xff>;
577 ranges = <0x81000000 0 474 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
578 0x82000000 0 475 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
579 msi-parent = <&its 0>; !! 476 msi-parent = <&its>;
580 #interrupt-cells = <1> 477 #interrupt-cells = <1>;
581 interrupt-map-mask = < 478 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0000 479 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 480 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 481 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
585 <0000 482 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
586 iommu-map = <0 &smmu 0 <<
587 status = "disabled"; 483 status = "disabled";
588 }; 484 };
589 485
590 pcie_ep1: pcie-ep@3400000 { !! 486 pcie@3500000 {
591 compatible = "fsl,ls10 <<
592 reg = <0x00 0x03400000 <<
593 <0x20 0x00000000 <<
594 reg-names = "regs", "a <<
595 interrupts = <GIC_SPI <<
596 interrupt-names = "pme <<
597 num-ib-windows = <24>; <<
598 num-ob-windows = <256> <<
599 max-functions = /bits/ <<
600 status = "disabled"; <<
601 }; <<
602 <<
603 pcie2: pcie@3500000 { <<
604 compatible = "fsl,ls10 487 compatible = "fsl,ls1088a-pcie";
605 reg = <0x00 0x03500000 !! 488 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
606 <0x28 0x00000000 !! 489 0x28 0x00000000 0x0 0x00002000>; /* configuration space */
607 reg-names = "regs", "c 490 reg-names = "regs", "config";
608 interrupts = <GIC_SPI !! 491 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
609 interrupt-names = "aer 492 interrupt-names = "aer";
610 #address-cells = <3>; 493 #address-cells = <3>;
611 #size-cells = <2>; 494 #size-cells = <2>;
612 device_type = "pci"; 495 device_type = "pci";
613 dma-coherent; 496 dma-coherent;
614 num-viewport = <6>; 497 num-viewport = <6>;
615 bus-range = <0x0 0xff> 498 bus-range = <0x0 0xff>;
616 ranges = <0x81000000 0 499 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
617 0x82000000 0 500 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
618 msi-parent = <&its 0>; !! 501 msi-parent = <&its>;
619 #interrupt-cells = <1> 502 #interrupt-cells = <1>;
620 interrupt-map-mask = < 503 interrupt-map-mask = <0 0 0 7>;
621 interrupt-map = <0000 504 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 505 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 506 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
624 <0000 507 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
625 iommu-map = <0 &smmu 0 <<
626 status = "disabled"; <<
627 }; <<
628 <<
629 pcie_ep2: pcie-ep@3500000 { <<
630 compatible = "fsl,ls10 <<
631 reg = <0x00 0x03500000 <<
632 <0x28 0x00000000 <<
633 reg-names = "regs", "a <<
634 interrupts = <GIC_SPI <<
635 interrupt-names = "pme <<
636 num-ib-windows = <6>; <<
637 num-ob-windows = <6>; <<
638 status = "disabled"; 508 status = "disabled";
639 }; 509 };
640 510
641 pcie3: pcie@3600000 { !! 511 pcie@3600000 {
642 compatible = "fsl,ls10 512 compatible = "fsl,ls1088a-pcie";
643 reg = <0x00 0x03600000 !! 513 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
644 <0x30 0x00000000 !! 514 0x30 0x00000000 0x0 0x00002000>; /* configuration space */
645 reg-names = "regs", "c 515 reg-names = "regs", "config";
646 interrupts = <GIC_SPI !! 516 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
647 interrupt-names = "aer 517 interrupt-names = "aer";
648 #address-cells = <3>; 518 #address-cells = <3>;
649 #size-cells = <2>; 519 #size-cells = <2>;
650 device_type = "pci"; 520 device_type = "pci";
651 dma-coherent; 521 dma-coherent;
652 num-viewport = <6>; 522 num-viewport = <6>;
653 bus-range = <0x0 0xff> 523 bus-range = <0x0 0xff>;
654 ranges = <0x81000000 0 524 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
655 0x82000000 0 525 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
656 msi-parent = <&its 0>; !! 526 msi-parent = <&its>;
657 #interrupt-cells = <1> 527 #interrupt-cells = <1>;
658 interrupt-map-mask = < 528 interrupt-map-mask = <0 0 0 7>;
659 interrupt-map = <0000 529 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 530 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 531 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
662 <0000 532 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
663 iommu-map = <0 &smmu 0 <<
664 status = "disabled"; <<
665 }; <<
666 <<
667 pcie_ep3: pcie-ep@3600000 { <<
668 compatible = "fsl,ls10 <<
669 reg = <0x00 0x03600000 <<
670 <0x30 0x00000000 <<
671 reg-names = "regs", "a <<
672 interrupts = <GIC_SPI <<
673 interrupt-names = "pme <<
674 num-ib-windows = <6>; <<
675 num-ob-windows = <6>; <<
676 status = "disabled"; 533 status = "disabled";
677 }; 534 };
678 535
679 smmu: iommu@5000000 { 536 smmu: iommu@5000000 {
680 compatible = "arm,mmu- 537 compatible = "arm,mmu-500";
681 reg = <0 0x5000000 0 0 538 reg = <0 0x5000000 0 0x800000>;
682 #iommu-cells = <1>; 539 #iommu-cells = <1>;
683 stream-match-mask = <0 540 stream-match-mask = <0x7C00>;
684 dma-coherent; <<
685 #global-interrupts = < 541 #global-interrupts = <12>;
686 // global 542 // global secure fault
687 interrupts = <GIC_SPI 543 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
688 // combin 544 // combined secure
689 <GIC_SPI 545 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
690 // global 546 // global non-secure fault
691 <GIC_SPI 547 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
692 // combin 548 // combined non-secure
693 <GIC_SPI 549 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
694 // perfor 550 // performance counter interrupts 0-7
695 <GIC_SPI 551 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 552 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 553 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 554 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 555 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 556 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 557 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 558 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
703 // per co 559 // per context interrupt, 64 interrupts
704 <GIC_SPI 560 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 561 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 562 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 563 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 564 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 565 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 566 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 567 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 568 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 569 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 570 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 571 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 572 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 573 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 574 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 575 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 576 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 577 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 578 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 579 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 580 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 581 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 582 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 583 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 584 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 585 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 586 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 587 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 588 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 589 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 590 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 591 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 592 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 593 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 594 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 595 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 596 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 597 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 598 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 599 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 600 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 601 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 602 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 603 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 604 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 605 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 606 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 607 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 608 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 609 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 610 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 611 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 612 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 613 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 614 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 615 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 616 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 617 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 618 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 619 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 620 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 621 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 622 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 623 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
768 }; 624 };
769 625
770 console@8340020 { 626 console@8340020 {
771 compatible = "fsl,dpaa 627 compatible = "fsl,dpaa2-console";
772 reg = <0x00000000 0x08 628 reg = <0x00000000 0x08340020 0 0x2>;
773 }; 629 };
774 630
775 ptp-timer@8b95000 { 631 ptp-timer@8b95000 {
776 compatible = "fsl,dpaa 632 compatible = "fsl,dpaa2-ptp";
777 reg = <0x0 0x8b95000 0 633 reg = <0x0 0x8b95000 0x0 0x100>;
778 clocks = <&clockgen QO !! 634 clocks = <&clockgen 4 0>;
779 QO <<
780 little-endian; 635 little-endian;
781 fsl,extts-fifo; 636 fsl,extts-fifo;
782 }; 637 };
783 638
784 emdio1: mdio@8b96000 { !! 639 cluster1_core0_watchdog: wdt@c000000 {
785 compatible = "fsl,fman <<
786 reg = <0x0 0x8b96000 0 <<
787 little-endian; <<
788 #address-cells = <1>; <<
789 #size-cells = <0>; <<
790 clock-frequency = <250 <<
791 clocks = <&clockgen QO <<
792 QO <<
793 status = "disabled"; <<
794 }; <<
795 <<
796 emdio2: mdio@8b97000 { <<
797 compatible = "fsl,fman <<
798 reg = <0x0 0x8b97000 0 <<
799 little-endian; <<
800 #address-cells = <1>; <<
801 #size-cells = <0>; <<
802 clock-frequency = <250 <<
803 clocks = <&clockgen QO <<
804 QO <<
805 status = "disabled"; <<
806 }; <<
807 <<
808 pcs_mdio1: mdio@8c07000 { <<
809 compatible = "fsl,fman <<
810 reg = <0x0 0x8c07000 0 <<
811 little-endian; <<
812 #address-cells = <1>; <<
813 #size-cells = <0>; <<
814 status = "disabled"; <<
815 <<
816 pcs1: ethernet-phy@0 { <<
817 reg = <0>; <<
818 }; <<
819 }; <<
820 <<
821 pcs_mdio2: mdio@8c0b000 { <<
822 compatible = "fsl,fman <<
823 reg = <0x0 0x8c0b000 0 <<
824 little-endian; <<
825 #address-cells = <1>; <<
826 #size-cells = <0>; <<
827 status = "disabled"; <<
828 <<
829 pcs2: ethernet-phy@0 { <<
830 reg = <0>; <<
831 }; <<
832 }; <<
833 <<
834 pcs_mdio3: mdio@8c0f000 { <<
835 compatible = "fsl,fman <<
836 reg = <0x0 0x8c0f000 0 <<
837 little-endian; <<
838 #address-cells = <1>; <<
839 #size-cells = <0>; <<
840 status = "disabled"; <<
841 <<
842 pcs3_0: ethernet-phy@0 <<
843 reg = <0>; <<
844 }; <<
845 <<
846 pcs3_1: ethernet-phy@1 <<
847 reg = <1>; <<
848 }; <<
849 <<
850 pcs3_2: ethernet-phy@2 <<
851 reg = <2>; <<
852 }; <<
853 <<
854 pcs3_3: ethernet-phy@3 <<
855 reg = <3>; <<
856 }; <<
857 }; <<
858 <<
859 pcs_mdio7: mdio@8c1f000 { <<
860 compatible = "fsl,fman <<
861 reg = <0x0 0x8c1f000 0 <<
862 little-endian; <<
863 #address-cells = <1>; <<
864 #size-cells = <0>; <<
865 status = "disabled"; <<
866 <<
867 pcs7_0: ethernet-phy@0 <<
868 reg = <0>; <<
869 }; <<
870 <<
871 pcs7_1: ethernet-phy@1 <<
872 reg = <1>; <<
873 }; <<
874 <<
875 pcs7_2: ethernet-phy@2 <<
876 reg = <2>; <<
877 }; <<
878 <<
879 pcs7_3: ethernet-phy@3 <<
880 reg = <3>; <<
881 }; <<
882 }; <<
883 <<
884 cluster1_core0_watchdog: watch <<
885 compatible = "arm,sp80 640 compatible = "arm,sp805", "arm,primecell";
886 reg = <0x0 0xc000000 0 641 reg = <0x0 0xc000000 0x0 0x1000>;
887 clocks = <&clockgen QO !! 642 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
888 QO <<
889 <&clockgen QO <<
890 QO <<
891 clock-names = "wdog_cl 643 clock-names = "wdog_clk", "apb_pclk";
892 }; 644 };
893 645
894 cluster1_core1_watchdog: watch !! 646 cluster1_core1_watchdog: wdt@c010000 {
895 compatible = "arm,sp80 647 compatible = "arm,sp805", "arm,primecell";
896 reg = <0x0 0xc010000 0 648 reg = <0x0 0xc010000 0x0 0x1000>;
897 clocks = <&clockgen QO !! 649 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
898 QO <<
899 <&clockgen QO <<
900 QO <<
901 clock-names = "wdog_cl 650 clock-names = "wdog_clk", "apb_pclk";
902 }; 651 };
903 652
904 cluster1_core2_watchdog: watch !! 653 cluster1_core2_watchdog: wdt@c020000 {
905 compatible = "arm,sp80 654 compatible = "arm,sp805", "arm,primecell";
906 reg = <0x0 0xc020000 0 655 reg = <0x0 0xc020000 0x0 0x1000>;
907 clocks = <&clockgen QO !! 656 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
908 QO <<
909 <&clockgen QO <<
910 QO <<
911 clock-names = "wdog_cl 657 clock-names = "wdog_clk", "apb_pclk";
912 }; 658 };
913 659
914 cluster1_core3_watchdog: watch !! 660 cluster1_core3_watchdog: wdt@c030000 {
915 compatible = "arm,sp80 661 compatible = "arm,sp805", "arm,primecell";
916 reg = <0x0 0xc030000 0 662 reg = <0x0 0xc030000 0x0 0x1000>;
917 clocks = <&clockgen QO !! 663 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
918 QO <<
919 <&clockgen QO <<
920 QO <<
921 clock-names = "wdog_cl 664 clock-names = "wdog_clk", "apb_pclk";
922 }; 665 };
923 666
924 cluster2_core0_watchdog: watch !! 667 cluster2_core0_watchdog: wdt@c100000 {
925 compatible = "arm,sp80 668 compatible = "arm,sp805", "arm,primecell";
926 reg = <0x0 0xc100000 0 669 reg = <0x0 0xc100000 0x0 0x1000>;
927 clocks = <&clockgen QO !! 670 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
928 QO <<
929 <&clockgen QO <<
930 QO <<
931 clock-names = "wdog_cl 671 clock-names = "wdog_clk", "apb_pclk";
932 }; 672 };
933 673
934 cluster2_core1_watchdog: watch !! 674 cluster2_core1_watchdog: wdt@c110000 {
935 compatible = "arm,sp80 675 compatible = "arm,sp805", "arm,primecell";
936 reg = <0x0 0xc110000 0 676 reg = <0x0 0xc110000 0x0 0x1000>;
937 clocks = <&clockgen QO !! 677 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
938 QO <<
939 <&clockgen QO <<
940 QO <<
941 clock-names = "wdog_cl 678 clock-names = "wdog_clk", "apb_pclk";
942 }; 679 };
943 680
944 cluster2_core2_watchdog: watch !! 681 cluster2_core2_watchdog: wdt@c120000 {
945 compatible = "arm,sp80 682 compatible = "arm,sp805", "arm,primecell";
946 reg = <0x0 0xc120000 0 683 reg = <0x0 0xc120000 0x0 0x1000>;
947 clocks = <&clockgen QO !! 684 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
948 QO <<
949 <&clockgen QO <<
950 QO <<
951 clock-names = "wdog_cl 685 clock-names = "wdog_clk", "apb_pclk";
952 }; 686 };
953 687
954 cluster2_core3_watchdog: watch !! 688 cluster2_core3_watchdog: wdt@c130000 {
955 compatible = "arm,sp80 689 compatible = "arm,sp805", "arm,primecell";
956 reg = <0x0 0xc130000 0 690 reg = <0x0 0xc130000 0x0 0x1000>;
957 clocks = <&clockgen QO !! 691 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
958 QO <<
959 <&clockgen QO <<
960 QO <<
961 clock-names = "wdog_cl 692 clock-names = "wdog_clk", "apb_pclk";
962 }; 693 };
963 694
964 fsl_mc: fsl-mc@80c000000 { 695 fsl_mc: fsl-mc@80c000000 {
965 compatible = "fsl,qori 696 compatible = "fsl,qoriq-mc";
966 reg = <0x00000008 0x0c 697 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
967 <0x00000000 0x08 698 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
968 msi-parent = <&its 0>; !! 699 msi-parent = <&its>;
969 iommu-map = <0 &smmu 0 700 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
970 dma-coherent; 701 dma-coherent;
971 #address-cells = <3>; 702 #address-cells = <3>;
972 #size-cells = <1>; 703 #size-cells = <1>;
973 704
974 /* 705 /*
975 * Region type 0x0 - M 706 * Region type 0x0 - MC portals
976 * Region type 0x1 - Q 707 * Region type 0x1 - QBMAN portals
977 */ 708 */
978 ranges = <0x0 0x0 0x0 709 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
979 0x1 0x0 0x0 710 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
980 711
981 dpmacs { 712 dpmacs {
982 #address-cells 713 #address-cells = <1>;
983 #size-cells = 714 #size-cells = <0>;
984 715
985 dpmac1: ethern !! 716 dpmac1: dpmac@1 {
986 compat 717 compatible = "fsl,qoriq-mc-dpmac";
987 reg = 718 reg = <1>;
988 }; 719 };
989 720
990 dpmac2: ethern !! 721 dpmac2: dpmac@2 {
991 compat 722 compatible = "fsl,qoriq-mc-dpmac";
992 reg = 723 reg = <2>;
993 }; 724 };
994 725
995 dpmac3: ethern !! 726 dpmac3: dpmac@3 {
996 compat 727 compatible = "fsl,qoriq-mc-dpmac";
997 reg = 728 reg = <3>;
998 }; 729 };
999 730
1000 dpmac4: ether !! 731 dpmac4: dpmac@4 {
1001 compa 732 compatible = "fsl,qoriq-mc-dpmac";
1002 reg = 733 reg = <4>;
1003 }; 734 };
1004 735
1005 dpmac5: ether !! 736 dpmac5: dpmac@5 {
1006 compa 737 compatible = "fsl,qoriq-mc-dpmac";
1007 reg = 738 reg = <5>;
1008 }; 739 };
1009 740
1010 dpmac6: ether !! 741 dpmac6: dpmac@6 {
1011 compa 742 compatible = "fsl,qoriq-mc-dpmac";
1012 reg = 743 reg = <6>;
1013 }; 744 };
1014 745
1015 dpmac7: ether !! 746 dpmac7: dpmac@7 {
1016 compa 747 compatible = "fsl,qoriq-mc-dpmac";
1017 reg = 748 reg = <7>;
1018 }; 749 };
1019 750
1020 dpmac8: ether !! 751 dpmac8: dpmac@8 {
1021 compa 752 compatible = "fsl,qoriq-mc-dpmac";
1022 reg = 753 reg = <8>;
1023 }; 754 };
1024 755
1025 dpmac9: ether !! 756 dpmac9: dpmac@9 {
1026 compa 757 compatible = "fsl,qoriq-mc-dpmac";
1027 reg = 758 reg = <9>;
1028 }; 759 };
1029 760
1030 dpmac10: ethe !! 761 dpmac10: dpmac@a {
1031 compa 762 compatible = "fsl,qoriq-mc-dpmac";
1032 reg = 763 reg = <0xa>;
1033 }; 764 };
1034 }; 765 };
1035 }; <<
1036 <<
1037 rcpm: wakeup-controller@1e340 <<
1038 compatible = "fsl,ls1 <<
1039 reg = <0x0 0x1e34040 <<
1040 #fsl,rcpm-wakeup-cell <<
1041 little-endian; <<
1042 }; <<
1043 <<
1044 ftm_alarm0: rtc@2800000 { <<
1045 compatible = "fsl,ls1 <<
1046 reg = <0x0 0x2800000 <<
1047 fsl,rcpm-wakeup = <&r <<
1048 interrupts = <GIC_SPI <<
1049 }; 766 };
1050 }; 767 };
1051 768
1052 firmware { 769 firmware {
1053 optee { 770 optee {
1054 compatible = "linaro, 771 compatible = "linaro,optee-tz";
1055 method = "smc"; 772 method = "smc";
1056 }; 773 };
1057 }; 774 };
1058 }; 775 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.