1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for NXP Layerscape 3 * Device Tree Include file for NXP Layerscape-1088A family SoC.
4 * 4 *
5 * Copyright 2017-2020 NXP 5 * Copyright 2017-2020 NXP
6 * 6 *
7 * Harninder Rai <harninder.rai@nxp.com> 7 * Harninder Rai <harninder.rai@nxp.com>
8 * 8 *
9 */ 9 */
10 #include <dt-bindings/clock/fsl,qoriq-clockgen 10 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
11 #include <dt-bindings/interrupt-controller/arm 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 / { 14 / {
15 compatible = "fsl,ls1088a"; 15 compatible = "fsl,ls1088a";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 crypto = &crypto; 21 crypto = &crypto;
22 rtc1 = &ftm_alarm0; 22 rtc1 = &ftm_alarm0;
23 }; 23 };
24 24
25 cpus { 25 cpus {
26 #address-cells = <1>; 26 #address-cells = <1>;
27 #size-cells = <0>; 27 #size-cells = <0>;
28 28
29 /* We have 2 clusters having 4 29 /* We have 2 clusters having 4 Cortex-A53 cores each */
30 cpu0: cpu@0 { 30 cpu0: cpu@0 {
31 device_type = "cpu"; 31 device_type = "cpu";
32 compatible = "arm,cort 32 compatible = "arm,cortex-a53";
33 reg = <0x0>; 33 reg = <0x0>;
34 clocks = <&clockgen QO 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 cpu-idle-states = <&CP 35 cpu-idle-states = <&CPU_PH20>;
36 #cooling-cells = <2>; 36 #cooling-cells = <2>;
37 }; 37 };
38 38
39 cpu1: cpu@1 { 39 cpu1: cpu@1 {
40 device_type = "cpu"; 40 device_type = "cpu";
41 compatible = "arm,cort 41 compatible = "arm,cortex-a53";
42 reg = <0x1>; 42 reg = <0x1>;
43 clocks = <&clockgen QO 43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
44 cpu-idle-states = <&CP 44 cpu-idle-states = <&CPU_PH20>;
45 #cooling-cells = <2>; 45 #cooling-cells = <2>;
46 }; 46 };
47 47
48 cpu2: cpu@2 { 48 cpu2: cpu@2 {
49 device_type = "cpu"; 49 device_type = "cpu";
50 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
51 reg = <0x2>; 51 reg = <0x2>;
52 clocks = <&clockgen QO 52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 cpu-idle-states = <&CP 53 cpu-idle-states = <&CPU_PH20>;
54 #cooling-cells = <2>; 54 #cooling-cells = <2>;
55 }; 55 };
56 56
57 cpu3: cpu@3 { 57 cpu3: cpu@3 {
58 device_type = "cpu"; 58 device_type = "cpu";
59 compatible = "arm,cort 59 compatible = "arm,cortex-a53";
60 reg = <0x3>; 60 reg = <0x3>;
61 clocks = <&clockgen QO 61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
62 cpu-idle-states = <&CP 62 cpu-idle-states = <&CPU_PH20>;
63 #cooling-cells = <2>; 63 #cooling-cells = <2>;
64 }; 64 };
65 65
66 cpu4: cpu@100 { 66 cpu4: cpu@100 {
67 device_type = "cpu"; 67 device_type = "cpu";
68 compatible = "arm,cort 68 compatible = "arm,cortex-a53";
69 reg = <0x100>; 69 reg = <0x100>;
70 clocks = <&clockgen QO 70 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
71 cpu-idle-states = <&CP 71 cpu-idle-states = <&CPU_PH20>;
72 #cooling-cells = <2>; 72 #cooling-cells = <2>;
73 }; 73 };
74 74
75 cpu5: cpu@101 { 75 cpu5: cpu@101 {
76 device_type = "cpu"; 76 device_type = "cpu";
77 compatible = "arm,cort 77 compatible = "arm,cortex-a53";
78 reg = <0x101>; 78 reg = <0x101>;
79 clocks = <&clockgen QO 79 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
80 cpu-idle-states = <&CP 80 cpu-idle-states = <&CPU_PH20>;
81 #cooling-cells = <2>; 81 #cooling-cells = <2>;
82 }; 82 };
83 83
84 cpu6: cpu@102 { 84 cpu6: cpu@102 {
85 device_type = "cpu"; 85 device_type = "cpu";
86 compatible = "arm,cort 86 compatible = "arm,cortex-a53";
87 reg = <0x102>; 87 reg = <0x102>;
88 clocks = <&clockgen QO 88 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
89 cpu-idle-states = <&CP 89 cpu-idle-states = <&CPU_PH20>;
90 #cooling-cells = <2>; 90 #cooling-cells = <2>;
91 }; 91 };
92 92
93 cpu7: cpu@103 { 93 cpu7: cpu@103 {
94 device_type = "cpu"; 94 device_type = "cpu";
95 compatible = "arm,cort 95 compatible = "arm,cortex-a53";
96 reg = <0x103>; 96 reg = <0x103>;
97 clocks = <&clockgen QO 97 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
98 cpu-idle-states = <&CP 98 cpu-idle-states = <&CPU_PH20>;
99 #cooling-cells = <2>; 99 #cooling-cells = <2>;
100 }; 100 };
101 101
102 CPU_PH20: cpu-ph20 { 102 CPU_PH20: cpu-ph20 {
103 compatible = "arm,idle 103 compatible = "arm,idle-state";
104 idle-state-name = "PH2 104 idle-state-name = "PH20";
105 arm,psci-suspend-param 105 arm,psci-suspend-param = <0x0>;
106 entry-latency-us = <10 106 entry-latency-us = <1000>;
107 exit-latency-us = <100 107 exit-latency-us = <1000>;
108 min-residency-us = <30 108 min-residency-us = <3000>;
109 }; 109 };
110 }; 110 };
111 111
112 gic: interrupt-controller@6000000 { 112 gic: interrupt-controller@6000000 {
113 compatible = "arm,gic-v3"; 113 compatible = "arm,gic-v3";
114 #interrupt-cells = <3>; 114 #interrupt-cells = <3>;
115 interrupt-controller; 115 interrupt-controller;
116 reg = <0x0 0x06000000 0 0x1000 116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x1000 117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000 118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000 119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x2000 120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
121 interrupts = <GIC_PPI 9 IRQ_TY !! 121 interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>;
122 #address-cells = <2>; 122 #address-cells = <2>;
123 #size-cells = <2>; 123 #size-cells = <2>;
124 ranges; 124 ranges;
125 125
126 its: msi-controller@6020000 { 126 its: msi-controller@6020000 {
127 compatible = "arm,gic- 127 compatible = "arm,gic-v3-its";
128 msi-controller; 128 msi-controller;
129 #msi-cells = <1>; <<
130 reg = <0x0 0x6020000 0 129 reg = <0x0 0x6020000 0 0x20000>;
131 }; 130 };
132 }; 131 };
133 132
134 thermal-zones { 133 thermal-zones {
135 cluster-thermal { !! 134 core-cluster {
136 polling-delay-passive 135 polling-delay-passive = <1000>;
137 polling-delay = <5000> 136 polling-delay = <5000>;
138 thermal-sensors = <&tm 137 thermal-sensors = <&tmu 0>;
139 138
140 trips { 139 trips {
141 core_cluster_a 140 core_cluster_alert: core-cluster-alert {
142 temper 141 temperature = <85000>;
143 hyster 142 hysteresis = <2000>;
144 type = 143 type = "passive";
145 }; 144 };
146 145
147 core-cluster-c 146 core-cluster-crit {
148 temper 147 temperature = <95000>;
149 hyster 148 hysteresis = <2000>;
150 type = 149 type = "critical";
151 }; 150 };
152 }; 151 };
153 152
154 cooling-maps { 153 cooling-maps {
155 map0 { 154 map0 {
156 trip = 155 trip = <&core_cluster_alert>;
157 coolin 156 cooling-device =
158 157 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
159 158 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
160 159 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
161 160 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 161 <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
163 162 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
164 163 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
165 164 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
166 }; 165 };
167 }; 166 };
168 }; 167 };
169 168
170 soc-thermal { !! 169 soc {
171 polling-delay-passive 170 polling-delay-passive = <1000>;
172 polling-delay = <5000> 171 polling-delay = <5000>;
173 thermal-sensors = <&tm 172 thermal-sensors = <&tmu 1>;
174 173
175 trips { 174 trips {
176 soc-crit { 175 soc-crit {
177 temper 176 temperature = <95000>;
178 hyster 177 hysteresis = <2000>;
179 type = 178 type = "critical";
180 }; 179 };
181 }; 180 };
182 }; 181 };
183 }; 182 };
184 183
185 timer { 184 timer {
186 compatible = "arm,armv8-timer" 185 compatible = "arm,armv8-timer";
187 interrupts = <GIC_PPI 13 IRQ_T !! 186 interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */
188 <GIC_PPI 14 IRQ_T !! 187 <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */
189 <GIC_PPI 11 IRQ_T !! 188 <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */
190 <GIC_PPI 10 IRQ_T !! 189 <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */
191 }; 190 };
192 191
193 pmu { 192 pmu {
194 compatible = "arm,cortex-a53-p 193 compatible = "arm,cortex-a53-pmu";
195 interrupts = <GIC_PPI 7 IRQ_TY 194 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
196 }; 195 };
197 196
198 psci { 197 psci {
199 compatible = "arm,psci-0.2"; 198 compatible = "arm,psci-0.2";
200 method = "smc"; 199 method = "smc";
201 }; 200 };
202 201
203 sysclk: sysclk { 202 sysclk: sysclk {
204 compatible = "fixed-clock"; 203 compatible = "fixed-clock";
205 #clock-cells = <0>; 204 #clock-cells = <0>;
206 clock-frequency = <100000000>; 205 clock-frequency = <100000000>;
207 clock-output-names = "sysclk"; 206 clock-output-names = "sysclk";
208 }; 207 };
209 208
210 reboot { 209 reboot {
211 compatible = "syscon-reboot"; 210 compatible = "syscon-reboot";
212 regmap = <&reset>; 211 regmap = <&reset>;
213 offset = <0x0>; 212 offset = <0x0>;
214 mask = <0x02>; 213 mask = <0x02>;
215 }; 214 };
216 215
217 soc { 216 soc {
218 compatible = "simple-bus"; 217 compatible = "simple-bus";
219 #address-cells = <2>; 218 #address-cells = <2>;
220 #size-cells = <2>; 219 #size-cells = <2>;
221 ranges; 220 ranges;
222 dma-ranges = <0x0 0x0 0x0 0x0 221 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
223 222
224 clockgen: clocking@1300000 { 223 clockgen: clocking@1300000 {
225 compatible = "fsl,ls10 224 compatible = "fsl,ls1088a-clockgen";
226 reg = <0 0x1300000 0 0 225 reg = <0 0x1300000 0 0xa0000>;
227 #clock-cells = <2>; 226 #clock-cells = <2>;
228 clocks = <&sysclk>; 227 clocks = <&sysclk>;
229 }; 228 };
230 229
231 dcfg: dcfg@1e00000 { 230 dcfg: dcfg@1e00000 {
232 compatible = "fsl,ls10 231 compatible = "fsl,ls1088a-dcfg", "syscon";
233 reg = <0x0 0x1e00000 0 232 reg = <0x0 0x1e00000 0x0 0x10000>;
234 little-endian; 233 little-endian;
235 }; 234 };
236 235
237 reset: syscon@1e60000 { 236 reset: syscon@1e60000 {
238 compatible = "fsl,ls10 237 compatible = "fsl,ls1088a-reset", "syscon";
239 reg = <0x0 0x1e60000 0 238 reg = <0x0 0x1e60000 0x0 0x10000>;
240 }; 239 };
241 240
242 isc: syscon@1f70000 { 241 isc: syscon@1f70000 {
243 compatible = "fsl,ls10 242 compatible = "fsl,ls1088a-isc", "syscon";
244 reg = <0x0 0x1f70000 0 243 reg = <0x0 0x1f70000 0x0 0x10000>;
245 little-endian; 244 little-endian;
246 #address-cells = <1>; 245 #address-cells = <1>;
247 #size-cells = <1>; 246 #size-cells = <1>;
248 ranges = <0x0 0x0 0x1f 247 ranges = <0x0 0x0 0x1f70000 0x10000>;
249 248
250 extirq: interrupt-cont 249 extirq: interrupt-controller@14 {
251 compatible = " 250 compatible = "fsl,ls1088a-extirq";
252 #interrupt-cel 251 #interrupt-cells = <2>;
253 #address-cells 252 #address-cells = <0>;
254 interrupt-cont 253 interrupt-controller;
255 reg = <0x14 4> 254 reg = <0x14 4>;
256 interrupt-map 255 interrupt-map =
257 <0 0 & 256 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <1 0 & 257 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <2 0 & 258 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <3 0 & 259 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <4 0 & 260 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
262 <5 0 & 261 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
263 <6 0 & 262 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
264 <7 0 & 263 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
265 <8 0 & 264 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
266 <9 0 & 265 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
267 <10 0 266 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
268 <11 0 267 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-map- 268 interrupt-map-mask = <0xf 0x0>;
270 }; 269 };
271 }; 270 };
272 271
273 sfp: efuse@1e80000 { 272 sfp: efuse@1e80000 {
274 compatible = "fsl,ls10 273 compatible = "fsl,ls1028a-sfp";
275 reg = <0x0 0x1e80000 0 274 reg = <0x0 0x1e80000 0x0 0x10000>;
276 clocks = <&clockgen QO 275 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
277 QO 276 QORIQ_CLK_PLL_DIV(4)>;
278 clock-names = "sfp"; 277 clock-names = "sfp";
279 }; 278 };
280 279
281 tmu: tmu@1f80000 { 280 tmu: tmu@1f80000 {
282 compatible = "fsl,qori 281 compatible = "fsl,qoriq-tmu";
283 reg = <0x0 0x1f80000 0 282 reg = <0x0 0x1f80000 0x0 0x10000>;
284 interrupts = <GIC_SPI !! 283 interrupts = <0 23 0x4>;
285 fsl,tmu-range = <0xb00 284 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
286 fsl,tmu-calibration = 285 fsl,tmu-calibration =
287 /* Calibration 286 /* Calibration data group 1 */
288 <0x00000000 0x !! 287 <0x00000000 0x00000023
289 <0x00000001 0x !! 288 0x00000001 0x0000002a
290 <0x00000002 0x !! 289 0x00000002 0x00000030
291 <0x00000003 0x !! 290 0x00000003 0x00000037
292 <0x00000004 0x !! 291 0x00000004 0x0000003d
293 <0x00000005 0x !! 292 0x00000005 0x00000044
294 <0x00000006 0x !! 293 0x00000006 0x0000004a
295 <0x00000007 0x !! 294 0x00000007 0x00000051
296 <0x00000008 0x !! 295 0x00000008 0x00000057
297 <0x00000009 0x !! 296 0x00000009 0x0000005e
298 <0x0000000a 0x !! 297 0x0000000a 0x00000064
299 <0x0000000b 0x !! 298 0x0000000b 0x0000006b
300 /* Calibration 299 /* Calibration data group 2 */
301 <0x00010000 0x !! 300 0x00010000 0x00000022
302 <0x00010001 0x !! 301 0x00010001 0x0000002a
303 <0x00010002 0x !! 302 0x00010002 0x00000032
304 <0x00010003 0x !! 303 0x00010003 0x0000003a
305 <0x00010004 0x !! 304 0x00010004 0x00000042
306 <0x00010005 0x !! 305 0x00010005 0x0000004a
307 <0x00010006 0x !! 306 0x00010006 0x00000052
308 <0x00010007 0x !! 307 0x00010007 0x0000005a
309 <0x00010008 0x !! 308 0x00010008 0x00000062
310 <0x00010009 0x !! 309 0x00010009 0x0000006a
311 /* Calibration 310 /* Calibration data group 3 */
312 <0x00020000 0x !! 311 0x00020000 0x00000021
313 <0x00020001 0x !! 312 0x00020001 0x0000002b
314 <0x00020002 0x !! 313 0x00020002 0x00000035
315 <0x00020003 0x !! 314 0x00020003 0x00000040
316 <0x00020004 0x !! 315 0x00020004 0x0000004a
317 <0x00020005 0x !! 316 0x00020005 0x00000054
318 <0x00020006 0x !! 317 0x00020006 0x0000005e
319 /* Calibration 318 /* Calibration data group 4 */
320 <0x00030000 0x !! 319 0x00030000 0x00000010
321 <0x00030001 0x !! 320 0x00030001 0x0000001c
322 <0x00030002 0x !! 321 0x00030002 0x00000027
323 <0x00030003 0x !! 322 0x00030003 0x00000032
324 <0x00030004 0x !! 323 0x00030004 0x0000003e
325 <0x00030005 0x !! 324 0x00030005 0x00000049
326 <0x00030006 0x !! 325 0x00030006 0x00000054
327 <0x00030007 0x !! 326 0x00030007 0x00000060>;
328 little-endian; 327 little-endian;
329 #thermal-sensor-cells 328 #thermal-sensor-cells = <1>;
330 }; 329 };
331 330
332 dspi: spi@2100000 { 331 dspi: spi@2100000 {
333 compatible = "fsl,ls10 332 compatible = "fsl,ls1088a-dspi",
334 "fsl,ls10 333 "fsl,ls1021a-v1.0-dspi";
335 #address-cells = <1>; 334 #address-cells = <1>;
336 #size-cells = <0>; 335 #size-cells = <0>;
337 reg = <0x0 0x2100000 0 336 reg = <0x0 0x2100000 0x0 0x10000>;
338 interrupts = <GIC_SPI 337 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
339 clock-names = "dspi"; 338 clock-names = "dspi";
340 clocks = <&clockgen QO 339 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
341 QO 340 QORIQ_CLK_PLL_DIV(2)>;
342 spi-num-chipselects = 341 spi-num-chipselects = <6>;
343 status = "disabled"; 342 status = "disabled";
344 }; 343 };
345 344
346 duart0: serial@21c0500 { 345 duart0: serial@21c0500 {
347 compatible = "fsl,ns16 346 compatible = "fsl,ns16550", "ns16550a";
348 reg = <0x0 0x21c0500 0 347 reg = <0x0 0x21c0500 0x0 0x100>;
349 clocks = <&clockgen QO 348 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
350 QO 349 QORIQ_CLK_PLL_DIV(4)>;
351 interrupts = <GIC_SPI !! 350 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
352 status = "disabled"; 351 status = "disabled";
353 }; 352 };
354 353
355 duart1: serial@21c0600 { 354 duart1: serial@21c0600 {
356 compatible = "fsl,ns16 355 compatible = "fsl,ns16550", "ns16550a";
357 reg = <0x0 0x21c0600 0 356 reg = <0x0 0x21c0600 0x0 0x100>;
358 clocks = <&clockgen QO 357 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
359 QO 358 QORIQ_CLK_PLL_DIV(4)>;
360 interrupts = <GIC_SPI !! 359 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
361 status = "disabled"; 360 status = "disabled";
362 }; 361 };
363 362
364 gpio0: gpio@2300000 { 363 gpio0: gpio@2300000 {
365 compatible = "fsl,ls10 364 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
366 reg = <0x0 0x2300000 0 365 reg = <0x0 0x2300000 0x0 0x10000>;
367 interrupts = <GIC_SPI !! 366 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
368 little-endian; 367 little-endian;
369 gpio-controller; 368 gpio-controller;
370 #gpio-cells = <2>; 369 #gpio-cells = <2>;
371 interrupt-controller; 370 interrupt-controller;
372 #interrupt-cells = <2> 371 #interrupt-cells = <2>;
373 }; 372 };
374 373
375 gpio1: gpio@2310000 { 374 gpio1: gpio@2310000 {
376 compatible = "fsl,ls10 375 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
377 reg = <0x0 0x2310000 0 376 reg = <0x0 0x2310000 0x0 0x10000>;
378 interrupts = <GIC_SPI !! 377 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
379 little-endian; 378 little-endian;
380 gpio-controller; 379 gpio-controller;
381 #gpio-cells = <2>; 380 #gpio-cells = <2>;
382 interrupt-controller; 381 interrupt-controller;
383 #interrupt-cells = <2> 382 #interrupt-cells = <2>;
384 }; 383 };
385 384
386 gpio2: gpio@2320000 { 385 gpio2: gpio@2320000 {
387 compatible = "fsl,ls10 386 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
388 reg = <0x0 0x2320000 0 387 reg = <0x0 0x2320000 0x0 0x10000>;
389 interrupts = <GIC_SPI !! 388 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
390 little-endian; 389 little-endian;
391 gpio-controller; 390 gpio-controller;
392 #gpio-cells = <2>; 391 #gpio-cells = <2>;
393 interrupt-controller; 392 interrupt-controller;
394 #interrupt-cells = <2> 393 #interrupt-cells = <2>;
395 }; 394 };
396 395
397 gpio3: gpio@2330000 { 396 gpio3: gpio@2330000 {
398 compatible = "fsl,ls10 397 compatible = "fsl,ls1088a-gpio", "fsl,qoriq-gpio";
399 reg = <0x0 0x2330000 0 398 reg = <0x0 0x2330000 0x0 0x10000>;
400 interrupts = <GIC_SPI !! 399 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
401 little-endian; 400 little-endian;
402 gpio-controller; 401 gpio-controller;
403 #gpio-cells = <2>; 402 #gpio-cells = <2>;
404 interrupt-controller; 403 interrupt-controller;
405 #interrupt-cells = <2> 404 #interrupt-cells = <2>;
406 }; 405 };
407 406
408 ifc: memory-controller@2240000 407 ifc: memory-controller@2240000 {
409 compatible = "fsl,ifc" 408 compatible = "fsl,ifc";
410 reg = <0x0 0x2240000 0 409 reg = <0x0 0x2240000 0x0 0x20000>;
411 interrupts = <GIC_SPI !! 410 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
412 little-endian; 411 little-endian;
413 #address-cells = <2>; 412 #address-cells = <2>;
414 #size-cells = <1>; 413 #size-cells = <1>;
415 status = "disabled"; 414 status = "disabled";
416 }; 415 };
417 416
418 i2c0: i2c@2000000 { 417 i2c0: i2c@2000000 {
419 compatible = "fsl,vf61 418 compatible = "fsl,vf610-i2c";
420 #address-cells = <1>; 419 #address-cells = <1>;
421 #size-cells = <0>; 420 #size-cells = <0>;
422 reg = <0x0 0x2000000 0 421 reg = <0x0 0x2000000 0x0 0x10000>;
423 interrupts = <GIC_SPI !! 422 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
424 clocks = <&clockgen QO 423 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
425 QO 424 QORIQ_CLK_PLL_DIV(8)>;
426 status = "disabled"; 425 status = "disabled";
427 }; 426 };
428 427
429 i2c1: i2c@2010000 { 428 i2c1: i2c@2010000 {
430 compatible = "fsl,vf61 429 compatible = "fsl,vf610-i2c";
431 #address-cells = <1>; 430 #address-cells = <1>;
432 #size-cells = <0>; 431 #size-cells = <0>;
433 reg = <0x0 0x2010000 0 432 reg = <0x0 0x2010000 0x0 0x10000>;
434 interrupts = <GIC_SPI !! 433 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
435 clocks = <&clockgen QO 434 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
436 QO 435 QORIQ_CLK_PLL_DIV(8)>;
437 status = "disabled"; 436 status = "disabled";
438 }; 437 };
439 438
440 i2c2: i2c@2020000 { 439 i2c2: i2c@2020000 {
441 compatible = "fsl,vf61 440 compatible = "fsl,vf610-i2c";
442 #address-cells = <1>; 441 #address-cells = <1>;
443 #size-cells = <0>; 442 #size-cells = <0>;
444 reg = <0x0 0x2020000 0 443 reg = <0x0 0x2020000 0x0 0x10000>;
445 interrupts = <GIC_SPI !! 444 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
446 clocks = <&clockgen QO 445 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
447 QO 446 QORIQ_CLK_PLL_DIV(8)>;
448 status = "disabled"; 447 status = "disabled";
449 }; 448 };
450 449
451 i2c3: i2c@2030000 { 450 i2c3: i2c@2030000 {
452 compatible = "fsl,vf61 451 compatible = "fsl,vf610-i2c";
453 #address-cells = <1>; 452 #address-cells = <1>;
454 #size-cells = <0>; 453 #size-cells = <0>;
455 reg = <0x0 0x2030000 0 454 reg = <0x0 0x2030000 0x0 0x10000>;
456 interrupts = <GIC_SPI !! 455 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
457 clocks = <&clockgen QO 456 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
458 QO 457 QORIQ_CLK_PLL_DIV(8)>;
459 status = "disabled"; 458 status = "disabled";
460 }; 459 };
461 460
462 qspi: spi@20c0000 { 461 qspi: spi@20c0000 {
463 compatible = "fsl,ls20 462 compatible = "fsl,ls2080a-qspi";
464 #address-cells = <1>; 463 #address-cells = <1>;
465 #size-cells = <0>; 464 #size-cells = <0>;
466 reg = <0x0 0x20c0000 0 465 reg = <0x0 0x20c0000 0x0 0x10000>,
467 <0x0 0x20000000 466 <0x0 0x20000000 0x0 0x10000000>;
468 reg-names = "QuadSPI", 467 reg-names = "QuadSPI", "QuadSPI-memory";
469 interrupts = <GIC_SPI 468 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
470 clock-names = "qspi_en 469 clock-names = "qspi_en", "qspi";
471 clocks = <&clockgen QO 470 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
472 QO 471 QORIQ_CLK_PLL_DIV(4)>,
473 <&clockgen QO 472 <&clockgen QORIQ_CLK_PLATFORM_PLL
474 QO 473 QORIQ_CLK_PLL_DIV(4)>;
475 status = "disabled"; 474 status = "disabled";
476 }; 475 };
477 476
478 esdhc: mmc@2140000 { !! 477 esdhc: esdhc@2140000 {
479 compatible = "fsl,ls10 478 compatible = "fsl,ls1088a-esdhc", "fsl,esdhc";
480 reg = <0x0 0x2140000 0 479 reg = <0x0 0x2140000 0x0 0x10000>;
481 interrupts = <GIC_SPI !! 480 interrupts = <0 28 0x4>; /* Level high type */
482 clock-frequency = <0>; 481 clock-frequency = <0>;
483 clocks = <&clockgen QO 482 clocks = <&clockgen QORIQ_CLK_HWACCEL 1>;
484 voltage-ranges = <1800 483 voltage-ranges = <1800 1800 3300 3300>;
485 sdhci,auto-cmd12; 484 sdhci,auto-cmd12;
486 little-endian; 485 little-endian;
487 bus-width = <4>; 486 bus-width = <4>;
488 status = "disabled"; 487 status = "disabled";
489 }; 488 };
490 489
491 usb0: usb@3100000 { 490 usb0: usb@3100000 {
492 compatible = "snps,dwc 491 compatible = "snps,dwc3";
493 reg = <0x0 0x3100000 0 492 reg = <0x0 0x3100000 0x0 0x10000>;
494 interrupts = <GIC_SPI !! 493 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
495 dr_mode = "host"; 494 dr_mode = "host";
496 snps,quirk-frame-lengt 495 snps,quirk-frame-length-adjustment = <0x20>;
497 snps,dis_rxdet_inp3_qu 496 snps,dis_rxdet_inp3_quirk;
498 snps,incr-burst-type-a 497 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
499 status = "disabled"; 498 status = "disabled";
500 }; 499 };
501 500
502 usb1: usb@3110000 { 501 usb1: usb@3110000 {
503 compatible = "snps,dwc 502 compatible = "snps,dwc3";
504 reg = <0x0 0x3110000 0 503 reg = <0x0 0x3110000 0x0 0x10000>;
505 interrupts = <GIC_SPI !! 504 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
506 dr_mode = "host"; 505 dr_mode = "host";
507 snps,quirk-frame-lengt 506 snps,quirk-frame-length-adjustment = <0x20>;
508 snps,dis_rxdet_inp3_qu 507 snps,dis_rxdet_inp3_quirk;
509 snps,incr-burst-type-a 508 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
510 status = "disabled"; 509 status = "disabled";
511 }; 510 };
512 511
513 sata: sata@3200000 { 512 sata: sata@3200000 {
514 compatible = "fsl,ls10 513 compatible = "fsl,ls1088a-ahci";
515 reg = <0x0 0x3200000 0 514 reg = <0x0 0x3200000 0x0 0x10000>,
516 <0x7 0x100520 515 <0x7 0x100520 0x0 0x4>;
517 reg-names = "ahci", "s 516 reg-names = "ahci", "sata-ecc";
518 interrupts = <GIC_SPI !! 517 interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>;
519 clocks = <&clockgen QO 518 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
520 QO 519 QORIQ_CLK_PLL_DIV(4)>;
521 dma-coherent; 520 dma-coherent;
522 status = "disabled"; 521 status = "disabled";
523 }; 522 };
524 523
525 crypto: crypto@8000000 { 524 crypto: crypto@8000000 {
526 compatible = "fsl,sec- 525 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
527 fsl,sec-era = <8>; 526 fsl,sec-era = <8>;
528 #address-cells = <1>; 527 #address-cells = <1>;
529 #size-cells = <1>; 528 #size-cells = <1>;
530 ranges = <0x0 0x00 0x8 529 ranges = <0x0 0x00 0x8000000 0x100000>;
531 reg = <0x00 0x8000000 530 reg = <0x00 0x8000000 0x0 0x100000>;
532 interrupts = <GIC_SPI 531 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
533 dma-coherent; 532 dma-coherent;
534 533
535 sec_jr0: jr@10000 { 534 sec_jr0: jr@10000 {
536 compatible = " 535 compatible = "fsl,sec-v5.0-job-ring",
537 " 536 "fsl,sec-v4.0-job-ring";
538 reg = <0x10000 537 reg = <0x10000 0x10000>;
539 interrupts = < 538 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
540 }; 539 };
541 540
542 sec_jr1: jr@20000 { 541 sec_jr1: jr@20000 {
543 compatible = " 542 compatible = "fsl,sec-v5.0-job-ring",
544 " 543 "fsl,sec-v4.0-job-ring";
545 reg = <0x20000 544 reg = <0x20000 0x10000>;
546 interrupts = < 545 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
547 }; 546 };
548 547
549 sec_jr2: jr@30000 { 548 sec_jr2: jr@30000 {
550 compatible = " 549 compatible = "fsl,sec-v5.0-job-ring",
551 " 550 "fsl,sec-v4.0-job-ring";
552 reg = <0x30000 551 reg = <0x30000 0x10000>;
553 interrupts = < 552 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
554 }; 553 };
555 554
556 sec_jr3: jr@40000 { 555 sec_jr3: jr@40000 {
557 compatible = " 556 compatible = "fsl,sec-v5.0-job-ring",
558 " 557 "fsl,sec-v4.0-job-ring";
559 reg = <0x40000 558 reg = <0x40000 0x10000>;
560 interrupts = < 559 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
561 }; 560 };
562 }; 561 };
563 562
564 pcie1: pcie@3400000 { 563 pcie1: pcie@3400000 {
565 compatible = "fsl,ls10 564 compatible = "fsl,ls1088a-pcie";
566 reg = <0x00 0x03400000 565 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
567 <0x20 0x00000000 566 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
568 reg-names = "regs", "c 567 reg-names = "regs", "config";
569 interrupts = <GIC_SPI !! 568 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
570 interrupt-names = "aer 569 interrupt-names = "aer";
571 #address-cells = <3>; 570 #address-cells = <3>;
572 #size-cells = <2>; 571 #size-cells = <2>;
573 device_type = "pci"; 572 device_type = "pci";
574 dma-coherent; 573 dma-coherent;
575 num-viewport = <256>; 574 num-viewport = <256>;
576 bus-range = <0x0 0xff> 575 bus-range = <0x0 0xff>;
577 ranges = <0x81000000 0 576 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
578 0x82000000 0 577 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
579 msi-parent = <&its 0>; !! 578 msi-parent = <&its>;
580 #interrupt-cells = <1> 579 #interrupt-cells = <1>;
581 interrupt-map-mask = < 580 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0000 581 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 582 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 583 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
585 <0000 584 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
586 iommu-map = <0 &smmu 0 585 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
587 status = "disabled"; 586 status = "disabled";
588 }; 587 };
589 588
590 pcie_ep1: pcie-ep@3400000 { 589 pcie_ep1: pcie-ep@3400000 {
591 compatible = "fsl,ls10 !! 590 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
592 reg = <0x00 0x03400000 591 reg = <0x00 0x03400000 0x0 0x00100000>,
593 <0x20 0x00000000 592 <0x20 0x00000000 0x8 0x00000000>;
594 reg-names = "regs", "a 593 reg-names = "regs", "addr_space";
595 interrupts = <GIC_SPI <<
596 interrupt-names = "pme <<
597 num-ib-windows = <24>; 594 num-ib-windows = <24>;
598 num-ob-windows = <256> 595 num-ob-windows = <256>;
599 max-functions = /bits/ 596 max-functions = /bits/ 8 <2>;
600 status = "disabled"; 597 status = "disabled";
601 }; 598 };
602 599
603 pcie2: pcie@3500000 { 600 pcie2: pcie@3500000 {
604 compatible = "fsl,ls10 601 compatible = "fsl,ls1088a-pcie";
605 reg = <0x00 0x03500000 602 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
606 <0x28 0x00000000 603 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
607 reg-names = "regs", "c 604 reg-names = "regs", "config";
608 interrupts = <GIC_SPI !! 605 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
609 interrupt-names = "aer 606 interrupt-names = "aer";
610 #address-cells = <3>; 607 #address-cells = <3>;
611 #size-cells = <2>; 608 #size-cells = <2>;
612 device_type = "pci"; 609 device_type = "pci";
613 dma-coherent; 610 dma-coherent;
614 num-viewport = <6>; 611 num-viewport = <6>;
615 bus-range = <0x0 0xff> 612 bus-range = <0x0 0xff>;
616 ranges = <0x81000000 0 613 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
617 0x82000000 0 614 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
618 msi-parent = <&its 0>; !! 615 msi-parent = <&its>;
619 #interrupt-cells = <1> 616 #interrupt-cells = <1>;
620 interrupt-map-mask = < 617 interrupt-map-mask = <0 0 0 7>;
621 interrupt-map = <0000 618 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 619 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 620 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
624 <0000 621 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
625 iommu-map = <0 &smmu 0 622 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
626 status = "disabled"; 623 status = "disabled";
627 }; 624 };
628 625
629 pcie_ep2: pcie-ep@3500000 { 626 pcie_ep2: pcie-ep@3500000 {
630 compatible = "fsl,ls10 !! 627 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
631 reg = <0x00 0x03500000 628 reg = <0x00 0x03500000 0x0 0x00100000>,
632 <0x28 0x00000000 629 <0x28 0x00000000 0x8 0x00000000>;
633 reg-names = "regs", "a 630 reg-names = "regs", "addr_space";
634 interrupts = <GIC_SPI <<
635 interrupt-names = "pme <<
636 num-ib-windows = <6>; 631 num-ib-windows = <6>;
637 num-ob-windows = <6>; 632 num-ob-windows = <6>;
638 status = "disabled"; 633 status = "disabled";
639 }; 634 };
640 635
641 pcie3: pcie@3600000 { 636 pcie3: pcie@3600000 {
642 compatible = "fsl,ls10 637 compatible = "fsl,ls1088a-pcie";
643 reg = <0x00 0x03600000 638 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
644 <0x30 0x00000000 639 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
645 reg-names = "regs", "c 640 reg-names = "regs", "config";
646 interrupts = <GIC_SPI !! 641 interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */
647 interrupt-names = "aer 642 interrupt-names = "aer";
648 #address-cells = <3>; 643 #address-cells = <3>;
649 #size-cells = <2>; 644 #size-cells = <2>;
650 device_type = "pci"; 645 device_type = "pci";
651 dma-coherent; 646 dma-coherent;
652 num-viewport = <6>; 647 num-viewport = <6>;
653 bus-range = <0x0 0xff> 648 bus-range = <0x0 0xff>;
654 ranges = <0x81000000 0 649 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
655 0x82000000 0 650 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
656 msi-parent = <&its 0>; !! 651 msi-parent = <&its>;
657 #interrupt-cells = <1> 652 #interrupt-cells = <1>;
658 interrupt-map-mask = < 653 interrupt-map-mask = <0 0 0 7>;
659 interrupt-map = <0000 654 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 655 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 656 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
662 <0000 657 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
663 iommu-map = <0 &smmu 0 658 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
664 status = "disabled"; 659 status = "disabled";
665 }; 660 };
666 661
667 pcie_ep3: pcie-ep@3600000 { 662 pcie_ep3: pcie-ep@3600000 {
668 compatible = "fsl,ls10 !! 663 compatible = "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep";
669 reg = <0x00 0x03600000 664 reg = <0x00 0x03600000 0x0 0x00100000>,
670 <0x30 0x00000000 665 <0x30 0x00000000 0x8 0x00000000>;
671 reg-names = "regs", "a 666 reg-names = "regs", "addr_space";
672 interrupts = <GIC_SPI <<
673 interrupt-names = "pme <<
674 num-ib-windows = <6>; 667 num-ib-windows = <6>;
675 num-ob-windows = <6>; 668 num-ob-windows = <6>;
676 status = "disabled"; 669 status = "disabled";
677 }; 670 };
678 671
679 smmu: iommu@5000000 { 672 smmu: iommu@5000000 {
680 compatible = "arm,mmu- 673 compatible = "arm,mmu-500";
681 reg = <0 0x5000000 0 0 674 reg = <0 0x5000000 0 0x800000>;
682 #iommu-cells = <1>; 675 #iommu-cells = <1>;
683 stream-match-mask = <0 676 stream-match-mask = <0x7C00>;
684 dma-coherent; 677 dma-coherent;
685 #global-interrupts = < 678 #global-interrupts = <12>;
686 // global 679 // global secure fault
687 interrupts = <GIC_SPI 680 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
688 // combin 681 // combined secure
689 <GIC_SPI 682 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
690 // global 683 // global non-secure fault
691 <GIC_SPI 684 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
692 // combin 685 // combined non-secure
693 <GIC_SPI 686 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
694 // perfor 687 // performance counter interrupts 0-7
695 <GIC_SPI 688 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 689 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 690 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 691 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 692 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 693 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 694 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 695 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
703 // per co 696 // per context interrupt, 64 interrupts
704 <GIC_SPI 697 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 698 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
706 <GIC_SPI 699 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
707 <GIC_SPI 700 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 701 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
709 <GIC_SPI 702 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
710 <GIC_SPI 703 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
711 <GIC_SPI 704 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
712 <GIC_SPI 705 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
713 <GIC_SPI 706 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
714 <GIC_SPI 707 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
715 <GIC_SPI 708 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
716 <GIC_SPI 709 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
717 <GIC_SPI 710 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
718 <GIC_SPI 711 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
719 <GIC_SPI 712 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
720 <GIC_SPI 713 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
721 <GIC_SPI 714 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
722 <GIC_SPI 715 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
723 <GIC_SPI 716 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
724 <GIC_SPI 717 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
725 <GIC_SPI 718 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
726 <GIC_SPI 719 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
727 <GIC_SPI 720 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
728 <GIC_SPI 721 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
729 <GIC_SPI 722 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
730 <GIC_SPI 723 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
731 <GIC_SPI 724 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
732 <GIC_SPI 725 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
733 <GIC_SPI 726 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
734 <GIC_SPI 727 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
735 <GIC_SPI 728 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
736 <GIC_SPI 729 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
737 <GIC_SPI 730 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
738 <GIC_SPI 731 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
739 <GIC_SPI 732 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
740 <GIC_SPI 733 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
741 <GIC_SPI 734 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
742 <GIC_SPI 735 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
743 <GIC_SPI 736 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
744 <GIC_SPI 737 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
745 <GIC_SPI 738 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
746 <GIC_SPI 739 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
747 <GIC_SPI 740 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
748 <GIC_SPI 741 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 742 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
750 <GIC_SPI 743 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
751 <GIC_SPI 744 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
752 <GIC_SPI 745 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
753 <GIC_SPI 746 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
754 <GIC_SPI 747 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
755 <GIC_SPI 748 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
756 <GIC_SPI 749 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
757 <GIC_SPI 750 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
758 <GIC_SPI 751 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
759 <GIC_SPI 752 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
760 <GIC_SPI 753 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
761 <GIC_SPI 754 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
762 <GIC_SPI 755 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
763 <GIC_SPI 756 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
764 <GIC_SPI 757 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
765 <GIC_SPI 758 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
766 <GIC_SPI 759 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
767 <GIC_SPI 760 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
768 }; 761 };
769 762
770 console@8340020 { 763 console@8340020 {
771 compatible = "fsl,dpaa 764 compatible = "fsl,dpaa2-console";
772 reg = <0x00000000 0x08 765 reg = <0x00000000 0x08340020 0 0x2>;
773 }; 766 };
774 767
775 ptp-timer@8b95000 { 768 ptp-timer@8b95000 {
776 compatible = "fsl,dpaa 769 compatible = "fsl,dpaa2-ptp";
777 reg = <0x0 0x8b95000 0 770 reg = <0x0 0x8b95000 0x0 0x100>;
778 clocks = <&clockgen QO 771 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
779 QO 772 QORIQ_CLK_PLL_DIV(1)>;
780 little-endian; 773 little-endian;
781 fsl,extts-fifo; 774 fsl,extts-fifo;
782 }; 775 };
783 776
784 emdio1: mdio@8b96000 { 777 emdio1: mdio@8b96000 {
785 compatible = "fsl,fman 778 compatible = "fsl,fman-memac-mdio";
786 reg = <0x0 0x8b96000 0 779 reg = <0x0 0x8b96000 0x0 0x1000>;
787 little-endian; 780 little-endian;
788 #address-cells = <1>; 781 #address-cells = <1>;
789 #size-cells = <0>; 782 #size-cells = <0>;
790 clock-frequency = <250 783 clock-frequency = <2500000>;
791 clocks = <&clockgen QO 784 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
792 QO 785 QORIQ_CLK_PLL_DIV(1)>;
793 status = "disabled"; 786 status = "disabled";
794 }; 787 };
795 788
796 emdio2: mdio@8b97000 { 789 emdio2: mdio@8b97000 {
797 compatible = "fsl,fman 790 compatible = "fsl,fman-memac-mdio";
798 reg = <0x0 0x8b97000 0 791 reg = <0x0 0x8b97000 0x0 0x1000>;
799 little-endian; 792 little-endian;
800 #address-cells = <1>; 793 #address-cells = <1>;
801 #size-cells = <0>; 794 #size-cells = <0>;
802 clock-frequency = <250 795 clock-frequency = <2500000>;
803 clocks = <&clockgen QO 796 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
804 QO 797 QORIQ_CLK_PLL_DIV(1)>;
805 status = "disabled"; 798 status = "disabled";
806 }; 799 };
807 800
808 pcs_mdio1: mdio@8c07000 { 801 pcs_mdio1: mdio@8c07000 {
809 compatible = "fsl,fman 802 compatible = "fsl,fman-memac-mdio";
810 reg = <0x0 0x8c07000 0 803 reg = <0x0 0x8c07000 0x0 0x1000>;
811 little-endian; 804 little-endian;
812 #address-cells = <1>; 805 #address-cells = <1>;
813 #size-cells = <0>; 806 #size-cells = <0>;
814 status = "disabled"; 807 status = "disabled";
815 808
816 pcs1: ethernet-phy@0 { 809 pcs1: ethernet-phy@0 {
817 reg = <0>; 810 reg = <0>;
818 }; 811 };
819 }; 812 };
820 813
821 pcs_mdio2: mdio@8c0b000 { 814 pcs_mdio2: mdio@8c0b000 {
822 compatible = "fsl,fman 815 compatible = "fsl,fman-memac-mdio";
823 reg = <0x0 0x8c0b000 0 816 reg = <0x0 0x8c0b000 0x0 0x1000>;
824 little-endian; 817 little-endian;
825 #address-cells = <1>; 818 #address-cells = <1>;
826 #size-cells = <0>; 819 #size-cells = <0>;
827 status = "disabled"; 820 status = "disabled";
828 821
829 pcs2: ethernet-phy@0 { 822 pcs2: ethernet-phy@0 {
830 reg = <0>; 823 reg = <0>;
831 }; 824 };
832 }; 825 };
833 826
834 pcs_mdio3: mdio@8c0f000 { 827 pcs_mdio3: mdio@8c0f000 {
835 compatible = "fsl,fman 828 compatible = "fsl,fman-memac-mdio";
836 reg = <0x0 0x8c0f000 0 829 reg = <0x0 0x8c0f000 0x0 0x1000>;
837 little-endian; 830 little-endian;
838 #address-cells = <1>; 831 #address-cells = <1>;
839 #size-cells = <0>; 832 #size-cells = <0>;
840 status = "disabled"; 833 status = "disabled";
841 834
842 pcs3_0: ethernet-phy@0 835 pcs3_0: ethernet-phy@0 {
843 reg = <0>; 836 reg = <0>;
844 }; 837 };
845 838
846 pcs3_1: ethernet-phy@1 839 pcs3_1: ethernet-phy@1 {
847 reg = <1>; 840 reg = <1>;
848 }; 841 };
849 842
850 pcs3_2: ethernet-phy@2 843 pcs3_2: ethernet-phy@2 {
851 reg = <2>; 844 reg = <2>;
852 }; 845 };
853 846
854 pcs3_3: ethernet-phy@3 847 pcs3_3: ethernet-phy@3 {
855 reg = <3>; 848 reg = <3>;
856 }; 849 };
857 }; 850 };
858 851
859 pcs_mdio7: mdio@8c1f000 { 852 pcs_mdio7: mdio@8c1f000 {
860 compatible = "fsl,fman 853 compatible = "fsl,fman-memac-mdio";
861 reg = <0x0 0x8c1f000 0 854 reg = <0x0 0x8c1f000 0x0 0x1000>;
862 little-endian; 855 little-endian;
863 #address-cells = <1>; 856 #address-cells = <1>;
864 #size-cells = <0>; 857 #size-cells = <0>;
865 status = "disabled"; 858 status = "disabled";
866 859
867 pcs7_0: ethernet-phy@0 860 pcs7_0: ethernet-phy@0 {
868 reg = <0>; 861 reg = <0>;
869 }; 862 };
870 863
871 pcs7_1: ethernet-phy@1 864 pcs7_1: ethernet-phy@1 {
872 reg = <1>; 865 reg = <1>;
873 }; 866 };
874 867
875 pcs7_2: ethernet-phy@2 868 pcs7_2: ethernet-phy@2 {
876 reg = <2>; 869 reg = <2>;
877 }; 870 };
878 871
879 pcs7_3: ethernet-phy@3 872 pcs7_3: ethernet-phy@3 {
880 reg = <3>; 873 reg = <3>;
881 }; 874 };
882 }; 875 };
883 876
884 cluster1_core0_watchdog: watch !! 877 cluster1_core0_watchdog: wdt@c000000 {
885 compatible = "arm,sp80 878 compatible = "arm,sp805", "arm,primecell";
886 reg = <0x0 0xc000000 0 879 reg = <0x0 0xc000000 0x0 0x1000>;
887 clocks = <&clockgen QO 880 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
888 QO 881 QORIQ_CLK_PLL_DIV(16)>,
889 <&clockgen QO 882 <&clockgen QORIQ_CLK_PLATFORM_PLL
890 QO 883 QORIQ_CLK_PLL_DIV(16)>;
891 clock-names = "wdog_cl 884 clock-names = "wdog_clk", "apb_pclk";
892 }; 885 };
893 886
894 cluster1_core1_watchdog: watch !! 887 cluster1_core1_watchdog: wdt@c010000 {
895 compatible = "arm,sp80 888 compatible = "arm,sp805", "arm,primecell";
896 reg = <0x0 0xc010000 0 889 reg = <0x0 0xc010000 0x0 0x1000>;
897 clocks = <&clockgen QO 890 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
898 QO 891 QORIQ_CLK_PLL_DIV(16)>,
899 <&clockgen QO 892 <&clockgen QORIQ_CLK_PLATFORM_PLL
900 QO 893 QORIQ_CLK_PLL_DIV(16)>;
901 clock-names = "wdog_cl 894 clock-names = "wdog_clk", "apb_pclk";
902 }; 895 };
903 896
904 cluster1_core2_watchdog: watch !! 897 cluster1_core2_watchdog: wdt@c020000 {
905 compatible = "arm,sp80 898 compatible = "arm,sp805", "arm,primecell";
906 reg = <0x0 0xc020000 0 899 reg = <0x0 0xc020000 0x0 0x1000>;
907 clocks = <&clockgen QO 900 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
908 QO 901 QORIQ_CLK_PLL_DIV(16)>,
909 <&clockgen QO 902 <&clockgen QORIQ_CLK_PLATFORM_PLL
910 QO 903 QORIQ_CLK_PLL_DIV(16)>;
911 clock-names = "wdog_cl 904 clock-names = "wdog_clk", "apb_pclk";
912 }; 905 };
913 906
914 cluster1_core3_watchdog: watch !! 907 cluster1_core3_watchdog: wdt@c030000 {
915 compatible = "arm,sp80 908 compatible = "arm,sp805", "arm,primecell";
916 reg = <0x0 0xc030000 0 909 reg = <0x0 0xc030000 0x0 0x1000>;
917 clocks = <&clockgen QO 910 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
918 QO 911 QORIQ_CLK_PLL_DIV(16)>,
919 <&clockgen QO 912 <&clockgen QORIQ_CLK_PLATFORM_PLL
920 QO 913 QORIQ_CLK_PLL_DIV(16)>;
921 clock-names = "wdog_cl 914 clock-names = "wdog_clk", "apb_pclk";
922 }; 915 };
923 916
924 cluster2_core0_watchdog: watch !! 917 cluster2_core0_watchdog: wdt@c100000 {
925 compatible = "arm,sp80 918 compatible = "arm,sp805", "arm,primecell";
926 reg = <0x0 0xc100000 0 919 reg = <0x0 0xc100000 0x0 0x1000>;
927 clocks = <&clockgen QO 920 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
928 QO 921 QORIQ_CLK_PLL_DIV(16)>,
929 <&clockgen QO 922 <&clockgen QORIQ_CLK_PLATFORM_PLL
930 QO 923 QORIQ_CLK_PLL_DIV(16)>;
931 clock-names = "wdog_cl 924 clock-names = "wdog_clk", "apb_pclk";
932 }; 925 };
933 926
934 cluster2_core1_watchdog: watch !! 927 cluster2_core1_watchdog: wdt@c110000 {
935 compatible = "arm,sp80 928 compatible = "arm,sp805", "arm,primecell";
936 reg = <0x0 0xc110000 0 929 reg = <0x0 0xc110000 0x0 0x1000>;
937 clocks = <&clockgen QO 930 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
938 QO 931 QORIQ_CLK_PLL_DIV(16)>,
939 <&clockgen QO 932 <&clockgen QORIQ_CLK_PLATFORM_PLL
940 QO 933 QORIQ_CLK_PLL_DIV(16)>;
941 clock-names = "wdog_cl 934 clock-names = "wdog_clk", "apb_pclk";
942 }; 935 };
943 936
944 cluster2_core2_watchdog: watch !! 937 cluster2_core2_watchdog: wdt@c120000 {
945 compatible = "arm,sp80 938 compatible = "arm,sp805", "arm,primecell";
946 reg = <0x0 0xc120000 0 939 reg = <0x0 0xc120000 0x0 0x1000>;
947 clocks = <&clockgen QO 940 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
948 QO 941 QORIQ_CLK_PLL_DIV(16)>,
949 <&clockgen QO 942 <&clockgen QORIQ_CLK_PLATFORM_PLL
950 QO 943 QORIQ_CLK_PLL_DIV(16)>;
951 clock-names = "wdog_cl 944 clock-names = "wdog_clk", "apb_pclk";
952 }; 945 };
953 946
954 cluster2_core3_watchdog: watch !! 947 cluster2_core3_watchdog: wdt@c130000 {
955 compatible = "arm,sp80 948 compatible = "arm,sp805", "arm,primecell";
956 reg = <0x0 0xc130000 0 949 reg = <0x0 0xc130000 0x0 0x1000>;
957 clocks = <&clockgen QO 950 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
958 QO 951 QORIQ_CLK_PLL_DIV(16)>,
959 <&clockgen QO 952 <&clockgen QORIQ_CLK_PLATFORM_PLL
960 QO 953 QORIQ_CLK_PLL_DIV(16)>;
961 clock-names = "wdog_cl 954 clock-names = "wdog_clk", "apb_pclk";
962 }; 955 };
963 956
964 fsl_mc: fsl-mc@80c000000 { 957 fsl_mc: fsl-mc@80c000000 {
965 compatible = "fsl,qori 958 compatible = "fsl,qoriq-mc";
966 reg = <0x00000008 0x0c 959 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
967 <0x00000000 0x08 960 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
968 msi-parent = <&its 0>; !! 961 msi-parent = <&its>;
969 iommu-map = <0 &smmu 0 962 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
970 dma-coherent; 963 dma-coherent;
971 #address-cells = <3>; 964 #address-cells = <3>;
972 #size-cells = <1>; 965 #size-cells = <1>;
973 966
974 /* 967 /*
975 * Region type 0x0 - M 968 * Region type 0x0 - MC portals
976 * Region type 0x1 - Q 969 * Region type 0x1 - QBMAN portals
977 */ 970 */
978 ranges = <0x0 0x0 0x0 971 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
979 0x1 0x0 0x0 972 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
980 973
981 dpmacs { 974 dpmacs {
982 #address-cells 975 #address-cells = <1>;
983 #size-cells = 976 #size-cells = <0>;
984 977
985 dpmac1: ethern 978 dpmac1: ethernet@1 {
986 compat 979 compatible = "fsl,qoriq-mc-dpmac";
987 reg = 980 reg = <1>;
988 }; 981 };
989 982
990 dpmac2: ethern 983 dpmac2: ethernet@2 {
991 compat 984 compatible = "fsl,qoriq-mc-dpmac";
992 reg = 985 reg = <2>;
993 }; 986 };
994 987
995 dpmac3: ethern 988 dpmac3: ethernet@3 {
996 compat 989 compatible = "fsl,qoriq-mc-dpmac";
997 reg = 990 reg = <3>;
998 }; 991 };
999 992
1000 dpmac4: ether 993 dpmac4: ethernet@4 {
1001 compa 994 compatible = "fsl,qoriq-mc-dpmac";
1002 reg = 995 reg = <4>;
1003 }; 996 };
1004 997
1005 dpmac5: ether 998 dpmac5: ethernet@5 {
1006 compa 999 compatible = "fsl,qoriq-mc-dpmac";
1007 reg = 1000 reg = <5>;
1008 }; 1001 };
1009 1002
1010 dpmac6: ether 1003 dpmac6: ethernet@6 {
1011 compa 1004 compatible = "fsl,qoriq-mc-dpmac";
1012 reg = 1005 reg = <6>;
1013 }; 1006 };
1014 1007
1015 dpmac7: ether 1008 dpmac7: ethernet@7 {
1016 compa 1009 compatible = "fsl,qoriq-mc-dpmac";
1017 reg = 1010 reg = <7>;
1018 }; 1011 };
1019 1012
1020 dpmac8: ether 1013 dpmac8: ethernet@8 {
1021 compa 1014 compatible = "fsl,qoriq-mc-dpmac";
1022 reg = 1015 reg = <8>;
1023 }; 1016 };
1024 1017
1025 dpmac9: ether 1018 dpmac9: ethernet@9 {
1026 compa 1019 compatible = "fsl,qoriq-mc-dpmac";
1027 reg = 1020 reg = <9>;
1028 }; 1021 };
1029 1022
1030 dpmac10: ethe 1023 dpmac10: ethernet@a {
1031 compa 1024 compatible = "fsl,qoriq-mc-dpmac";
1032 reg = 1025 reg = <0xa>;
1033 }; 1026 };
1034 }; 1027 };
1035 }; 1028 };
1036 1029
1037 rcpm: wakeup-controller@1e340 !! 1030 rcpm: power-controller@1e34040 {
1038 compatible = "fsl,ls1 1031 compatible = "fsl,ls1088a-rcpm", "fsl,qoriq-rcpm-2.1+";
1039 reg = <0x0 0x1e34040 1032 reg = <0x0 0x1e34040 0x0 0x18>;
1040 #fsl,rcpm-wakeup-cell 1033 #fsl,rcpm-wakeup-cells = <6>;
1041 little-endian; 1034 little-endian;
1042 }; 1035 };
1043 1036
1044 ftm_alarm0: rtc@2800000 { !! 1037 ftm_alarm0: timer@2800000 {
1045 compatible = "fsl,ls1 1038 compatible = "fsl,ls1088a-ftm-alarm";
1046 reg = <0x0 0x2800000 1039 reg = <0x0 0x2800000 0x0 0x10000>;
1047 fsl,rcpm-wakeup = <&r 1040 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1048 interrupts = <GIC_SPI 1041 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1049 }; 1042 };
1050 }; 1043 };
1051 1044
1052 firmware { 1045 firmware {
1053 optee { 1046 optee {
1054 compatible = "linaro, 1047 compatible = "linaro,optee-tz";
1055 method = "smc"; 1048 method = "smc";
1056 }; 1049 };
1057 }; 1050 };
1058 }; 1051 };
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