1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree Include file for Freescale Laye
4 *
5 * Copyright 2014-2016 Freescale Semiconductor
6 *
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 * Bhupesh Sharma <bhupesh.sharma@freescale.com
9 *
10 */
11
12 #include <dt-bindings/clock/fsl,qoriq-clockgen
13 #include "fsl-ls208xa.dtsi"
14
15 / {
16 pmu {
17 compatible = "arm,cortex-a57-p
18 interrupts = <GIC_PPI 7 IRQ_TY
19 };
20 };
21
22 &cpu {
23 cpu0: cpu@0 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a57";
26 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_
28 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_
30 #cooling-cells = <2>;
31 };
32
33 cpu1: cpu@1 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a57";
36 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_
38 cpu-idle-states = <&CPU_PW20>;
39 next-level-cache = <&cluster0_
40 #cooling-cells = <2>;
41 };
42
43 cpu2: cpu@100 {
44 device_type = "cpu";
45 compatible = "arm,cortex-a57";
46 reg = <0x100>;
47 clocks = <&clockgen QORIQ_CLK_
48 cpu-idle-states = <&CPU_PW20>;
49 next-level-cache = <&cluster1_
50 #cooling-cells = <2>;
51 };
52
53 cpu3: cpu@101 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a57";
56 reg = <0x101>;
57 clocks = <&clockgen QORIQ_CLK_
58 cpu-idle-states = <&CPU_PW20>;
59 next-level-cache = <&cluster1_
60 #cooling-cells = <2>;
61 };
62
63 cpu4: cpu@200 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a57";
66 reg = <0x200>;
67 clocks = <&clockgen QORIQ_CLK_
68 cpu-idle-states = <&CPU_PW20>;
69 next-level-cache = <&cluster2_
70 #cooling-cells = <2>;
71 };
72
73 cpu5: cpu@201 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a57";
76 reg = <0x201>;
77 clocks = <&clockgen QORIQ_CLK_
78 cpu-idle-states = <&CPU_PW20>;
79 next-level-cache = <&cluster2_
80 #cooling-cells = <2>;
81 };
82
83 cpu6: cpu@300 {
84 device_type = "cpu";
85 compatible = "arm,cortex-a57";
86 reg = <0x300>;
87 clocks = <&clockgen QORIQ_CLK_
88 next-level-cache = <&cluster3_
89 cpu-idle-states = <&CPU_PW20>;
90 #cooling-cells = <2>;
91 };
92
93 cpu7: cpu@301 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a57";
96 reg = <0x301>;
97 clocks = <&clockgen QORIQ_CLK_
98 cpu-idle-states = <&CPU_PW20>;
99 next-level-cache = <&cluster3_
100 #cooling-cells = <2>;
101 };
102
103 cluster0_l2: l2-cache0 {
104 compatible = "cache";
105 cache-level = <2>;
106 cache-unified;
107 };
108
109 cluster1_l2: l2-cache1 {
110 compatible = "cache";
111 cache-level = <2>;
112 cache-unified;
113 };
114
115 cluster2_l2: l2-cache2 {
116 compatible = "cache";
117 cache-level = <2>;
118 cache-unified;
119 };
120
121 cluster3_l2: l2-cache3 {
122 compatible = "cache";
123 cache-level = <2>;
124 cache-unified;
125 };
126
127 CPU_PW20: cpu-pw20 {
128 compatible = "arm,idle-state";
129 idle-state-name = "PW20";
130 arm,psci-suspend-param = <0x00
131 entry-latency-us = <2000>;
132 exit-latency-us = <2000>;
133 min-residency-us = <6000>;
134 };
135 };
136
137 &pcie1 {
138 reg = <0x00 0x03400000 0x0 0x00100000>
139 <0x10 0x00000000 0x0 0x00002000>
140
141 ranges = <0x81000000 0x0 0x00000000 0x
142 0x82000000 0x0 0x40000000 0x
143 };
144
145 &pcie2 {
146 reg = <0x00 0x03500000 0x0 0x00100000>
147 <0x12 0x00000000 0x0 0x00002000>
148
149 ranges = <0x81000000 0x0 0x00000000 0x
150 0x82000000 0x0 0x40000000 0x
151 };
152
153 &pcie3 {
154 reg = <0x00 0x03600000 0x0 0x00100000>
155 <0x14 0x00000000 0x0 0x00002000>
156
157 ranges = <0x81000000 0x0 0x00000000 0x
158 0x82000000 0x0 0x40000000 0x
159 };
160
161 &pcie4 {
162 reg = <0x00 0x03700000 0x0 0x00100000>
163 <0x16 0x00000000 0x0 0x00002000>
164
165 ranges = <0x81000000 0x0 0x00000000 0x
166 0x82000000 0x0 0x40000000 0x
167 };
168
169 &timer {
170 fsl,erratum-a008585;
171 };
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