1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) <<
2 /* 1 /*
3 * Device Tree Include file for Freescale Laye 2 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * 3 *
5 * Copyright 2014-2016 Freescale Semiconductor 4 * Copyright 2014-2016 Freescale Semiconductor, Inc.
6 * 5 *
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 6 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 * Bhupesh Sharma <bhupesh.sharma@freescale.com 7 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
9 * 8 *
>> 9 * This file is dual-licensed: you can use it either under the terms
>> 10 * of the GPLv2 or the X11 license, at your option. Note that this dual
>> 11 * licensing only applies to this file, and not this project as a
>> 12 * whole.
>> 13 *
>> 14 * a) This library is free software; you can redistribute it and/or
>> 15 * modify it under the terms of the GNU General Public License as
>> 16 * published by the Free Software Foundation; either version 2 of the
>> 17 * License, or (at your option) any later version.
>> 18 *
>> 19 * This library is distributed in the hope that it will be useful,
>> 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> 22 * GNU General Public License for more details.
>> 23 *
>> 24 * Or, alternatively,
>> 25 *
>> 26 * b) Permission is hereby granted, free of charge, to any person
>> 27 * obtaining a copy of this software and associated documentation
>> 28 * files (the "Software"), to deal in the Software without
>> 29 * restriction, including without limitation the rights to use,
>> 30 * copy, modify, merge, publish, distribute, sublicense, and/or
>> 31 * sell copies of the Software, and to permit persons to whom the
>> 32 * Software is furnished to do so, subject to the following
>> 33 * conditions:
>> 34 *
>> 35 * The above copyright notice and this permission notice shall be
>> 36 * included in all copies or substantial portions of the Software.
>> 37 *
>> 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>> 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
>> 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>> 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
>> 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
>> 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
>> 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> 45 * OTHER DEALINGS IN THE SOFTWARE.
10 */ 46 */
11 47
12 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
13 #include "fsl-ls208xa.dtsi" 48 #include "fsl-ls208xa.dtsi"
14 49
15 / { <<
16 pmu { <<
17 compatible = "arm,cortex-a57-p <<
18 interrupts = <GIC_PPI 7 IRQ_TY <<
19 }; <<
20 }; <<
21 <<
22 &cpu { 50 &cpu {
23 cpu0: cpu@0 { 51 cpu0: cpu@0 {
24 device_type = "cpu"; 52 device_type = "cpu";
25 compatible = "arm,cortex-a57"; 53 compatible = "arm,cortex-a57";
26 reg = <0x0>; 54 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_ !! 55 clocks = <&clockgen 1 0>;
28 cpu-idle-states = <&CPU_PW20>; <<
29 next-level-cache = <&cluster0_ 56 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>; 57 #cooling-cells = <2>;
31 }; 58 };
32 59
33 cpu1: cpu@1 { 60 cpu1: cpu@1 {
34 device_type = "cpu"; 61 device_type = "cpu";
35 compatible = "arm,cortex-a57"; 62 compatible = "arm,cortex-a57";
36 reg = <0x1>; 63 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_ !! 64 clocks = <&clockgen 1 0>;
38 cpu-idle-states = <&CPU_PW20>; <<
39 next-level-cache = <&cluster0_ 65 next-level-cache = <&cluster0_l2>;
40 #cooling-cells = <2>; <<
41 }; 66 };
42 67
43 cpu2: cpu@100 { 68 cpu2: cpu@100 {
44 device_type = "cpu"; 69 device_type = "cpu";
45 compatible = "arm,cortex-a57"; 70 compatible = "arm,cortex-a57";
46 reg = <0x100>; 71 reg = <0x100>;
47 clocks = <&clockgen QORIQ_CLK_ !! 72 clocks = <&clockgen 1 1>;
48 cpu-idle-states = <&CPU_PW20>; <<
49 next-level-cache = <&cluster1_ 73 next-level-cache = <&cluster1_l2>;
50 #cooling-cells = <2>; 74 #cooling-cells = <2>;
51 }; 75 };
52 76
53 cpu3: cpu@101 { 77 cpu3: cpu@101 {
54 device_type = "cpu"; 78 device_type = "cpu";
55 compatible = "arm,cortex-a57"; 79 compatible = "arm,cortex-a57";
56 reg = <0x101>; 80 reg = <0x101>;
57 clocks = <&clockgen QORIQ_CLK_ !! 81 clocks = <&clockgen 1 1>;
58 cpu-idle-states = <&CPU_PW20>; <<
59 next-level-cache = <&cluster1_ 82 next-level-cache = <&cluster1_l2>;
60 #cooling-cells = <2>; <<
61 }; 83 };
62 84
63 cpu4: cpu@200 { 85 cpu4: cpu@200 {
64 device_type = "cpu"; 86 device_type = "cpu";
65 compatible = "arm,cortex-a57"; 87 compatible = "arm,cortex-a57";
66 reg = <0x200>; 88 reg = <0x200>;
67 clocks = <&clockgen QORIQ_CLK_ !! 89 clocks = <&clockgen 1 2>;
68 cpu-idle-states = <&CPU_PW20>; <<
69 next-level-cache = <&cluster2_ 90 next-level-cache = <&cluster2_l2>;
70 #cooling-cells = <2>; 91 #cooling-cells = <2>;
71 }; 92 };
72 93
73 cpu5: cpu@201 { 94 cpu5: cpu@201 {
74 device_type = "cpu"; 95 device_type = "cpu";
75 compatible = "arm,cortex-a57"; 96 compatible = "arm,cortex-a57";
76 reg = <0x201>; 97 reg = <0x201>;
77 clocks = <&clockgen QORIQ_CLK_ !! 98 clocks = <&clockgen 1 2>;
78 cpu-idle-states = <&CPU_PW20>; <<
79 next-level-cache = <&cluster2_ 99 next-level-cache = <&cluster2_l2>;
80 #cooling-cells = <2>; <<
81 }; 100 };
82 101
83 cpu6: cpu@300 { 102 cpu6: cpu@300 {
84 device_type = "cpu"; 103 device_type = "cpu";
85 compatible = "arm,cortex-a57"; 104 compatible = "arm,cortex-a57";
86 reg = <0x300>; 105 reg = <0x300>;
87 clocks = <&clockgen QORIQ_CLK_ !! 106 clocks = <&clockgen 1 3>;
88 next-level-cache = <&cluster3_ 107 next-level-cache = <&cluster3_l2>;
89 cpu-idle-states = <&CPU_PW20>; <<
90 #cooling-cells = <2>; 108 #cooling-cells = <2>;
91 }; 109 };
92 110
93 cpu7: cpu@301 { 111 cpu7: cpu@301 {
94 device_type = "cpu"; 112 device_type = "cpu";
95 compatible = "arm,cortex-a57"; 113 compatible = "arm,cortex-a57";
96 reg = <0x301>; 114 reg = <0x301>;
97 clocks = <&clockgen QORIQ_CLK_ !! 115 clocks = <&clockgen 1 3>;
98 cpu-idle-states = <&CPU_PW20>; <<
99 next-level-cache = <&cluster3_ 116 next-level-cache = <&cluster3_l2>;
100 #cooling-cells = <2>; <<
101 }; 117 };
102 118
103 cluster0_l2: l2-cache0 { 119 cluster0_l2: l2-cache0 {
104 compatible = "cache"; 120 compatible = "cache";
105 cache-level = <2>; <<
106 cache-unified; <<
107 }; 121 };
108 122
109 cluster1_l2: l2-cache1 { 123 cluster1_l2: l2-cache1 {
110 compatible = "cache"; 124 compatible = "cache";
111 cache-level = <2>; <<
112 cache-unified; <<
113 }; 125 };
114 126
115 cluster2_l2: l2-cache2 { 127 cluster2_l2: l2-cache2 {
116 compatible = "cache"; 128 compatible = "cache";
117 cache-level = <2>; <<
118 cache-unified; <<
119 }; 129 };
120 130
121 cluster3_l2: l2-cache3 { 131 cluster3_l2: l2-cache3 {
122 compatible = "cache"; 132 compatible = "cache";
123 cache-level = <2>; <<
124 cache-unified; <<
125 }; <<
126 <<
127 CPU_PW20: cpu-pw20 { <<
128 compatible = "arm,idle-state"; <<
129 idle-state-name = "PW20"; <<
130 arm,psci-suspend-param = <0x00 <<
131 entry-latency-us = <2000>; <<
132 exit-latency-us = <2000>; <<
133 min-residency-us = <6000>; <<
134 }; 133 };
135 }; 134 };
136 135
137 &pcie1 { 136 &pcie1 {
138 reg = <0x00 0x03400000 0x0 0x00100000> !! 137 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
139 <0x10 0x00000000 0x0 0x00002000> !! 138 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
140 139
141 ranges = <0x81000000 0x0 0x00000000 0x 140 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x 141 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
143 }; 142 };
144 143
145 &pcie2 { 144 &pcie2 {
146 reg = <0x00 0x03500000 0x0 0x00100000> !! 145 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
147 <0x12 0x00000000 0x0 0x00002000> !! 146 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
148 147
149 ranges = <0x81000000 0x0 0x00000000 0x 148 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x 149 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
151 }; 150 };
152 151
153 &pcie3 { 152 &pcie3 {
154 reg = <0x00 0x03600000 0x0 0x00100000> !! 153 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
155 <0x14 0x00000000 0x0 0x00002000> !! 154 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
156 155
157 ranges = <0x81000000 0x0 0x00000000 0x 156 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
158 0x82000000 0x0 0x40000000 0x 157 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
159 }; 158 };
160 159
161 &pcie4 { 160 &pcie4 {
162 reg = <0x00 0x03700000 0x0 0x00100000> !! 161 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
163 <0x16 0x00000000 0x0 0x00002000> !! 162 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
164 163
165 ranges = <0x81000000 0x0 0x00000000 0x 164 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
166 0x82000000 0x0 0x40000000 0x 165 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
167 }; <<
168 <<
169 &timer { <<
170 fsl,erratum-a008585; <<
171 }; 166 };
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