1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Freescale Laye 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * 4 *
5 * Copyright 2014-2016 Freescale Semiconductor 5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
6 * 6 *
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 * Bhupesh Sharma <bhupesh.sharma@freescale.com 8 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
9 * 9 *
10 */ 10 */
11 11
12 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
13 #include "fsl-ls208xa.dtsi" 12 #include "fsl-ls208xa.dtsi"
14 13
15 / { <<
16 pmu { <<
17 compatible = "arm,cortex-a57-p <<
18 interrupts = <GIC_PPI 7 IRQ_TY <<
19 }; <<
20 }; <<
21 <<
22 &cpu { 14 &cpu {
23 cpu0: cpu@0 { 15 cpu0: cpu@0 {
24 device_type = "cpu"; 16 device_type = "cpu";
25 compatible = "arm,cortex-a57"; 17 compatible = "arm,cortex-a57";
26 reg = <0x0>; 18 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_ !! 19 clocks = <&clockgen 1 0>;
28 cpu-idle-states = <&CPU_PW20>; 20 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_ 21 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>; 22 #cooling-cells = <2>;
31 }; 23 };
32 24
33 cpu1: cpu@1 { 25 cpu1: cpu@1 {
34 device_type = "cpu"; 26 device_type = "cpu";
35 compatible = "arm,cortex-a57"; 27 compatible = "arm,cortex-a57";
36 reg = <0x1>; 28 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_ !! 29 clocks = <&clockgen 1 0>;
38 cpu-idle-states = <&CPU_PW20>; 30 cpu-idle-states = <&CPU_PW20>;
39 next-level-cache = <&cluster0_ 31 next-level-cache = <&cluster0_l2>;
40 #cooling-cells = <2>; 32 #cooling-cells = <2>;
41 }; 33 };
42 34
43 cpu2: cpu@100 { 35 cpu2: cpu@100 {
44 device_type = "cpu"; 36 device_type = "cpu";
45 compatible = "arm,cortex-a57"; 37 compatible = "arm,cortex-a57";
46 reg = <0x100>; 38 reg = <0x100>;
47 clocks = <&clockgen QORIQ_CLK_ !! 39 clocks = <&clockgen 1 1>;
48 cpu-idle-states = <&CPU_PW20>; 40 cpu-idle-states = <&CPU_PW20>;
49 next-level-cache = <&cluster1_ 41 next-level-cache = <&cluster1_l2>;
50 #cooling-cells = <2>; 42 #cooling-cells = <2>;
51 }; 43 };
52 44
53 cpu3: cpu@101 { 45 cpu3: cpu@101 {
54 device_type = "cpu"; 46 device_type = "cpu";
55 compatible = "arm,cortex-a57"; 47 compatible = "arm,cortex-a57";
56 reg = <0x101>; 48 reg = <0x101>;
57 clocks = <&clockgen QORIQ_CLK_ !! 49 clocks = <&clockgen 1 1>;
58 cpu-idle-states = <&CPU_PW20>; 50 cpu-idle-states = <&CPU_PW20>;
59 next-level-cache = <&cluster1_ 51 next-level-cache = <&cluster1_l2>;
60 #cooling-cells = <2>; 52 #cooling-cells = <2>;
61 }; 53 };
62 54
63 cpu4: cpu@200 { 55 cpu4: cpu@200 {
64 device_type = "cpu"; 56 device_type = "cpu";
65 compatible = "arm,cortex-a57"; 57 compatible = "arm,cortex-a57";
66 reg = <0x200>; 58 reg = <0x200>;
67 clocks = <&clockgen QORIQ_CLK_ !! 59 clocks = <&clockgen 1 2>;
68 cpu-idle-states = <&CPU_PW20>; 60 cpu-idle-states = <&CPU_PW20>;
69 next-level-cache = <&cluster2_ 61 next-level-cache = <&cluster2_l2>;
70 #cooling-cells = <2>; 62 #cooling-cells = <2>;
71 }; 63 };
72 64
73 cpu5: cpu@201 { 65 cpu5: cpu@201 {
74 device_type = "cpu"; 66 device_type = "cpu";
75 compatible = "arm,cortex-a57"; 67 compatible = "arm,cortex-a57";
76 reg = <0x201>; 68 reg = <0x201>;
77 clocks = <&clockgen QORIQ_CLK_ !! 69 clocks = <&clockgen 1 2>;
78 cpu-idle-states = <&CPU_PW20>; 70 cpu-idle-states = <&CPU_PW20>;
79 next-level-cache = <&cluster2_ 71 next-level-cache = <&cluster2_l2>;
80 #cooling-cells = <2>; 72 #cooling-cells = <2>;
81 }; 73 };
82 74
83 cpu6: cpu@300 { 75 cpu6: cpu@300 {
84 device_type = "cpu"; 76 device_type = "cpu";
85 compatible = "arm,cortex-a57"; 77 compatible = "arm,cortex-a57";
86 reg = <0x300>; 78 reg = <0x300>;
87 clocks = <&clockgen QORIQ_CLK_ !! 79 clocks = <&clockgen 1 3>;
88 next-level-cache = <&cluster3_ 80 next-level-cache = <&cluster3_l2>;
89 cpu-idle-states = <&CPU_PW20>; 81 cpu-idle-states = <&CPU_PW20>;
90 #cooling-cells = <2>; 82 #cooling-cells = <2>;
91 }; 83 };
92 84
93 cpu7: cpu@301 { 85 cpu7: cpu@301 {
94 device_type = "cpu"; 86 device_type = "cpu";
95 compatible = "arm,cortex-a57"; 87 compatible = "arm,cortex-a57";
96 reg = <0x301>; 88 reg = <0x301>;
97 clocks = <&clockgen QORIQ_CLK_ !! 89 clocks = <&clockgen 1 3>;
98 cpu-idle-states = <&CPU_PW20>; 90 cpu-idle-states = <&CPU_PW20>;
99 next-level-cache = <&cluster3_ 91 next-level-cache = <&cluster3_l2>;
100 #cooling-cells = <2>; 92 #cooling-cells = <2>;
101 }; 93 };
102 94
103 cluster0_l2: l2-cache0 { 95 cluster0_l2: l2-cache0 {
104 compatible = "cache"; 96 compatible = "cache";
105 cache-level = <2>; <<
106 cache-unified; <<
107 }; 97 };
108 98
109 cluster1_l2: l2-cache1 { 99 cluster1_l2: l2-cache1 {
110 compatible = "cache"; 100 compatible = "cache";
111 cache-level = <2>; <<
112 cache-unified; <<
113 }; 101 };
114 102
115 cluster2_l2: l2-cache2 { 103 cluster2_l2: l2-cache2 {
116 compatible = "cache"; 104 compatible = "cache";
117 cache-level = <2>; <<
118 cache-unified; <<
119 }; 105 };
120 106
121 cluster3_l2: l2-cache3 { 107 cluster3_l2: l2-cache3 {
122 compatible = "cache"; 108 compatible = "cache";
123 cache-level = <2>; <<
124 cache-unified; <<
125 }; 109 };
126 110
127 CPU_PW20: cpu-pw20 { 111 CPU_PW20: cpu-pw20 {
128 compatible = "arm,idle-state"; 112 compatible = "arm,idle-state";
129 idle-state-name = "PW20"; 113 idle-state-name = "PW20";
130 arm,psci-suspend-param = <0x00 114 arm,psci-suspend-param = <0x00010000>;
131 entry-latency-us = <2000>; 115 entry-latency-us = <2000>;
132 exit-latency-us = <2000>; 116 exit-latency-us = <2000>;
133 min-residency-us = <6000>; 117 min-residency-us = <6000>;
134 }; 118 };
135 }; 119 };
136 120
137 &pcie1 { 121 &pcie1 {
138 reg = <0x00 0x03400000 0x0 0x00100000> !! 122 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
139 <0x10 0x00000000 0x0 0x00002000> !! 123 0x10 0x00000000 0x0 0x00002000>; /* configuration space */
140 124
141 ranges = <0x81000000 0x0 0x00000000 0x 125 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x 126 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
143 }; 127 };
144 128
145 &pcie2 { 129 &pcie2 {
146 reg = <0x00 0x03500000 0x0 0x00100000> !! 130 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
147 <0x12 0x00000000 0x0 0x00002000> !! 131 0x12 0x00000000 0x0 0x00002000>; /* configuration space */
148 132
149 ranges = <0x81000000 0x0 0x00000000 0x 133 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x 134 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
151 }; 135 };
152 136
153 &pcie3 { 137 &pcie3 {
154 reg = <0x00 0x03600000 0x0 0x00100000> !! 138 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
155 <0x14 0x00000000 0x0 0x00002000> !! 139 0x14 0x00000000 0x0 0x00002000>; /* configuration space */
156 140
157 ranges = <0x81000000 0x0 0x00000000 0x 141 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
158 0x82000000 0x0 0x40000000 0x 142 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
159 }; 143 };
160 144
161 &pcie4 { 145 &pcie4 {
162 reg = <0x00 0x03700000 0x0 0x00100000> !! 146 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
163 <0x16 0x00000000 0x0 0x00002000> !! 147 0x16 0x00000000 0x0 0x00002000>; /* configuration space */
164 148
165 ranges = <0x81000000 0x0 0x00000000 0x 149 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
166 0x82000000 0x0 0x40000000 0x 150 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
167 }; <<
168 <<
169 &timer { <<
170 fsl,erratum-a008585; <<
171 }; 151 };
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