1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Device Tree Include file for Freescale Laye 3 * Device Tree Include file for Freescale Layerscape-2080A family SoC.
4 * 4 *
5 * Copyright 2014-2016 Freescale Semiconductor 5 * Copyright 2014-2016 Freescale Semiconductor, Inc.
6 * 6 *
7 * Abhimanyu Saini <abhimanyu.saini@nxp.com> 7 * Abhimanyu Saini <abhimanyu.saini@nxp.com>
8 * Bhupesh Sharma <bhupesh.sharma@freescale.com 8 * Bhupesh Sharma <bhupesh.sharma@freescale.com>
9 * 9 *
10 */ 10 */
11 11
12 #include <dt-bindings/clock/fsl,qoriq-clockgen 12 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
13 #include "fsl-ls208xa.dtsi" 13 #include "fsl-ls208xa.dtsi"
14 14
15 / { <<
16 pmu { <<
17 compatible = "arm,cortex-a57-p <<
18 interrupts = <GIC_PPI 7 IRQ_TY <<
19 }; <<
20 }; <<
21 <<
22 &cpu { 15 &cpu {
23 cpu0: cpu@0 { 16 cpu0: cpu@0 {
24 device_type = "cpu"; 17 device_type = "cpu";
25 compatible = "arm,cortex-a57"; 18 compatible = "arm,cortex-a57";
26 reg = <0x0>; 19 reg = <0x0>;
27 clocks = <&clockgen QORIQ_CLK_ 20 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
28 cpu-idle-states = <&CPU_PW20>; 21 cpu-idle-states = <&CPU_PW20>;
29 next-level-cache = <&cluster0_ 22 next-level-cache = <&cluster0_l2>;
30 #cooling-cells = <2>; 23 #cooling-cells = <2>;
31 }; 24 };
32 25
33 cpu1: cpu@1 { 26 cpu1: cpu@1 {
34 device_type = "cpu"; 27 device_type = "cpu";
35 compatible = "arm,cortex-a57"; 28 compatible = "arm,cortex-a57";
36 reg = <0x1>; 29 reg = <0x1>;
37 clocks = <&clockgen QORIQ_CLK_ 30 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
38 cpu-idle-states = <&CPU_PW20>; 31 cpu-idle-states = <&CPU_PW20>;
39 next-level-cache = <&cluster0_ 32 next-level-cache = <&cluster0_l2>;
40 #cooling-cells = <2>; 33 #cooling-cells = <2>;
41 }; 34 };
42 35
43 cpu2: cpu@100 { 36 cpu2: cpu@100 {
44 device_type = "cpu"; 37 device_type = "cpu";
45 compatible = "arm,cortex-a57"; 38 compatible = "arm,cortex-a57";
46 reg = <0x100>; 39 reg = <0x100>;
47 clocks = <&clockgen QORIQ_CLK_ 40 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
48 cpu-idle-states = <&CPU_PW20>; 41 cpu-idle-states = <&CPU_PW20>;
49 next-level-cache = <&cluster1_ 42 next-level-cache = <&cluster1_l2>;
50 #cooling-cells = <2>; 43 #cooling-cells = <2>;
51 }; 44 };
52 45
53 cpu3: cpu@101 { 46 cpu3: cpu@101 {
54 device_type = "cpu"; 47 device_type = "cpu";
55 compatible = "arm,cortex-a57"; 48 compatible = "arm,cortex-a57";
56 reg = <0x101>; 49 reg = <0x101>;
57 clocks = <&clockgen QORIQ_CLK_ 50 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
58 cpu-idle-states = <&CPU_PW20>; 51 cpu-idle-states = <&CPU_PW20>;
59 next-level-cache = <&cluster1_ 52 next-level-cache = <&cluster1_l2>;
60 #cooling-cells = <2>; 53 #cooling-cells = <2>;
61 }; 54 };
62 55
63 cpu4: cpu@200 { 56 cpu4: cpu@200 {
64 device_type = "cpu"; 57 device_type = "cpu";
65 compatible = "arm,cortex-a57"; 58 compatible = "arm,cortex-a57";
66 reg = <0x200>; 59 reg = <0x200>;
67 clocks = <&clockgen QORIQ_CLK_ 60 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
68 cpu-idle-states = <&CPU_PW20>; 61 cpu-idle-states = <&CPU_PW20>;
69 next-level-cache = <&cluster2_ 62 next-level-cache = <&cluster2_l2>;
70 #cooling-cells = <2>; 63 #cooling-cells = <2>;
71 }; 64 };
72 65
73 cpu5: cpu@201 { 66 cpu5: cpu@201 {
74 device_type = "cpu"; 67 device_type = "cpu";
75 compatible = "arm,cortex-a57"; 68 compatible = "arm,cortex-a57";
76 reg = <0x201>; 69 reg = <0x201>;
77 clocks = <&clockgen QORIQ_CLK_ 70 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
78 cpu-idle-states = <&CPU_PW20>; 71 cpu-idle-states = <&CPU_PW20>;
79 next-level-cache = <&cluster2_ 72 next-level-cache = <&cluster2_l2>;
80 #cooling-cells = <2>; 73 #cooling-cells = <2>;
81 }; 74 };
82 75
83 cpu6: cpu@300 { 76 cpu6: cpu@300 {
84 device_type = "cpu"; 77 device_type = "cpu";
85 compatible = "arm,cortex-a57"; 78 compatible = "arm,cortex-a57";
86 reg = <0x300>; 79 reg = <0x300>;
87 clocks = <&clockgen QORIQ_CLK_ 80 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
88 next-level-cache = <&cluster3_ 81 next-level-cache = <&cluster3_l2>;
89 cpu-idle-states = <&CPU_PW20>; 82 cpu-idle-states = <&CPU_PW20>;
90 #cooling-cells = <2>; 83 #cooling-cells = <2>;
91 }; 84 };
92 85
93 cpu7: cpu@301 { 86 cpu7: cpu@301 {
94 device_type = "cpu"; 87 device_type = "cpu";
95 compatible = "arm,cortex-a57"; 88 compatible = "arm,cortex-a57";
96 reg = <0x301>; 89 reg = <0x301>;
97 clocks = <&clockgen QORIQ_CLK_ 90 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
98 cpu-idle-states = <&CPU_PW20>; 91 cpu-idle-states = <&CPU_PW20>;
99 next-level-cache = <&cluster3_ 92 next-level-cache = <&cluster3_l2>;
100 #cooling-cells = <2>; 93 #cooling-cells = <2>;
101 }; 94 };
102 95
103 cluster0_l2: l2-cache0 { 96 cluster0_l2: l2-cache0 {
104 compatible = "cache"; 97 compatible = "cache";
105 cache-level = <2>; 98 cache-level = <2>;
106 cache-unified; <<
107 }; 99 };
108 100
109 cluster1_l2: l2-cache1 { 101 cluster1_l2: l2-cache1 {
110 compatible = "cache"; 102 compatible = "cache";
111 cache-level = <2>; 103 cache-level = <2>;
112 cache-unified; <<
113 }; 104 };
114 105
115 cluster2_l2: l2-cache2 { 106 cluster2_l2: l2-cache2 {
116 compatible = "cache"; 107 compatible = "cache";
117 cache-level = <2>; 108 cache-level = <2>;
118 cache-unified; <<
119 }; 109 };
120 110
121 cluster3_l2: l2-cache3 { 111 cluster3_l2: l2-cache3 {
122 compatible = "cache"; 112 compatible = "cache";
123 cache-level = <2>; 113 cache-level = <2>;
124 cache-unified; <<
125 }; 114 };
126 115
127 CPU_PW20: cpu-pw20 { 116 CPU_PW20: cpu-pw20 {
128 compatible = "arm,idle-state"; 117 compatible = "arm,idle-state";
129 idle-state-name = "PW20"; 118 idle-state-name = "PW20";
130 arm,psci-suspend-param = <0x00 119 arm,psci-suspend-param = <0x00010000>;
131 entry-latency-us = <2000>; 120 entry-latency-us = <2000>;
132 exit-latency-us = <2000>; 121 exit-latency-us = <2000>;
133 min-residency-us = <6000>; 122 min-residency-us = <6000>;
134 }; 123 };
135 }; 124 };
136 125
137 &pcie1 { 126 &pcie1 {
138 reg = <0x00 0x03400000 0x0 0x00100000> 127 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
139 <0x10 0x00000000 0x0 0x00002000> 128 <0x10 0x00000000 0x0 0x00002000>; /* configuration space */
140 129
141 ranges = <0x81000000 0x0 0x00000000 0x 130 ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
142 0x82000000 0x0 0x40000000 0x 131 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
143 }; 132 };
144 133
145 &pcie2 { 134 &pcie2 {
146 reg = <0x00 0x03500000 0x0 0x00100000> 135 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
147 <0x12 0x00000000 0x0 0x00002000> 136 <0x12 0x00000000 0x0 0x00002000>; /* configuration space */
148 137
149 ranges = <0x81000000 0x0 0x00000000 0x 138 ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
150 0x82000000 0x0 0x40000000 0x 139 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
151 }; 140 };
152 141
153 &pcie3 { 142 &pcie3 {
154 reg = <0x00 0x03600000 0x0 0x00100000> 143 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
155 <0x14 0x00000000 0x0 0x00002000> 144 <0x14 0x00000000 0x0 0x00002000>; /* configuration space */
156 145
157 ranges = <0x81000000 0x0 0x00000000 0x 146 ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
158 0x82000000 0x0 0x40000000 0x 147 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
159 }; 148 };
160 149
161 &pcie4 { 150 &pcie4 {
162 reg = <0x00 0x03700000 0x0 0x00100000> 151 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
163 <0x16 0x00000000 0x0 0x00002000> 152 <0x16 0x00000000 0x0 0x00002000>; /* configuration space */
164 153
165 ranges = <0x81000000 0x0 0x00000000 0x 154 ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
166 0x82000000 0x0 0x40000000 0x 155 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
167 }; 156 };
168 157
169 &timer { 158 &timer {
170 fsl,erratum-a008585; 159 fsl,erratum-a008585;
171 }; 160 };
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