1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Device Tree file for LX2160ARDB
4 //
5 // Copyright 2018-2020 NXP
6
7 /dts-v1/;
8
9 #include "fsl-lx2160a.dtsi"
10
11 / {
12 model = "NXP Layerscape LX2160ARDB";
13 compatible = "fsl,lx2160a-rdb", "fsl,l
14
15 aliases {
16 crypto = &crypto;
17 mmc0 = &esdhc0;
18 mmc1 = &esdhc1;
19 serial0 = &uart0;
20 };
21
22 chosen {
23 stdout-path = "serial0:115200n
24 };
25
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed"
28 regulator-name = "MC34717-3.3V
29 regulator-min-microvolt = <330
30 regulator-max-microvolt = <330
31 regulator-boot-on;
32 regulator-always-on;
33 };
34 };
35
36 &crypto {
37 status = "okay";
38 };
39
40 &dpmac3 {
41 phy-handle = <&aquantia_phy1>;
42 phy-connection-type = "usxgmii";
43 managed = "in-band-status";
44 };
45
46 &dpmac4 {
47 phy-handle = <&aquantia_phy2>;
48 phy-connection-type = "usxgmii";
49 managed = "in-band-status";
50 };
51
52 &dpmac5 {
53 phy-handle = <&inphi_phy>;
54 };
55
56 &dpmac6 {
57 phy-handle = <&inphi_phy>;
58 };
59
60 &dpmac17 {
61 phy-handle = <&rgmii_phy1>;
62 phy-connection-type = "rgmii-id";
63 };
64
65 &dpmac18 {
66 phy-handle = <&rgmii_phy2>;
67 phy-connection-type = "rgmii-id";
68 };
69
70 &emdio1 {
71 status = "okay";
72
73 rgmii_phy1: ethernet-phy@1 {
74 /* AR8035 PHY */
75 compatible = "ethernet-phy-id0
76 interrupts-extended = <&extirq
77 reg = <0x1>;
78 eee-broken-1000t;
79 };
80
81 rgmii_phy2: ethernet-phy@2 {
82 /* AR8035 PHY */
83 compatible = "ethernet-phy-id0
84 interrupts-extended = <&extirq
85 reg = <0x2>;
86 eee-broken-1000t;
87 };
88
89 aquantia_phy1: ethernet-phy@4 {
90 /* AQR107 PHY */
91 compatible = "ethernet-phy-iee
92 interrupts-extended = <&extirq
93 reg = <0x4>;
94 };
95
96 aquantia_phy2: ethernet-phy@5 {
97 /* AQR107 PHY */
98 compatible = "ethernet-phy-iee
99 interrupts-extended = <&extirq
100 reg = <0x5>;
101 };
102 };
103
104 &can0 {
105 status = "okay";
106
107 can-transceiver {
108 max-bitrate = <5000000>;
109 };
110 };
111
112 &can1 {
113 status = "okay";
114
115 can-transceiver {
116 max-bitrate = <5000000>;
117 };
118 };
119
120 &emdio2 {
121 status = "okay";
122
123 inphi_phy: ethernet-phy@0 {
124 compatible = "ethernet-phy-id0
125 reg = <0x0>;
126 };
127 };
128
129 &esdhc0 {
130 sd-uhs-sdr104;
131 sd-uhs-sdr50;
132 sd-uhs-sdr25;
133 sd-uhs-sdr12;
134 status = "okay";
135 };
136
137 &esdhc1 {
138 mmc-hs200-1_8v;
139 mmc-hs400-1_8v;
140 bus-width = <8>;
141 status = "okay";
142 };
143
144 &fspi {
145 status = "okay";
146
147 mt35xu512aba0: flash@0 {
148 #address-cells = <1>;
149 #size-cells = <1>;
150 compatible = "jedec,spi-nor";
151 m25p,fast-read;
152 spi-max-frequency = <50000000>
153 reg = <0>;
154 spi-rx-bus-width = <8>;
155 spi-tx-bus-width = <8>;
156 };
157
158 mt35xu512aba1: flash@1 {
159 #address-cells = <1>;
160 #size-cells = <1>;
161 compatible = "jedec,spi-nor";
162 m25p,fast-read;
163 spi-max-frequency = <50000000>
164 reg = <1>;
165 spi-rx-bus-width = <8>;
166 spi-tx-bus-width = <8>;
167 };
168 };
169
170 &i2c0 {
171 status = "okay";
172
173 i2c-mux@77 {
174 compatible = "nxp,pca9547";
175 reg = <0x77>;
176 #address-cells = <1>;
177 #size-cells = <0>;
178
179 i2c@2 {
180 #address-cells = <1>;
181 #size-cells = <0>;
182 reg = <0x2>;
183
184 power-monitor@40 {
185 compatible = "
186 reg = <0x40>;
187 shunt-resistor
188 };
189 };
190
191 i2c@3 {
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <0x3>;
195
196 temperature-sensor@4c
197 compatible = "
198 reg = <0x4c>;
199 vcc-supply = <
200 };
201
202 temperature-sensor@4d
203 compatible = "
204 reg = <0x4d>;
205 vcc-supply = <
206 };
207 };
208 };
209 };
210
211 &i2c4 {
212 status = "okay";
213
214 rtc@51 {
215 compatible = "nxp,pcf2129";
216 reg = <0x51>;
217 /* IRQ_RTC_B -> IRQ08, active
218 interrupts-extended = <&extirq
219 };
220 };
221
222 &optee {
223 status = "okay";
224 };
225
226 &pcs_mdio3 {
227 status = "okay";
228 };
229
230 &pcs_mdio4 {
231 status = "okay";
232 };
233
234 &sata0 {
235 status = "okay";
236 };
237
238 &sata1 {
239 status = "okay";
240 };
241
242 &sata2 {
243 status = "okay";
244 };
245
246 &sata3 {
247 status = "okay";
248 };
249
250 &uart0 {
251 status = "okay";
252 };
253
254 &uart1 {
255 status = "okay";
256 };
257
258 &usb0 {
259 status = "okay";
260 };
261
262 &usb1 {
263 status = "okay";
264 };
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