1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree file for LX2160ARDB 3 // Device Tree file for LX2160ARDB
4 // 4 //
5 // Copyright 2018-2020 NXP !! 5 // Copyright 2018 NXP
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "fsl-lx2160a.dtsi" 9 #include "fsl-lx2160a.dtsi"
10 10
11 / { 11 / {
12 model = "NXP Layerscape LX2160ARDB"; 12 model = "NXP Layerscape LX2160ARDB";
13 compatible = "fsl,lx2160a-rdb", "fsl,l 13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
14 14
15 aliases { 15 aliases {
16 crypto = &crypto; 16 crypto = &crypto;
17 mmc0 = &esdhc0; <<
18 mmc1 = &esdhc1; <<
19 serial0 = &uart0; 17 serial0 = &uart0;
20 }; 18 };
21 19
22 chosen { 20 chosen {
23 stdout-path = "serial0:115200n 21 stdout-path = "serial0:115200n8";
24 }; 22 };
25 23
26 sb_3v3: regulator-sb3v3 { 24 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3V 26 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <330 27 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <330 28 regulator-max-microvolt = <3300000>;
31 regulator-boot-on; 29 regulator-boot-on;
32 regulator-always-on; 30 regulator-always-on;
33 }; 31 };
34 }; 32 };
35 33
36 &crypto { 34 &crypto {
37 status = "okay"; 35 status = "okay";
38 }; 36 };
39 37
40 &dpmac3 { <<
41 phy-handle = <&aquantia_phy1>; <<
42 phy-connection-type = "usxgmii"; <<
43 managed = "in-band-status"; <<
44 }; <<
45 <<
46 &dpmac4 { <<
47 phy-handle = <&aquantia_phy2>; <<
48 phy-connection-type = "usxgmii"; <<
49 managed = "in-band-status"; <<
50 }; <<
51 <<
52 &dpmac5 { <<
53 phy-handle = <&inphi_phy>; <<
54 }; <<
55 <<
56 &dpmac6 { <<
57 phy-handle = <&inphi_phy>; <<
58 }; <<
59 <<
60 &dpmac17 { <<
61 phy-handle = <&rgmii_phy1>; <<
62 phy-connection-type = "rgmii-id"; <<
63 }; <<
64 <<
65 &dpmac18 { <<
66 phy-handle = <&rgmii_phy2>; <<
67 phy-connection-type = "rgmii-id"; <<
68 }; <<
69 <<
70 &emdio1 { <<
71 status = "okay"; <<
72 <<
73 rgmii_phy1: ethernet-phy@1 { <<
74 /* AR8035 PHY */ <<
75 compatible = "ethernet-phy-id0 <<
76 interrupts-extended = <&extirq <<
77 reg = <0x1>; <<
78 eee-broken-1000t; <<
79 }; <<
80 <<
81 rgmii_phy2: ethernet-phy@2 { <<
82 /* AR8035 PHY */ <<
83 compatible = "ethernet-phy-id0 <<
84 interrupts-extended = <&extirq <<
85 reg = <0x2>; <<
86 eee-broken-1000t; <<
87 }; <<
88 <<
89 aquantia_phy1: ethernet-phy@4 { <<
90 /* AQR107 PHY */ <<
91 compatible = "ethernet-phy-iee <<
92 interrupts-extended = <&extirq <<
93 reg = <0x4>; <<
94 }; <<
95 <<
96 aquantia_phy2: ethernet-phy@5 { <<
97 /* AQR107 PHY */ <<
98 compatible = "ethernet-phy-iee <<
99 interrupts-extended = <&extirq <<
100 reg = <0x5>; <<
101 }; <<
102 }; <<
103 <<
104 &can0 { <<
105 status = "okay"; <<
106 <<
107 can-transceiver { <<
108 max-bitrate = <5000000>; <<
109 }; <<
110 }; <<
111 <<
112 &can1 { <<
113 status = "okay"; <<
114 <<
115 can-transceiver { <<
116 max-bitrate = <5000000>; <<
117 }; <<
118 }; <<
119 <<
120 &emdio2 { <<
121 status = "okay"; <<
122 <<
123 inphi_phy: ethernet-phy@0 { <<
124 compatible = "ethernet-phy-id0 <<
125 reg = <0x0>; <<
126 }; <<
127 }; <<
128 <<
129 &esdhc0 { 38 &esdhc0 {
130 sd-uhs-sdr104; 39 sd-uhs-sdr104;
131 sd-uhs-sdr50; 40 sd-uhs-sdr50;
132 sd-uhs-sdr25; 41 sd-uhs-sdr25;
133 sd-uhs-sdr12; 42 sd-uhs-sdr12;
134 status = "okay"; 43 status = "okay";
135 }; 44 };
136 45
137 &esdhc1 { 46 &esdhc1 {
138 mmc-hs200-1_8v; 47 mmc-hs200-1_8v;
139 mmc-hs400-1_8v; 48 mmc-hs400-1_8v;
140 bus-width = <8>; 49 bus-width = <8>;
141 status = "okay"; 50 status = "okay";
142 }; 51 };
143 52
144 &fspi { 53 &fspi {
145 status = "okay"; 54 status = "okay";
146 55
147 mt35xu512aba0: flash@0 { 56 mt35xu512aba0: flash@0 {
148 #address-cells = <1>; 57 #address-cells = <1>;
149 #size-cells = <1>; 58 #size-cells = <1>;
150 compatible = "jedec,spi-nor"; !! 59 compatible = "spansion,m25p80";
151 m25p,fast-read; 60 m25p,fast-read;
152 spi-max-frequency = <50000000> 61 spi-max-frequency = <50000000>;
153 reg = <0>; 62 reg = <0>;
154 spi-rx-bus-width = <8>; 63 spi-rx-bus-width = <8>;
155 spi-tx-bus-width = <8>; 64 spi-tx-bus-width = <8>;
156 }; 65 };
157 66
158 mt35xu512aba1: flash@1 { 67 mt35xu512aba1: flash@1 {
159 #address-cells = <1>; 68 #address-cells = <1>;
160 #size-cells = <1>; 69 #size-cells = <1>;
161 compatible = "jedec,spi-nor"; !! 70 compatible = "spansion,m25p80";
162 m25p,fast-read; 71 m25p,fast-read;
163 spi-max-frequency = <50000000> 72 spi-max-frequency = <50000000>;
164 reg = <1>; 73 reg = <1>;
165 spi-rx-bus-width = <8>; 74 spi-rx-bus-width = <8>;
166 spi-tx-bus-width = <8>; 75 spi-tx-bus-width = <8>;
167 }; 76 };
168 }; 77 };
169 78
170 &i2c0 { 79 &i2c0 {
171 status = "okay"; 80 status = "okay";
172 81
173 i2c-mux@77 { 82 i2c-mux@77 {
174 compatible = "nxp,pca9547"; 83 compatible = "nxp,pca9547";
175 reg = <0x77>; 84 reg = <0x77>;
176 #address-cells = <1>; 85 #address-cells = <1>;
177 #size-cells = <0>; 86 #size-cells = <0>;
178 87
179 i2c@2 { 88 i2c@2 {
180 #address-cells = <1>; 89 #address-cells = <1>;
181 #size-cells = <0>; 90 #size-cells = <0>;
182 reg = <0x2>; 91 reg = <0x2>;
183 92
184 power-monitor@40 { 93 power-monitor@40 {
185 compatible = " 94 compatible = "ti,ina220";
186 reg = <0x40>; 95 reg = <0x40>;
187 shunt-resistor !! 96 shunt-resistor = <1000>;
188 }; 97 };
189 }; 98 };
190 99
191 i2c@3 { 100 i2c@3 {
192 #address-cells = <1>; 101 #address-cells = <1>;
193 #size-cells = <0>; 102 #size-cells = <0>;
194 reg = <0x3>; 103 reg = <0x3>;
195 104
196 temperature-sensor@4c 105 temperature-sensor@4c {
197 compatible = " 106 compatible = "nxp,sa56004";
198 reg = <0x4c>; 107 reg = <0x4c>;
199 vcc-supply = < 108 vcc-supply = <&sb_3v3>;
200 }; 109 };
201 110
202 temperature-sensor@4d 111 temperature-sensor@4d {
203 compatible = " 112 compatible = "nxp,sa56004";
204 reg = <0x4d>; 113 reg = <0x4d>;
205 vcc-supply = < 114 vcc-supply = <&sb_3v3>;
206 }; 115 };
207 }; 116 };
208 }; 117 };
209 }; 118 };
210 119
211 &i2c4 { 120 &i2c4 {
212 status = "okay"; 121 status = "okay";
213 122
214 rtc@51 { 123 rtc@51 {
215 compatible = "nxp,pcf2129"; 124 compatible = "nxp,pcf2129";
216 reg = <0x51>; 125 reg = <0x51>;
217 /* IRQ_RTC_B -> IRQ08, active !! 126 // IRQ10_B
218 interrupts-extended = <&extirq !! 127 interrupts = <0 150 0x4>;
219 }; 128 };
220 }; <<
221 <<
222 &optee { <<
223 status = "okay"; <<
224 }; <<
225 <<
226 &pcs_mdio3 { <<
227 status = "okay"; <<
228 }; <<
229 <<
230 &pcs_mdio4 { <<
231 status = "okay"; <<
232 }; 129 };
233 130
234 &sata0 { 131 &sata0 {
235 status = "okay"; 132 status = "okay";
236 }; 133 };
237 134
238 &sata1 { 135 &sata1 {
239 status = "okay"; 136 status = "okay";
240 }; 137 };
241 138
242 &sata2 { 139 &sata2 {
243 status = "okay"; 140 status = "okay";
244 }; 141 };
245 142
246 &sata3 { 143 &sata3 {
247 status = "okay"; 144 status = "okay";
248 }; 145 };
249 146
250 &uart0 { 147 &uart0 {
251 status = "okay"; 148 status = "okay";
252 }; 149 };
253 150
254 &uart1 { 151 &uart1 {
255 status = "okay"; 152 status = "okay";
256 }; 153 };
257 154
258 &usb0 { 155 &usb0 {
259 status = "okay"; 156 status = "okay";
260 }; 157 };
261 158
262 &usb1 { 159 &usb1 {
263 status = "okay"; 160 status = "okay";
264 }; 161 };
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