1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree file for LX2160ARDB 3 // Device Tree file for LX2160ARDB
4 // 4 //
5 // Copyright 2018-2020 NXP 5 // Copyright 2018-2020 NXP
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "fsl-lx2160a.dtsi" 9 #include "fsl-lx2160a.dtsi"
10 10
11 / { 11 / {
12 model = "NXP Layerscape LX2160ARDB"; 12 model = "NXP Layerscape LX2160ARDB";
13 compatible = "fsl,lx2160a-rdb", "fsl,l 13 compatible = "fsl,lx2160a-rdb", "fsl,lx2160a";
14 14
15 aliases { 15 aliases {
16 crypto = &crypto; 16 crypto = &crypto;
17 mmc0 = &esdhc0; 17 mmc0 = &esdhc0;
18 mmc1 = &esdhc1; 18 mmc1 = &esdhc1;
19 serial0 = &uart0; 19 serial0 = &uart0;
20 }; 20 };
21 21
22 chosen { 22 chosen {
23 stdout-path = "serial0:115200n 23 stdout-path = "serial0:115200n8";
24 }; 24 };
25 25
26 sb_3v3: regulator-sb3v3 { 26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed" 27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3V 28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <330 29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <330 30 regulator-max-microvolt = <3300000>;
31 regulator-boot-on; 31 regulator-boot-on;
32 regulator-always-on; 32 regulator-always-on;
33 }; 33 };
34 }; 34 };
35 35
36 &crypto { 36 &crypto {
37 status = "okay"; 37 status = "okay";
38 }; 38 };
39 39
40 &dpmac3 { 40 &dpmac3 {
41 phy-handle = <&aquantia_phy1>; 41 phy-handle = <&aquantia_phy1>;
42 phy-connection-type = "usxgmii"; 42 phy-connection-type = "usxgmii";
43 managed = "in-band-status"; 43 managed = "in-band-status";
44 }; 44 };
45 45
46 &dpmac4 { 46 &dpmac4 {
47 phy-handle = <&aquantia_phy2>; 47 phy-handle = <&aquantia_phy2>;
48 phy-connection-type = "usxgmii"; 48 phy-connection-type = "usxgmii";
49 managed = "in-band-status"; 49 managed = "in-band-status";
50 }; 50 };
51 51
52 &dpmac5 { 52 &dpmac5 {
53 phy-handle = <&inphi_phy>; 53 phy-handle = <&inphi_phy>;
54 }; 54 };
55 55
56 &dpmac6 { 56 &dpmac6 {
57 phy-handle = <&inphi_phy>; 57 phy-handle = <&inphi_phy>;
58 }; 58 };
59 59
60 &dpmac17 { 60 &dpmac17 {
61 phy-handle = <&rgmii_phy1>; 61 phy-handle = <&rgmii_phy1>;
62 phy-connection-type = "rgmii-id"; 62 phy-connection-type = "rgmii-id";
63 }; 63 };
64 64
65 &dpmac18 { 65 &dpmac18 {
66 phy-handle = <&rgmii_phy2>; 66 phy-handle = <&rgmii_phy2>;
67 phy-connection-type = "rgmii-id"; 67 phy-connection-type = "rgmii-id";
68 }; 68 };
69 69
70 &emdio1 { 70 &emdio1 {
71 status = "okay"; 71 status = "okay";
72 72
73 rgmii_phy1: ethernet-phy@1 { 73 rgmii_phy1: ethernet-phy@1 {
74 /* AR8035 PHY */ 74 /* AR8035 PHY */
75 compatible = "ethernet-phy-id0 75 compatible = "ethernet-phy-id004d.d072";
76 interrupts-extended = <&extirq 76 interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>;
77 reg = <0x1>; 77 reg = <0x1>;
78 eee-broken-1000t; 78 eee-broken-1000t;
79 }; 79 };
80 80
81 rgmii_phy2: ethernet-phy@2 { 81 rgmii_phy2: ethernet-phy@2 {
82 /* AR8035 PHY */ 82 /* AR8035 PHY */
83 compatible = "ethernet-phy-id0 83 compatible = "ethernet-phy-id004d.d072";
84 interrupts-extended = <&extirq 84 interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
85 reg = <0x2>; 85 reg = <0x2>;
86 eee-broken-1000t; 86 eee-broken-1000t;
87 }; 87 };
88 88
89 aquantia_phy1: ethernet-phy@4 { 89 aquantia_phy1: ethernet-phy@4 {
90 /* AQR107 PHY */ 90 /* AQR107 PHY */
91 compatible = "ethernet-phy-iee 91 compatible = "ethernet-phy-ieee802.3-c45";
92 interrupts-extended = <&extirq 92 interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>;
93 reg = <0x4>; 93 reg = <0x4>;
94 }; 94 };
95 95
96 aquantia_phy2: ethernet-phy@5 { 96 aquantia_phy2: ethernet-phy@5 {
97 /* AQR107 PHY */ 97 /* AQR107 PHY */
98 compatible = "ethernet-phy-iee 98 compatible = "ethernet-phy-ieee802.3-c45";
99 interrupts-extended = <&extirq 99 interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>;
100 reg = <0x5>; 100 reg = <0x5>;
101 }; 101 };
102 }; 102 };
103 103
104 &can0 { 104 &can0 {
105 status = "okay"; 105 status = "okay";
106 106
107 can-transceiver { 107 can-transceiver {
108 max-bitrate = <5000000>; 108 max-bitrate = <5000000>;
109 }; 109 };
110 }; 110 };
111 111
112 &can1 { 112 &can1 {
113 status = "okay"; 113 status = "okay";
114 114
115 can-transceiver { 115 can-transceiver {
116 max-bitrate = <5000000>; 116 max-bitrate = <5000000>;
117 }; 117 };
118 }; 118 };
119 119
120 &emdio2 { 120 &emdio2 {
121 status = "okay"; 121 status = "okay";
122 122
123 inphi_phy: ethernet-phy@0 { 123 inphi_phy: ethernet-phy@0 {
124 compatible = "ethernet-phy-id0 124 compatible = "ethernet-phy-id0210.7440";
125 reg = <0x0>; 125 reg = <0x0>;
126 }; 126 };
127 }; 127 };
128 128
129 &esdhc0 { 129 &esdhc0 {
130 sd-uhs-sdr104; 130 sd-uhs-sdr104;
131 sd-uhs-sdr50; 131 sd-uhs-sdr50;
132 sd-uhs-sdr25; 132 sd-uhs-sdr25;
133 sd-uhs-sdr12; 133 sd-uhs-sdr12;
134 status = "okay"; 134 status = "okay";
135 }; 135 };
136 136
137 &esdhc1 { 137 &esdhc1 {
138 mmc-hs200-1_8v; 138 mmc-hs200-1_8v;
139 mmc-hs400-1_8v; 139 mmc-hs400-1_8v;
140 bus-width = <8>; 140 bus-width = <8>;
141 status = "okay"; 141 status = "okay";
142 }; 142 };
143 143
144 &fspi { 144 &fspi {
145 status = "okay"; 145 status = "okay";
146 146
147 mt35xu512aba0: flash@0 { 147 mt35xu512aba0: flash@0 {
148 #address-cells = <1>; 148 #address-cells = <1>;
149 #size-cells = <1>; 149 #size-cells = <1>;
150 compatible = "jedec,spi-nor"; 150 compatible = "jedec,spi-nor";
151 m25p,fast-read; 151 m25p,fast-read;
152 spi-max-frequency = <50000000> 152 spi-max-frequency = <50000000>;
153 reg = <0>; 153 reg = <0>;
154 spi-rx-bus-width = <8>; 154 spi-rx-bus-width = <8>;
155 spi-tx-bus-width = <8>; 155 spi-tx-bus-width = <8>;
156 }; 156 };
157 157
158 mt35xu512aba1: flash@1 { 158 mt35xu512aba1: flash@1 {
159 #address-cells = <1>; 159 #address-cells = <1>;
160 #size-cells = <1>; 160 #size-cells = <1>;
161 compatible = "jedec,spi-nor"; 161 compatible = "jedec,spi-nor";
162 m25p,fast-read; 162 m25p,fast-read;
163 spi-max-frequency = <50000000> 163 spi-max-frequency = <50000000>;
164 reg = <1>; 164 reg = <1>;
165 spi-rx-bus-width = <8>; 165 spi-rx-bus-width = <8>;
166 spi-tx-bus-width = <8>; 166 spi-tx-bus-width = <8>;
167 }; 167 };
168 }; 168 };
169 169
170 &i2c0 { 170 &i2c0 {
171 status = "okay"; 171 status = "okay";
172 172
173 i2c-mux@77 { 173 i2c-mux@77 {
174 compatible = "nxp,pca9547"; 174 compatible = "nxp,pca9547";
175 reg = <0x77>; 175 reg = <0x77>;
176 #address-cells = <1>; 176 #address-cells = <1>;
177 #size-cells = <0>; 177 #size-cells = <0>;
178 178
179 i2c@2 { 179 i2c@2 {
180 #address-cells = <1>; 180 #address-cells = <1>;
181 #size-cells = <0>; 181 #size-cells = <0>;
182 reg = <0x2>; 182 reg = <0x2>;
183 183
184 power-monitor@40 { 184 power-monitor@40 {
185 compatible = " 185 compatible = "ti,ina220";
186 reg = <0x40>; 186 reg = <0x40>;
187 shunt-resistor 187 shunt-resistor = <500>;
188 }; 188 };
189 }; 189 };
190 190
191 i2c@3 { 191 i2c@3 {
192 #address-cells = <1>; 192 #address-cells = <1>;
193 #size-cells = <0>; 193 #size-cells = <0>;
194 reg = <0x3>; 194 reg = <0x3>;
195 195
196 temperature-sensor@4c 196 temperature-sensor@4c {
197 compatible = " 197 compatible = "nxp,sa56004";
198 reg = <0x4c>; 198 reg = <0x4c>;
199 vcc-supply = < 199 vcc-supply = <&sb_3v3>;
200 }; 200 };
201 201
202 temperature-sensor@4d 202 temperature-sensor@4d {
203 compatible = " 203 compatible = "nxp,sa56004";
204 reg = <0x4d>; 204 reg = <0x4d>;
205 vcc-supply = < 205 vcc-supply = <&sb_3v3>;
206 }; 206 };
207 }; 207 };
208 }; 208 };
209 }; 209 };
210 210
211 &i2c4 { 211 &i2c4 {
212 status = "okay"; 212 status = "okay";
213 213
214 rtc@51 { 214 rtc@51 {
215 compatible = "nxp,pcf2129"; 215 compatible = "nxp,pcf2129";
216 reg = <0x51>; 216 reg = <0x51>;
217 /* IRQ_RTC_B -> IRQ08, active 217 /* IRQ_RTC_B -> IRQ08, active low */
218 interrupts-extended = <&extirq 218 interrupts-extended = <&extirq 8 IRQ_TYPE_LEVEL_LOW>;
219 }; 219 };
220 }; 220 };
221 221
222 &optee { 222 &optee {
223 status = "okay"; 223 status = "okay";
224 }; 224 };
225 225
226 &pcs_mdio3 { 226 &pcs_mdio3 {
227 status = "okay"; 227 status = "okay";
228 }; 228 };
229 229
230 &pcs_mdio4 { 230 &pcs_mdio4 {
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 &sata0 { 234 &sata0 {
235 status = "okay"; 235 status = "okay";
236 }; 236 };
237 237
238 &sata1 { 238 &sata1 {
239 status = "okay"; 239 status = "okay";
240 }; 240 };
241 241
242 &sata2 { 242 &sata2 {
243 status = "okay"; 243 status = "okay";
244 }; 244 };
245 245
246 &sata3 { 246 &sata3 {
247 status = "okay"; 247 status = "okay";
248 }; 248 };
249 249
250 &uart0 { 250 &uart0 {
251 status = "okay"; 251 status = "okay";
252 }; 252 };
253 253
254 &uart1 { 254 &uart1 {
255 status = "okay"; 255 status = "okay";
256 }; 256 };
257 257
258 &usb0 { 258 &usb0 {
259 status = "okay"; 259 status = "okay";
260 }; 260 };
261 261
262 &usb1 { 262 &usb1 {
263 status = "okay"; 263 status = "okay";
264 }; 264 };
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