1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 //
3 // Device Tree Include file for Layerscape-LX2
4 //
5 // Copyright 2018-2020 NXP
6
7 #include <dt-bindings/clock/fsl,qoriq-clockgen
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm
10 #include <dt-bindings/thermal/thermal.h>
11
12 /memreserve/ 0x80000000 0x00010000;
13
14 / {
15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 rtc1 = &ftm_alarm0;
22 };
23
24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
27
28 // 8 clusters having 2 Cortex-
29 cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cort
32 enable-method = "psci"
33 reg = <0x0>;
34 clocks = <&clockgen QO
35 d-cache-size = <0x8000
36 d-cache-line-size = <6
37 d-cache-sets = <128>;
38 i-cache-size = <0xC000
39 i-cache-line-size = <6
40 i-cache-sets = <192>;
41 next-level-cache = <&c
42 cpu-idle-states = <&cp
43 #cooling-cells = <2>;
44 };
45
46 cpu1: cpu@1 {
47 device_type = "cpu";
48 compatible = "arm,cort
49 enable-method = "psci"
50 reg = <0x1>;
51 clocks = <&clockgen QO
52 d-cache-size = <0x8000
53 d-cache-line-size = <6
54 d-cache-sets = <128>;
55 i-cache-size = <0xC000
56 i-cache-line-size = <6
57 i-cache-sets = <192>;
58 next-level-cache = <&c
59 cpu-idle-states = <&cp
60 #cooling-cells = <2>;
61 };
62
63 cpu100: cpu@100 {
64 device_type = "cpu";
65 compatible = "arm,cort
66 enable-method = "psci"
67 reg = <0x100>;
68 clocks = <&clockgen QO
69 d-cache-size = <0x8000
70 d-cache-line-size = <6
71 d-cache-sets = <128>;
72 i-cache-size = <0xC000
73 i-cache-line-size = <6
74 i-cache-sets = <192>;
75 next-level-cache = <&c
76 cpu-idle-states = <&cp
77 #cooling-cells = <2>;
78 };
79
80 cpu101: cpu@101 {
81 device_type = "cpu";
82 compatible = "arm,cort
83 enable-method = "psci"
84 reg = <0x101>;
85 clocks = <&clockgen QO
86 d-cache-size = <0x8000
87 d-cache-line-size = <6
88 d-cache-sets = <128>;
89 i-cache-size = <0xC000
90 i-cache-line-size = <6
91 i-cache-sets = <192>;
92 next-level-cache = <&c
93 cpu-idle-states = <&cp
94 #cooling-cells = <2>;
95 };
96
97 cpu200: cpu@200 {
98 device_type = "cpu";
99 compatible = "arm,cort
100 enable-method = "psci"
101 reg = <0x200>;
102 clocks = <&clockgen QO
103 d-cache-size = <0x8000
104 d-cache-line-size = <6
105 d-cache-sets = <128>;
106 i-cache-size = <0xC000
107 i-cache-line-size = <6
108 i-cache-sets = <192>;
109 next-level-cache = <&c
110 cpu-idle-states = <&cp
111 #cooling-cells = <2>;
112 };
113
114 cpu201: cpu@201 {
115 device_type = "cpu";
116 compatible = "arm,cort
117 enable-method = "psci"
118 reg = <0x201>;
119 clocks = <&clockgen QO
120 d-cache-size = <0x8000
121 d-cache-line-size = <6
122 d-cache-sets = <128>;
123 i-cache-size = <0xC000
124 i-cache-line-size = <6
125 i-cache-sets = <192>;
126 next-level-cache = <&c
127 cpu-idle-states = <&cp
128 #cooling-cells = <2>;
129 };
130
131 cpu300: cpu@300 {
132 device_type = "cpu";
133 compatible = "arm,cort
134 enable-method = "psci"
135 reg = <0x300>;
136 clocks = <&clockgen QO
137 d-cache-size = <0x8000
138 d-cache-line-size = <6
139 d-cache-sets = <128>;
140 i-cache-size = <0xC000
141 i-cache-line-size = <6
142 i-cache-sets = <192>;
143 next-level-cache = <&c
144 cpu-idle-states = <&cp
145 #cooling-cells = <2>;
146 };
147
148 cpu301: cpu@301 {
149 device_type = "cpu";
150 compatible = "arm,cort
151 enable-method = "psci"
152 reg = <0x301>;
153 clocks = <&clockgen QO
154 d-cache-size = <0x8000
155 d-cache-line-size = <6
156 d-cache-sets = <128>;
157 i-cache-size = <0xC000
158 i-cache-line-size = <6
159 i-cache-sets = <192>;
160 next-level-cache = <&c
161 cpu-idle-states = <&cp
162 #cooling-cells = <2>;
163 };
164
165 cpu400: cpu@400 {
166 device_type = "cpu";
167 compatible = "arm,cort
168 enable-method = "psci"
169 reg = <0x400>;
170 clocks = <&clockgen QO
171 d-cache-size = <0x8000
172 d-cache-line-size = <6
173 d-cache-sets = <128>;
174 i-cache-size = <0xC000
175 i-cache-line-size = <6
176 i-cache-sets = <192>;
177 next-level-cache = <&c
178 cpu-idle-states = <&cp
179 #cooling-cells = <2>;
180 };
181
182 cpu401: cpu@401 {
183 device_type = "cpu";
184 compatible = "arm,cort
185 enable-method = "psci"
186 reg = <0x401>;
187 clocks = <&clockgen QO
188 d-cache-size = <0x8000
189 d-cache-line-size = <6
190 d-cache-sets = <128>;
191 i-cache-size = <0xC000
192 i-cache-line-size = <6
193 i-cache-sets = <192>;
194 next-level-cache = <&c
195 cpu-idle-states = <&cp
196 #cooling-cells = <2>;
197 };
198
199 cpu500: cpu@500 {
200 device_type = "cpu";
201 compatible = "arm,cort
202 enable-method = "psci"
203 reg = <0x500>;
204 clocks = <&clockgen QO
205 d-cache-size = <0x8000
206 d-cache-line-size = <6
207 d-cache-sets = <128>;
208 i-cache-size = <0xC000
209 i-cache-line-size = <6
210 i-cache-sets = <192>;
211 next-level-cache = <&c
212 cpu-idle-states = <&cp
213 #cooling-cells = <2>;
214 };
215
216 cpu501: cpu@501 {
217 device_type = "cpu";
218 compatible = "arm,cort
219 enable-method = "psci"
220 reg = <0x501>;
221 clocks = <&clockgen QO
222 d-cache-size = <0x8000
223 d-cache-line-size = <6
224 d-cache-sets = <128>;
225 i-cache-size = <0xC000
226 i-cache-line-size = <6
227 i-cache-sets = <192>;
228 next-level-cache = <&c
229 cpu-idle-states = <&cp
230 #cooling-cells = <2>;
231 };
232
233 cpu600: cpu@600 {
234 device_type = "cpu";
235 compatible = "arm,cort
236 enable-method = "psci"
237 reg = <0x600>;
238 clocks = <&clockgen QO
239 d-cache-size = <0x8000
240 d-cache-line-size = <6
241 d-cache-sets = <128>;
242 i-cache-size = <0xC000
243 i-cache-line-size = <6
244 i-cache-sets = <192>;
245 next-level-cache = <&c
246 cpu-idle-states = <&cp
247 #cooling-cells = <2>;
248 };
249
250 cpu601: cpu@601 {
251 device_type = "cpu";
252 compatible = "arm,cort
253 enable-method = "psci"
254 reg = <0x601>;
255 clocks = <&clockgen QO
256 d-cache-size = <0x8000
257 d-cache-line-size = <6
258 d-cache-sets = <128>;
259 i-cache-size = <0xC000
260 i-cache-line-size = <6
261 i-cache-sets = <192>;
262 next-level-cache = <&c
263 cpu-idle-states = <&cp
264 #cooling-cells = <2>;
265 };
266
267 cpu700: cpu@700 {
268 device_type = "cpu";
269 compatible = "arm,cort
270 enable-method = "psci"
271 reg = <0x700>;
272 clocks = <&clockgen QO
273 d-cache-size = <0x8000
274 d-cache-line-size = <6
275 d-cache-sets = <128>;
276 i-cache-size = <0xC000
277 i-cache-line-size = <6
278 i-cache-sets = <192>;
279 next-level-cache = <&c
280 cpu-idle-states = <&cp
281 #cooling-cells = <2>;
282 };
283
284 cpu701: cpu@701 {
285 device_type = "cpu";
286 compatible = "arm,cort
287 enable-method = "psci"
288 reg = <0x701>;
289 clocks = <&clockgen QO
290 d-cache-size = <0x8000
291 d-cache-line-size = <6
292 d-cache-sets = <128>;
293 i-cache-size = <0xC000
294 i-cache-line-size = <6
295 i-cache-sets = <192>;
296 next-level-cache = <&c
297 cpu-idle-states = <&cp
298 #cooling-cells = <2>;
299 };
300
301 cluster0_l2: l2-cache0 {
302 compatible = "cache";
303 cache-unified;
304 cache-size = <0x100000
305 cache-line-size = <64>
306 cache-sets = <1024>;
307 cache-level = <2>;
308 };
309
310 cluster1_l2: l2-cache1 {
311 compatible = "cache";
312 cache-unified;
313 cache-size = <0x100000
314 cache-line-size = <64>
315 cache-sets = <1024>;
316 cache-level = <2>;
317 };
318
319 cluster2_l2: l2-cache2 {
320 compatible = "cache";
321 cache-unified;
322 cache-size = <0x100000
323 cache-line-size = <64>
324 cache-sets = <1024>;
325 cache-level = <2>;
326 };
327
328 cluster3_l2: l2-cache3 {
329 compatible = "cache";
330 cache-unified;
331 cache-size = <0x100000
332 cache-line-size = <64>
333 cache-sets = <1024>;
334 cache-level = <2>;
335 };
336
337 cluster4_l2: l2-cache4 {
338 compatible = "cache";
339 cache-unified;
340 cache-size = <0x100000
341 cache-line-size = <64>
342 cache-sets = <1024>;
343 cache-level = <2>;
344 };
345
346 cluster5_l2: l2-cache5 {
347 compatible = "cache";
348 cache-unified;
349 cache-size = <0x100000
350 cache-line-size = <64>
351 cache-sets = <1024>;
352 cache-level = <2>;
353 };
354
355 cluster6_l2: l2-cache6 {
356 compatible = "cache";
357 cache-unified;
358 cache-size = <0x100000
359 cache-line-size = <64>
360 cache-sets = <1024>;
361 cache-level = <2>;
362 };
363
364 cluster7_l2: l2-cache7 {
365 compatible = "cache";
366 cache-unified;
367 cache-size = <0x100000
368 cache-line-size = <64>
369 cache-sets = <1024>;
370 cache-level = <2>;
371 };
372
373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle
375 idle-state-name = "PW1
376 arm,psci-suspend-param
377 entry-latency-us = <20
378 exit-latency-us = <200
379 min-residency-us = <60
380 };
381 };
382
383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x1000
386 <0x0 0x06200000 0 0x20
387
388 <0x0 0x0c0c0000 0 0x20
389 <0x0 0x0c0d0000 0 0x10
390 <0x0 0x0c0e0000 0 0x20
391 #interrupt-cells = <3>;
392 #address-cells = <2>;
393 #size-cells = <2>;
394 ranges;
395 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TY
397
398 its: msi-controller@6020000 {
399 compatible = "arm,gic-
400 msi-controller;
401 #msi-cells = <1>;
402 reg = <0x0 0x6020000 0
403 };
404 };
405
406 timer {
407 compatible = "arm,armv8-timer"
408 interrupts = <GIC_PPI 13 IRQ_T
409 <GIC_PPI 14 IRQ_T
410 <GIC_PPI 11 IRQ_T
411 <GIC_PPI 10 IRQ_T
412 };
413
414 pmu {
415 compatible = "arm,cortex-a72-p
416 interrupts = <GIC_PPI 7 IRQ_TY
417 };
418
419 psci {
420 compatible = "arm,psci-0.2";
421 method = "smc";
422 };
423
424 memory@80000000 {
425 // DRAM space - 1, size : 2 GB
426 device_type = "memory";
427 reg = <0x00000000 0x80000000 0
428 };
429
430 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory
432 reg = <0x0 0x1080000 0x0 0x100
433 interrupts = <GIC_SPI 17 IRQ_T
434 little-endian;
435 };
436
437 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory
439 reg = <0x0 0x1090000 0x0 0x100
440 interrupts = <GIC_SPI 18 IRQ_T
441 little-endian;
442 };
443
444 // One clock unit-sysclk node which bo
445 sysclk: sysclk {
446 compatible = "fixed-clock";
447 #clock-cells = <0>;
448 clock-frequency = <100000000>;
449 clock-output-names = "sysclk";
450 };
451
452 thermal-zones {
453 cluster6-7-thermal {
454 polling-delay-passive
455 polling-delay = <5000>
456 thermal-sensors = <&tm
457
458 trips {
459 cluster6_7_ale
460 temper
461 hyster
462 type =
463 };
464
465 cluster6_7_cri
466 temper
467 hyster
468 type =
469 };
470 };
471
472 cooling-maps {
473 map0 {
474 trip =
475 coolin
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492 };
493 };
494 };
495
496 ddr-ctrl5-thermal {
497 polling-delay-passive
498 polling-delay = <5000>
499 thermal-sensors = <&tm
500
501 trips {
502 ddr-cluster5-a
503 temper
504 hyster
505 type =
506 };
507
508 ddr-cluster5-c
509 temper
510 hyster
511 type =
512 };
513 };
514 };
515
516 wriop-thermal {
517 polling-delay-passive
518 polling-delay = <5000>
519 thermal-sensors = <&tm
520
521 trips {
522 wriop-alert {
523 temper
524 hyster
525 type =
526 };
527
528 wriop-crit {
529 temper
530 hyster
531 type =
532 };
533 };
534 };
535
536 dce-thermal {
537 polling-delay-passive
538 polling-delay = <5000>
539 thermal-sensors = <&tm
540
541 trips {
542 dce-qbman-aler
543 temper
544 hyster
545 type =
546 };
547
548 dce-qbman-crit
549 temper
550 hyster
551 type =
552 };
553 };
554 };
555
556 ccn-thermal {
557 polling-delay-passive
558 polling-delay = <5000>
559 thermal-sensors = <&tm
560
561 trips {
562 ccn-dpaa-alert
563 temper
564 hyster
565 type =
566 };
567
568 ccn-dpaa-crit
569 temper
570 hyster
571 type =
572 };
573 };
574 };
575
576 cluster4-thermal {
577 polling-delay-passive
578 polling-delay = <5000>
579 thermal-sensors = <&tm
580
581 trips {
582 clust4-hsio3-a
583 temper
584 hyster
585 type =
586 };
587
588 clust4-hsio3-c
589 temper
590 hyster
591 type =
592 };
593 };
594 };
595
596 cluster2-3-thermal {
597 polling-delay-passive
598 polling-delay = <5000>
599 thermal-sensors = <&tm
600
601 trips {
602 cluster2-3-ale
603 temper
604 hyster
605 type =
606 };
607
608 cluster2-3-cri
609 temper
610 hyster
611 type =
612 };
613 };
614 };
615 };
616
617 soc {
618 compatible = "simple-bus";
619 #address-cells = <2>;
620 #size-cells = <2>;
621 ranges;
622 dma-ranges = <0x0 0x0 0x0 0x0
623
624 serdes_1: phy@1ea0000 {
625 compatible = "fsl,lynx
626 reg = <0x0 0x1ea0000 0
627 #phy-cells = <1>;
628 };
629
630 serdes_2: phy@1eb0000 {
631 compatible = "fsl,lynx
632 reg = <0x0 0x1eb0000 0
633 #phy-cells = <1>;
634 status = "disabled";
635 };
636
637 crypto: crypto@8000000 {
638 compatible = "fsl,sec-
639 fsl,sec-era = <10>;
640 #address-cells = <1>;
641 #size-cells = <1>;
642 ranges = <0x0 0x00 0x8
643 reg = <0x00 0x8000000
644 interrupts = <GIC_SPI
645 dma-coherent;
646 status = "disabled";
647
648 sec_jr0: jr@10000 {
649 compatible = "
650 "
651 reg = <0x10000
652 interrupts = <
653 };
654
655 sec_jr1: jr@20000 {
656 compatible = "
657 "
658 reg = <0x20000
659 interrupts = <
660 };
661
662 sec_jr2: jr@30000 {
663 compatible = "
664 "
665 reg = <0x30000
666 interrupts = <
667 };
668
669 sec_jr3: jr@40000 {
670 compatible = "
671 "
672 reg = <0x40000
673 interrupts = <
674 };
675 };
676
677 clockgen: clock-controller@130
678 compatible = "fsl,lx21
679 reg = <0 0x1300000 0 0
680 #clock-cells = <2>;
681 clocks = <&sysclk>;
682 };
683
684 dcfg: syscon@1e00000 {
685 compatible = "fsl,lx21
686 reg = <0x0 0x1e00000 0
687 little-endian;
688 };
689
690 sfp: efuse@1e80000 {
691 compatible = "fsl,ls10
692 reg = <0x0 0x1e80000 0
693 clocks = <&clockgen QO
694 QO
695 clock-names = "sfp";
696 };
697
698 isc: syscon@1f70000 {
699 compatible = "fsl,lx21
700 reg = <0x0 0x1f70000 0
701 little-endian;
702 #address-cells = <1>;
703 #size-cells = <1>;
704 ranges = <0x0 0x0 0x1f
705
706 extirq: interrupt-cont
707 compatible = "
708 #interrupt-cel
709 #address-cells
710 interrupt-cont
711 reg = <0x14 4>
712 interrupt-map
713 <0 0 &
714 <1 0 &
715 <2 0 &
716 <3 0 &
717 <4 0 &
718 <5 0 &
719 <6 0 &
720 <7 0 &
721 <8 0 &
722 <9 0 &
723 <10 0
724 <11 0
725 interrupt-map-
726 };
727 };
728
729 tmu: tmu@1f80000 {
730 compatible = "fsl,qori
731 reg = <0x0 0x1f80000 0
732 interrupts = <GIC_SPI
733 fsl,tmu-range = <0x800
734 fsl,tmu-calibration =
735 /* Calibration
736 <0x00000000 0x
737 /* Calibration
738 <0x00000001 0x
739 little-endian;
740 #thermal-sensor-cells
741 };
742
743 i2c0: i2c@2000000 {
744 compatible = "fsl,vf61
745 #address-cells = <1>;
746 #size-cells = <0>;
747 reg = <0x0 0x2000000 0
748 interrupts = <GIC_SPI
749 clock-names = "ipg";
750 clocks = <&clockgen QO
751 QO
752 pinctrl-names = "defau
753 pinctrl-0 = <&i2c0_scl
754 pinctrl-1 = <&i2c0_scl
755 scl-gpios = <&gpio0 3
756 status = "disabled";
757 };
758
759 i2c1: i2c@2010000 {
760 compatible = "fsl,vf61
761 #address-cells = <1>;
762 #size-cells = <0>;
763 reg = <0x0 0x2010000 0
764 interrupts = <GIC_SPI
765 clock-names = "ipg";
766 clocks = <&clockgen QO
767 QO
768 pinctrl-names = "defau
769 pinctrl-0 = <&i2c1_scl
770 pinctrl-1 = <&i2c1_scl
771 scl-gpios = <&gpio0 31
772 status = "disabled";
773 };
774
775 i2c2: i2c@2020000 {
776 compatible = "fsl,vf61
777 #address-cells = <1>;
778 #size-cells = <0>;
779 reg = <0x0 0x2020000 0
780 interrupts = <GIC_SPI
781 clock-names = "ipg";
782 clocks = <&clockgen QO
783 QO
784 pinctrl-names = "defau
785 pinctrl-0 = <&i2c2_scl
786 pinctrl-1 = <&i2c2_scl
787 scl-gpios = <&gpio0 29
788 status = "disabled";
789 };
790
791 i2c3: i2c@2030000 {
792 compatible = "fsl,vf61
793 #address-cells = <1>;
794 #size-cells = <0>;
795 reg = <0x0 0x2030000 0
796 interrupts = <GIC_SPI
797 clock-names = "ipg";
798 clocks = <&clockgen QO
799 QO
800 pinctrl-names = "defau
801 pinctrl-0 = <&i2c3_scl
802 pinctrl-1 = <&i2c3_scl
803 scl-gpios = <&gpio0 27
804 status = "disabled";
805 };
806
807 i2c4: i2c@2040000 {
808 compatible = "fsl,vf61
809 #address-cells = <1>;
810 #size-cells = <0>;
811 reg = <0x0 0x2040000 0
812 interrupts = <GIC_SPI
813 clock-names = "ipg";
814 clocks = <&clockgen QO
815 QO
816 pinctrl-names = "defau
817 pinctrl-0 = <&i2c4_scl
818 pinctrl-1 = <&i2c4_scl
819 scl-gpios = <&gpio0 25
820 status = "disabled";
821 };
822
823 i2c5: i2c@2050000 {
824 compatible = "fsl,vf61
825 #address-cells = <1>;
826 #size-cells = <0>;
827 reg = <0x0 0x2050000 0
828 interrupts = <GIC_SPI
829 clock-names = "ipg";
830 clocks = <&clockgen QO
831 QO
832 pinctrl-names = "defau
833 pinctrl-0 = <&i2c5_scl
834 pinctrl-1 = <&i2c5_scl
835 scl-gpios = <&gpio0 23
836 status = "disabled";
837 };
838
839 i2c6: i2c@2060000 {
840 compatible = "fsl,vf61
841 #address-cells = <1>;
842 #size-cells = <0>;
843 reg = <0x0 0x2060000 0
844 interrupts = <GIC_SPI
845 clock-names = "ipg";
846 clocks = <&clockgen QO
847 QO
848 pinctrl-names = "defau
849 pinctrl-0 = <&i2c6_scl
850 pinctrl-1 = <&i2c6_scl
851 scl-gpios = <&gpio1 16
852 status = "disabled";
853 };
854
855 i2c7: i2c@2070000 {
856 compatible = "fsl,vf61
857 #address-cells = <1>;
858 #size-cells = <0>;
859 reg = <0x0 0x2070000 0
860 interrupts = <GIC_SPI
861 clock-names = "ipg";
862 clocks = <&clockgen QO
863 QO
864 pinctrl-names = "defau
865 pinctrl-0 = <&i2c7_scl
866 pinctrl-1 = <&i2c7_scl
867 scl-gpios = <&gpio1 18
868 status = "disabled";
869 };
870
871 fspi: spi@20c0000 {
872 compatible = "nxp,lx21
873 #address-cells = <1>;
874 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0
876 <0x0 0x20000000
877 reg-names = "fspi_base
878 interrupts = <GIC_SPI
879 clocks = <&clockgen QO
880 QO
881 <&clockgen QO
882 QO
883 clock-names = "fspi_en
884 status = "disabled";
885 };
886
887 dspi0: spi@2100000 {
888 compatible = "fsl,lx21
889 #address-cells = <1>;
890 #size-cells = <0>;
891 reg = <0x0 0x2100000 0
892 interrupts = <GIC_SPI
893 clocks = <&clockgen QO
894 QO
895 clock-names = "dspi";
896 spi-num-chipselects =
897 bus-num = <0>;
898 status = "disabled";
899 };
900
901 dspi1: spi@2110000 {
902 compatible = "fsl,lx21
903 #address-cells = <1>;
904 #size-cells = <0>;
905 reg = <0x0 0x2110000 0
906 interrupts = <GIC_SPI
907 clocks = <&clockgen QO
908 QO
909 clock-names = "dspi";
910 spi-num-chipselects =
911 bus-num = <1>;
912 status = "disabled";
913 };
914
915 dspi2: spi@2120000 {
916 compatible = "fsl,lx21
917 #address-cells = <1>;
918 #size-cells = <0>;
919 reg = <0x0 0x2120000 0
920 interrupts = <GIC_SPI
921 clocks = <&clockgen QO
922 QO
923 clock-names = "dspi";
924 spi-num-chipselects =
925 bus-num = <2>;
926 status = "disabled";
927 };
928
929 esdhc0: mmc@2140000 {
930 compatible = "fsl,ls20
931 reg = <0x0 0x2140000 0
932 interrupts = <GIC_SPI
933 clocks = <&clockgen QO
934 QO
935 dma-coherent;
936 voltage-ranges = <1800
937 sdhci,auto-cmd12;
938 little-endian;
939 bus-width = <4>;
940 status = "disabled";
941 };
942
943 esdhc1: mmc@2150000 {
944 compatible = "fsl,ls20
945 reg = <0x0 0x2150000 0
946 interrupts = <GIC_SPI
947 clocks = <&clockgen QO
948 QO
949 dma-coherent;
950 voltage-ranges = <1800
951 sdhci,auto-cmd12;
952 broken-cd;
953 little-endian;
954 bus-width = <4>;
955 status = "disabled";
956 };
957
958 can0: can@2180000 {
959 compatible = "fsl,lx21
960 reg = <0x0 0x2180000 0
961 interrupts = <GIC_SPI
962 clocks = <&clockgen QO
963 QO
964 <&clockgen QO
965 clock-names = "ipg", "
966 fsl,clk-source = /bits
967 status = "disabled";
968 };
969
970 can1: can@2190000 {
971 compatible = "fsl,lx21
972 reg = <0x0 0x2190000 0
973 interrupts = <GIC_SPI
974 clocks = <&clockgen QO
975 QO
976 <&clockgen QO
977 clock-names = "ipg", "
978 fsl,clk-source = /bits
979 status = "disabled";
980 };
981
982 uart0: serial@21c0000 {
983 compatible = "arm,pl01
984 clocks = <&clockgen QO
985 QO
986 <&clockgen QO
987 QO
988 clock-names = "uartclk
989 reg = <0x0 0x21c0000 0
990 interrupts = <GIC_SPI
991 status = "disabled";
992 };
993
994 uart1: serial@21d0000 {
995 compatible = "arm,pl01
996 clocks = <&clockgen QO
997 QO
998 <&clockgen QO
999 QO
1000 clock-names = "uartcl
1001 reg = <0x0 0x21d0000
1002 interrupts = <GIC_SPI
1003 status = "disabled";
1004 };
1005
1006 uart2: serial@21e0000 {
1007 compatible = "arm,pl0
1008 clocks = <&clockgen Q
1009 Q
1010 <&clockgen Q
1011 Q
1012 clock-names = "uartcl
1013 reg = <0x0 0x21e0000
1014 interrupts = <GIC_SPI
1015 status = "disabled";
1016 };
1017
1018 uart3: serial@21f0000 {
1019 compatible = "arm,pl0
1020 clocks = <&clockgen Q
1021 Q
1022 <&clockgen Q
1023 Q
1024 clock-names = "uartcl
1025 reg = <0x0 0x21f0000
1026 interrupts = <GIC_SPI
1027 status = "disabled";
1028 };
1029
1030 gpio0: gpio@2300000 {
1031 compatible = "fsl,ls2
1032 reg = <0x0 0x2300000
1033 interrupts = <GIC_SPI
1034 gpio-controller;
1035 little-endian;
1036 #gpio-cells = <2>;
1037 interrupt-controller;
1038 #interrupt-cells = <2
1039 };
1040
1041 gpio1: gpio@2310000 {
1042 compatible = "fsl,ls2
1043 reg = <0x0 0x2310000
1044 interrupts = <GIC_SPI
1045 gpio-controller;
1046 little-endian;
1047 #gpio-cells = <2>;
1048 interrupt-controller;
1049 #interrupt-cells = <2
1050 };
1051
1052 gpio2: gpio@2320000 {
1053 compatible = "fsl,ls2
1054 reg = <0x0 0x2320000
1055 interrupts = <GIC_SPI
1056 gpio-controller;
1057 little-endian;
1058 #gpio-cells = <2>;
1059 interrupt-controller;
1060 #interrupt-cells = <2
1061 };
1062
1063 gpio3: gpio@2330000 {
1064 compatible = "fsl,ls2
1065 reg = <0x0 0x2330000
1066 interrupts = <GIC_SPI
1067 gpio-controller;
1068 little-endian;
1069 #gpio-cells = <2>;
1070 interrupt-controller;
1071 #interrupt-cells = <2
1072 };
1073
1074 watchdog@23a0000 {
1075 compatible = "arm,sbs
1076 reg = <0x0 0x23a0000
1077 <0x0 0x2390000
1078 interrupts = <GIC_SPI
1079 timeout-sec = <30>;
1080 };
1081
1082 rcpm: wakeup-controller@1e340
1083 compatible = "fsl,lx2
1084 reg = <0x0 0x1e34040
1085 #fsl,rcpm-wakeup-cell
1086 little-endian;
1087 };
1088
1089 ftm_alarm0: rtc@2800000 {
1090 compatible = "fsl,lx2
1091 reg = <0x0 0x2800000
1092 fsl,rcpm-wakeup = <&r
1093 interrupts = <GIC_SPI
1094 };
1095
1096 usb0: usb@3100000 {
1097 compatible = "snps,dw
1098 reg = <0x0 0x3100000
1099 interrupts = <GIC_SPI
1100 dr_mode = "host";
1101 snps,quirk-frame-leng
1102 usb3-lpm-capable;
1103 snps,dis_rxdet_inp3_q
1104 snps,incr-burst-type-
1105 status = "disabled";
1106 };
1107
1108 usb1: usb@3110000 {
1109 compatible = "snps,dw
1110 reg = <0x0 0x3110000
1111 interrupts = <GIC_SPI
1112 dr_mode = "host";
1113 snps,quirk-frame-leng
1114 usb3-lpm-capable;
1115 snps,dis_rxdet_inp3_q
1116 snps,incr-burst-type-
1117 status = "disabled";
1118 };
1119
1120 sata0: sata@3200000 {
1121 compatible = "fsl,lx2
1122 reg = <0x0 0x3200000
1123 <0x7 0x100520 0
1124 reg-names = "ahci", "
1125 interrupts = <GIC_SPI
1126 clocks = <&clockgen Q
1127 Q
1128 dma-coherent;
1129 status = "disabled";
1130 };
1131
1132 sata1: sata@3210000 {
1133 compatible = "fsl,lx2
1134 reg = <0x0 0x3210000
1135 <0x7 0x100520 0
1136 reg-names = "ahci", "
1137 interrupts = <GIC_SPI
1138 clocks = <&clockgen Q
1139 Q
1140 dma-coherent;
1141 status = "disabled";
1142 };
1143
1144 sata2: sata@3220000 {
1145 compatible = "fsl,lx2
1146 reg = <0x0 0x3220000
1147 <0x7 0x100520 0
1148 reg-names = "ahci", "
1149 interrupts = <GIC_SPI
1150 clocks = <&clockgen Q
1151 Q
1152 dma-coherent;
1153 status = "disabled";
1154 };
1155
1156 sata3: sata@3230000 {
1157 compatible = "fsl,lx2
1158 reg = <0x0 0x3230000
1159 <0x7 0x100520 0
1160 reg-names = "ahci", "
1161 interrupts = <GIC_SPI
1162 clocks = <&clockgen Q
1163 Q
1164 dma-coherent;
1165 status = "disabled";
1166 };
1167
1168 pcie1: pcie@3400000 {
1169 compatible = "fsl,lx2
1170 reg = <0x00 0x0340000
1171 <0x80 0x0000000
1172 reg-names = "csr_axi_
1173 interrupts = <GIC_SPI
1174 <GIC_SPI
1175 <GIC_SPI
1176 interrupt-names = "ae
1177 #address-cells = <3>;
1178 #size-cells = <2>;
1179 device_type = "pci";
1180 dma-coherent;
1181 apio-wins = <8>;
1182 ppio-wins = <8>;
1183 bus-range = <0x0 0xff
1184 ranges = <0x82000000
1185 msi-parent = <&its 0>
1186 #interrupt-cells = <1
1187 interrupt-map-mask =
1188 interrupt-map = <0000
1189 <0000
1190 <0000
1191 <0000
1192 iommu-map = <0 &smmu
1193 status = "disabled";
1194 };
1195
1196 pcie2: pcie@3500000 {
1197 compatible = "fsl,lx2
1198 reg = <0x00 0x0350000
1199 <0x88 0x0000000
1200 reg-names = "csr_axi_
1201 interrupts = <GIC_SPI
1202 <GIC_SPI
1203 <GIC_SPI
1204 interrupt-names = "ae
1205 #address-cells = <3>;
1206 #size-cells = <2>;
1207 device_type = "pci";
1208 dma-coherent;
1209 apio-wins = <8>;
1210 ppio-wins = <8>;
1211 bus-range = <0x0 0xff
1212 ranges = <0x82000000
1213 msi-parent = <&its 0>
1214 #interrupt-cells = <1
1215 interrupt-map-mask =
1216 interrupt-map = <0000
1217 <0000
1218 <0000
1219 <0000
1220 iommu-map = <0 &smmu
1221 status = "disabled";
1222 };
1223
1224 pcie3: pcie@3600000 {
1225 compatible = "fsl,lx2
1226 reg = <0x00 0x0360000
1227 <0x90 0x0000000
1228 reg-names = "csr_axi_
1229 interrupts = <GIC_SPI
1230 <GIC_SPI
1231 <GIC_SPI
1232 interrupt-names = "ae
1233 #address-cells = <3>;
1234 #size-cells = <2>;
1235 device_type = "pci";
1236 dma-coherent;
1237 apio-wins = <256>;
1238 ppio-wins = <24>;
1239 bus-range = <0x0 0xff
1240 ranges = <0x82000000
1241 msi-parent = <&its 0>
1242 #interrupt-cells = <1
1243 interrupt-map-mask =
1244 interrupt-map = <0000
1245 <0000
1246 <0000
1247 <0000
1248 iommu-map = <0 &smmu
1249 status = "disabled";
1250 };
1251
1252 pcie4: pcie@3700000 {
1253 compatible = "fsl,lx2
1254 reg = <0x00 0x0370000
1255 <0x98 0x0000000
1256 reg-names = "csr_axi_
1257 interrupts = <GIC_SPI
1258 <GIC_SPI
1259 <GIC_SPI
1260 interrupt-names = "ae
1261 #address-cells = <3>;
1262 #size-cells = <2>;
1263 device_type = "pci";
1264 dma-coherent;
1265 apio-wins = <8>;
1266 ppio-wins = <8>;
1267 bus-range = <0x0 0xff
1268 ranges = <0x82000000
1269 msi-parent = <&its 0>
1270 #interrupt-cells = <1
1271 interrupt-map-mask =
1272 interrupt-map = <0000
1273 <0000
1274 <0000
1275 <0000
1276 iommu-map = <0 &smmu
1277 status = "disabled";
1278 };
1279
1280 pcie5: pcie@3800000 {
1281 compatible = "fsl,lx2
1282 reg = <0x00 0x0380000
1283 <0xa0 0x0000000
1284 reg-names = "csr_axi_
1285 interrupts = <GIC_SPI
1286 <GIC_SPI
1287 <GIC_SPI
1288 interrupt-names = "ae
1289 #address-cells = <3>;
1290 #size-cells = <2>;
1291 device_type = "pci";
1292 dma-coherent;
1293 apio-wins = <256>;
1294 ppio-wins = <24>;
1295 bus-range = <0x0 0xff
1296 ranges = <0x82000000
1297 msi-parent = <&its 0>
1298 #interrupt-cells = <1
1299 interrupt-map-mask =
1300 interrupt-map = <0000
1301 <0000
1302 <0000
1303 <0000
1304 iommu-map = <0 &smmu
1305 status = "disabled";
1306 };
1307
1308 pcie6: pcie@3900000 {
1309 compatible = "fsl,lx2
1310 reg = <0x00 0x0390000
1311 <0xa8 0x0000000
1312 reg-names = "csr_axi_
1313 interrupts = <GIC_SPI
1314 <GIC_SPI
1315 <GIC_SPI
1316 interrupt-names = "ae
1317 #address-cells = <3>;
1318 #size-cells = <2>;
1319 device_type = "pci";
1320 dma-coherent;
1321 apio-wins = <8>;
1322 ppio-wins = <8>;
1323 bus-range = <0x0 0xff
1324 ranges = <0x82000000
1325 msi-parent = <&its 0>
1326 #interrupt-cells = <1
1327 interrupt-map-mask =
1328 interrupt-map = <0000
1329 <0000
1330 <0000
1331 <0000
1332 iommu-map = <0 &smmu
1333 status = "disabled";
1334 };
1335
1336 smmu: iommu@5000000 {
1337 compatible = "arm,mmu
1338 reg = <0 0x5000000 0
1339 #iommu-cells = <1>;
1340 #global-interrupts =
1341 // globa
1342 interrupts = <GIC_SPI
1343 // combi
1344 <GIC_SPI
1345 // globa
1346 <GIC_SPI
1347 // combi
1348 <GIC_SPI
1349 // perfo
1350 <GIC_SPI
1351 <GIC_SPI
1352 <GIC_SPI
1353 <GIC_SPI
1354 <GIC_SPI
1355 <GIC_SPI
1356 <GIC_SPI
1357 <GIC_SPI
1358 <GIC_SPI
1359 <GIC_SPI
1360 // per c
1361 <GIC_SPI
1362 <GIC_SPI
1363 <GIC_SPI
1364 <GIC_SPI
1365 <GIC_SPI
1366 <GIC_SPI
1367 <GIC_SPI
1368 <GIC_SPI
1369 <GIC_SPI
1370 <GIC_SPI
1371 <GIC_SPI
1372 <GIC_SPI
1373 <GIC_SPI
1374 <GIC_SPI
1375 <GIC_SPI
1376 <GIC_SPI
1377 <GIC_SPI
1378 <GIC_SPI
1379 <GIC_SPI
1380 <GIC_SPI
1381 <GIC_SPI
1382 <GIC_SPI
1383 <GIC_SPI
1384 <GIC_SPI
1385 <GIC_SPI
1386 <GIC_SPI
1387 <GIC_SPI
1388 <GIC_SPI
1389 <GIC_SPI
1390 <GIC_SPI
1391 <GIC_SPI
1392 <GIC_SPI
1393 <GIC_SPI
1394 <GIC_SPI
1395 <GIC_SPI
1396 <GIC_SPI
1397 <GIC_SPI
1398 <GIC_SPI
1399 <GIC_SPI
1400 <GIC_SPI
1401 <GIC_SPI
1402 <GIC_SPI
1403 <GIC_SPI
1404 <GIC_SPI
1405 <GIC_SPI
1406 <GIC_SPI
1407 <GIC_SPI
1408 <GIC_SPI
1409 <GIC_SPI
1410 <GIC_SPI
1411 <GIC_SPI
1412 <GIC_SPI
1413 <GIC_SPI
1414 <GIC_SPI
1415 <GIC_SPI
1416 <GIC_SPI
1417 <GIC_SPI
1418 <GIC_SPI
1419 <GIC_SPI
1420 <GIC_SPI
1421 <GIC_SPI
1422 <GIC_SPI
1423 <GIC_SPI
1424 <GIC_SPI
1425 dma-coherent;
1426 };
1427
1428 console@8340020 {
1429 compatible = "fsl,dpa
1430 reg = <0x00000000 0x0
1431 };
1432
1433 ptp-timer@8b95000 {
1434 compatible = "fsl,dpa
1435 reg = <0x0 0x8b95000
1436 clocks = <&clockgen Q
1437 Q
1438 little-endian;
1439 fsl,extts-fifo;
1440 };
1441
1442 /* WRIOP0: 0x8b8_0000, E-MDIO
1443 emdio1: mdio@8b96000 {
1444 compatible = "fsl,fma
1445 reg = <0x0 0x8b96000
1446 interrupts = <GIC_SPI
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1449 little-endian;
1450 clock-frequency = <25
1451 clocks = <&clockgen Q
1452 Q
1453 status = "disabled";
1454 };
1455
1456 emdio2: mdio@8b97000 {
1457 compatible = "fsl,fma
1458 reg = <0x0 0x8b97000
1459 interrupts = <GIC_SPI
1460 little-endian;
1461 #address-cells = <1>;
1462 #size-cells = <0>;
1463 clock-frequency = <25
1464 clocks = <&clockgen Q
1465 Q
1466 status = "disabled";
1467 };
1468
1469 pcs_mdio1: mdio@8c07000 {
1470 compatible = "fsl,fma
1471 reg = <0x0 0x8c07000
1472 little-endian;
1473 #address-cells = <1>;
1474 #size-cells = <0>;
1475 status = "disabled";
1476
1477 pcs1: ethernet-phy@0
1478 reg = <0>;
1479 };
1480 };
1481
1482 pcs_mdio2: mdio@8c0b000 {
1483 compatible = "fsl,fma
1484 reg = <0x0 0x8c0b000
1485 little-endian;
1486 #address-cells = <1>;
1487 #size-cells = <0>;
1488 status = "disabled";
1489
1490 pcs2: ethernet-phy@0
1491 reg = <0>;
1492 };
1493 };
1494
1495 pcs_mdio3: mdio@8c0f000 {
1496 compatible = "fsl,fma
1497 reg = <0x0 0x8c0f000
1498 little-endian;
1499 #address-cells = <1>;
1500 #size-cells = <0>;
1501 status = "disabled";
1502
1503 pcs3: ethernet-phy@0
1504 reg = <0>;
1505 };
1506 };
1507
1508 pcs_mdio4: mdio@8c13000 {
1509 compatible = "fsl,fma
1510 reg = <0x0 0x8c13000
1511 little-endian;
1512 #address-cells = <1>;
1513 #size-cells = <0>;
1514 status = "disabled";
1515
1516 pcs4: ethernet-phy@0
1517 reg = <0>;
1518 };
1519 };
1520
1521 pcs_mdio5: mdio@8c17000 {
1522 compatible = "fsl,fma
1523 reg = <0x0 0x8c17000
1524 little-endian;
1525 #address-cells = <1>;
1526 #size-cells = <0>;
1527 status = "disabled";
1528
1529 pcs5: ethernet-phy@0
1530 reg = <0>;
1531 };
1532 };
1533
1534 pcs_mdio6: mdio@8c1b000 {
1535 compatible = "fsl,fma
1536 reg = <0x0 0x8c1b000
1537 little-endian;
1538 #address-cells = <1>;
1539 #size-cells = <0>;
1540 status = "disabled";
1541
1542 pcs6: ethernet-phy@0
1543 reg = <0>;
1544 };
1545 };
1546
1547 pcs_mdio7: mdio@8c1f000 {
1548 compatible = "fsl,fma
1549 reg = <0x0 0x8c1f000
1550 little-endian;
1551 #address-cells = <1>;
1552 #size-cells = <0>;
1553 status = "disabled";
1554
1555 pcs7: ethernet-phy@0
1556 reg = <0>;
1557 };
1558 };
1559
1560 pcs_mdio8: mdio@8c23000 {
1561 compatible = "fsl,fma
1562 reg = <0x0 0x8c23000
1563 little-endian;
1564 #address-cells = <1>;
1565 #size-cells = <0>;
1566 status = "disabled";
1567
1568 pcs8: ethernet-phy@0
1569 reg = <0>;
1570 };
1571 };
1572
1573 pcs_mdio9: mdio@8c27000 {
1574 compatible = "fsl,fma
1575 reg = <0x0 0x8c27000
1576 little-endian;
1577 #address-cells = <1>;
1578 #size-cells = <0>;
1579 status = "disabled";
1580
1581 pcs9: ethernet-phy@0
1582 reg = <0>;
1583 };
1584 };
1585
1586 pcs_mdio10: mdio@8c2b000 {
1587 compatible = "fsl,fma
1588 reg = <0x0 0x8c2b000
1589 little-endian;
1590 #address-cells = <1>;
1591 #size-cells = <0>;
1592 status = "disabled";
1593
1594 pcs10: ethernet-phy@0
1595 reg = <0>;
1596 };
1597 };
1598
1599 pcs_mdio11: mdio@8c2f000 {
1600 compatible = "fsl,fma
1601 reg = <0x0 0x8c2f000
1602 little-endian;
1603 #address-cells = <1>;
1604 #size-cells = <0>;
1605 status = "disabled";
1606
1607 pcs11: ethernet-phy@0
1608 reg = <0>;
1609 };
1610 };
1611
1612 pcs_mdio12: mdio@8c33000 {
1613 compatible = "fsl,fma
1614 reg = <0x0 0x8c33000
1615 little-endian;
1616 #address-cells = <1>;
1617 #size-cells = <0>;
1618 status = "disabled";
1619
1620 pcs12: ethernet-phy@0
1621 reg = <0>;
1622 };
1623 };
1624
1625 pcs_mdio13: mdio@8c37000 {
1626 compatible = "fsl,fma
1627 reg = <0x0 0x8c37000
1628 little-endian;
1629 #address-cells = <1>;
1630 #size-cells = <0>;
1631 status = "disabled";
1632
1633 pcs13: ethernet-phy@0
1634 reg = <0>;
1635 };
1636 };
1637
1638 pcs_mdio14: mdio@8c3b000 {
1639 compatible = "fsl,fma
1640 reg = <0x0 0x8c3b000
1641 little-endian;
1642 #address-cells = <1>;
1643 #size-cells = <0>;
1644 status = "disabled";
1645
1646 pcs14: ethernet-phy@0
1647 reg = <0>;
1648 };
1649 };
1650
1651 pcs_mdio15: mdio@8c3f000 {
1652 compatible = "fsl,fma
1653 reg = <0x0 0x8c3f000
1654 little-endian;
1655 #address-cells = <1>;
1656 #size-cells = <0>;
1657 status = "disabled";
1658
1659 pcs15: ethernet-phy@0
1660 reg = <0>;
1661 };
1662 };
1663
1664 pcs_mdio16: mdio@8c43000 {
1665 compatible = "fsl,fma
1666 reg = <0x0 0x8c43000
1667 little-endian;
1668 #address-cells = <1>;
1669 #size-cells = <0>;
1670 status = "disabled";
1671
1672 pcs16: ethernet-phy@0
1673 reg = <0>;
1674 };
1675 };
1676
1677 pcs_mdio17: mdio@8c47000 {
1678 compatible = "fsl,fma
1679 reg = <0x0 0x8c47000
1680 little-endian;
1681 #address-cells = <1>;
1682 #size-cells = <0>;
1683 status = "disabled";
1684
1685 pcs17: ethernet-phy@0
1686 reg = <0>;
1687 };
1688 };
1689
1690 pcs_mdio18: mdio@8c4b000 {
1691 compatible = "fsl,fma
1692 reg = <0x0 0x8c4b000
1693 little-endian;
1694 #address-cells = <1>;
1695 #size-cells = <0>;
1696 status = "disabled";
1697
1698 pcs18: ethernet-phy@0
1699 reg = <0>;
1700 };
1701 };
1702
1703 pinmux_i2crv: pinmux@70010012
1704 compatible = "pinctrl
1705 reg = <0x00000007 0x0
1706 #address-cells = <1>;
1707 #size-cells = <0>;
1708 pinctrl-single,bit-pe
1709 pinctrl-single,regist
1710 pinctrl-single,functi
1711
1712 i2c1_scl: i2c1-scl-pi
1713 pinctrl-singl
1714 };
1715
1716 i2c1_scl_gpio: i2c1-s
1717 pinctrl-singl
1718 };
1719
1720 i2c2_scl: i2c2-scl-pi
1721 pinctrl-singl
1722 };
1723
1724 i2c2_scl_gpio: i2c2-s
1725 pinctrl-singl
1726 };
1727
1728 i2c3_scl: i2c3-scl-pi
1729 pinctrl-singl
1730 };
1731
1732 i2c3_scl_gpio: i2c3-s
1733 pinctrl-singl
1734 };
1735
1736 i2c4_scl: i2c4-scl-pi
1737 pinctrl-singl
1738 };
1739
1740 i2c4_scl_gpio: i2c4-s
1741 pinctrl-singl
1742 };
1743
1744 i2c5_scl: i2c5-scl-pi
1745 pinctrl-singl
1746 };
1747
1748 i2c5_scl_gpio: i2c5-s
1749 pinctrl-singl
1750 };
1751
1752 i2c6_scl: i2c6-scl-pi
1753 pinctrl-singl
1754 };
1755
1756 i2c6_scl_gpio: i2c6-s
1757 pinctrl-singl
1758 };
1759
1760 i2c7_scl: i2c7-scl-pi
1761 pinctrl-singl
1762 };
1763
1764 i2c7_scl_gpio: i2c7-s
1765 pinctrl-singl
1766 };
1767
1768 i2c0_scl: i2c0-scl-pi
1769 pinctrl-singl
1770 };
1771
1772 i2c0_scl_gpio: i2c0-s
1773 pinctrl-singl
1774 };
1775 };
1776
1777 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qor
1779 reg = <0x00000008 0x0
1780 <0x00000000 0x0
1781 msi-parent = <&its 0>
1782 /* iommu-map property
1783 iommu-map = <0 &smmu
1784 dma-coherent;
1785 #address-cells = <3>;
1786 #size-cells = <1>;
1787
1788 /*
1789 * Region type 0x0 -
1790 * Region type 0x1 -
1791 */
1792 ranges = <0x0 0x0 0x0
1793 0x1 0x0 0x0
1794
1795 /*
1796 * Define the maximum
1797 */
1798 dpmacs {
1799 #address-cell
1800 #size-cells =
1801
1802 dpmac1: ether
1803 compa
1804 reg =
1805 pcs-h
1806 };
1807
1808 dpmac2: ether
1809 compa
1810 reg =
1811 pcs-h
1812 };
1813
1814 dpmac3: ether
1815 compa
1816 reg =
1817 pcs-h
1818 };
1819
1820 dpmac4: ether
1821 compa
1822 reg =
1823 pcs-h
1824 };
1825
1826 dpmac5: ether
1827 compa
1828 reg =
1829 pcs-h
1830 };
1831
1832 dpmac6: ether
1833 compa
1834 reg =
1835 pcs-h
1836 };
1837
1838 dpmac7: ether
1839 compa
1840 reg =
1841 pcs-h
1842 };
1843
1844 dpmac8: ether
1845 compa
1846 reg =
1847 pcs-h
1848 };
1849
1850 dpmac9: ether
1851 compa
1852 reg =
1853 pcs-h
1854 };
1855
1856 dpmac10: ethe
1857 compa
1858 reg =
1859 pcs-h
1860 };
1861
1862 dpmac11: ethe
1863 compa
1864 reg =
1865 pcs-h
1866 };
1867
1868 dpmac12: ethe
1869 compa
1870 reg =
1871 pcs-h
1872 };
1873
1874 dpmac13: ethe
1875 compa
1876 reg =
1877 pcs-h
1878 };
1879
1880 dpmac14: ethe
1881 compa
1882 reg =
1883 pcs-h
1884 };
1885
1886 dpmac15: ethe
1887 compa
1888 reg =
1889 pcs-h
1890 };
1891
1892 dpmac16: ethe
1893 compa
1894 reg =
1895 pcs-h
1896 };
1897
1898 dpmac17: ethe
1899 compa
1900 reg =
1901 pcs-h
1902 };
1903
1904 dpmac18: ethe
1905 compa
1906 reg =
1907 pcs-h
1908 };
1909 };
1910 };
1911 };
1912
1913 firmware {
1914 optee: optee {
1915 compatible = "linaro,
1916 method = "smc";
1917 status = "disabled";
1918 };
1919 };
1920 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.