1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree Include file for Layerscape-LX2 3 // Device Tree Include file for Layerscape-LX2160A family SoC.
4 // 4 //
5 // Copyright 2018-2020 NXP !! 5 // Copyright 2018 NXP
6 6
7 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
8 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h> <<
11 9
12 /memreserve/ 0x80000000 0x00010000; 10 /memreserve/ 0x80000000 0x00010000;
13 11
14 / { 12 / {
15 compatible = "fsl,lx2160a"; 13 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>; 14 interrupt-parent = <&gic>;
17 #address-cells = <2>; 15 #address-cells = <2>;
18 #size-cells = <2>; 16 #size-cells = <2>;
19 17
20 aliases { <<
21 rtc1 = &ftm_alarm0; <<
22 }; <<
23 <<
24 cpus { 18 cpus {
25 #address-cells = <1>; 19 #address-cells = <1>;
26 #size-cells = <0>; 20 #size-cells = <0>;
27 21
28 // 8 clusters having 2 Cortex- 22 // 8 clusters having 2 Cortex-A72 cores each
29 cpu0: cpu@0 { !! 23 cpu@0 {
30 device_type = "cpu"; 24 device_type = "cpu";
31 compatible = "arm,cort 25 compatible = "arm,cortex-a72";
32 enable-method = "psci" 26 enable-method = "psci";
33 reg = <0x0>; 27 reg = <0x0>;
34 clocks = <&clockgen QO !! 28 clocks = <&clockgen 1 0>;
35 d-cache-size = <0x8000 29 d-cache-size = <0x8000>;
36 d-cache-line-size = <6 30 d-cache-line-size = <64>;
37 d-cache-sets = <128>; 31 d-cache-sets = <128>;
38 i-cache-size = <0xC000 32 i-cache-size = <0xC000>;
39 i-cache-line-size = <6 33 i-cache-line-size = <64>;
40 i-cache-sets = <192>; 34 i-cache-sets = <192>;
41 next-level-cache = <&c 35 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cp <<
43 #cooling-cells = <2>; <<
44 }; 36 };
45 37
46 cpu1: cpu@1 { !! 38 cpu@1 {
47 device_type = "cpu"; 39 device_type = "cpu";
48 compatible = "arm,cort 40 compatible = "arm,cortex-a72";
49 enable-method = "psci" 41 enable-method = "psci";
50 reg = <0x1>; 42 reg = <0x1>;
51 clocks = <&clockgen QO !! 43 clocks = <&clockgen 1 0>;
52 d-cache-size = <0x8000 44 d-cache-size = <0x8000>;
53 d-cache-line-size = <6 45 d-cache-line-size = <64>;
54 d-cache-sets = <128>; 46 d-cache-sets = <128>;
55 i-cache-size = <0xC000 47 i-cache-size = <0xC000>;
56 i-cache-line-size = <6 48 i-cache-line-size = <64>;
57 i-cache-sets = <192>; 49 i-cache-sets = <192>;
58 next-level-cache = <&c 50 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cp <<
60 #cooling-cells = <2>; <<
61 }; 51 };
62 52
63 cpu100: cpu@100 { !! 53 cpu@100 {
64 device_type = "cpu"; 54 device_type = "cpu";
65 compatible = "arm,cort 55 compatible = "arm,cortex-a72";
66 enable-method = "psci" 56 enable-method = "psci";
67 reg = <0x100>; 57 reg = <0x100>;
68 clocks = <&clockgen QO !! 58 clocks = <&clockgen 1 1>;
69 d-cache-size = <0x8000 59 d-cache-size = <0x8000>;
70 d-cache-line-size = <6 60 d-cache-line-size = <64>;
71 d-cache-sets = <128>; 61 d-cache-sets = <128>;
72 i-cache-size = <0xC000 62 i-cache-size = <0xC000>;
73 i-cache-line-size = <6 63 i-cache-line-size = <64>;
74 i-cache-sets = <192>; 64 i-cache-sets = <192>;
75 next-level-cache = <&c 65 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cp <<
77 #cooling-cells = <2>; <<
78 }; 66 };
79 67
80 cpu101: cpu@101 { !! 68 cpu@101 {
81 device_type = "cpu"; 69 device_type = "cpu";
82 compatible = "arm,cort 70 compatible = "arm,cortex-a72";
83 enable-method = "psci" 71 enable-method = "psci";
84 reg = <0x101>; 72 reg = <0x101>;
85 clocks = <&clockgen QO !! 73 clocks = <&clockgen 1 1>;
86 d-cache-size = <0x8000 74 d-cache-size = <0x8000>;
87 d-cache-line-size = <6 75 d-cache-line-size = <64>;
88 d-cache-sets = <128>; 76 d-cache-sets = <128>;
89 i-cache-size = <0xC000 77 i-cache-size = <0xC000>;
90 i-cache-line-size = <6 78 i-cache-line-size = <64>;
91 i-cache-sets = <192>; 79 i-cache-sets = <192>;
92 next-level-cache = <&c 80 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cp <<
94 #cooling-cells = <2>; <<
95 }; 81 };
96 82
97 cpu200: cpu@200 { !! 83 cpu@200 {
98 device_type = "cpu"; 84 device_type = "cpu";
99 compatible = "arm,cort 85 compatible = "arm,cortex-a72";
100 enable-method = "psci" 86 enable-method = "psci";
101 reg = <0x200>; 87 reg = <0x200>;
102 clocks = <&clockgen QO !! 88 clocks = <&clockgen 1 2>;
103 d-cache-size = <0x8000 89 d-cache-size = <0x8000>;
104 d-cache-line-size = <6 90 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 91 d-cache-sets = <128>;
106 i-cache-size = <0xC000 92 i-cache-size = <0xC000>;
107 i-cache-line-size = <6 93 i-cache-line-size = <64>;
108 i-cache-sets = <192>; 94 i-cache-sets = <192>;
109 next-level-cache = <&c 95 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cp <<
111 #cooling-cells = <2>; <<
112 }; 96 };
113 97
114 cpu201: cpu@201 { !! 98 cpu@201 {
115 device_type = "cpu"; 99 device_type = "cpu";
116 compatible = "arm,cort 100 compatible = "arm,cortex-a72";
117 enable-method = "psci" 101 enable-method = "psci";
118 reg = <0x201>; 102 reg = <0x201>;
119 clocks = <&clockgen QO !! 103 clocks = <&clockgen 1 2>;
120 d-cache-size = <0x8000 104 d-cache-size = <0x8000>;
121 d-cache-line-size = <6 105 d-cache-line-size = <64>;
122 d-cache-sets = <128>; 106 d-cache-sets = <128>;
123 i-cache-size = <0xC000 107 i-cache-size = <0xC000>;
124 i-cache-line-size = <6 108 i-cache-line-size = <64>;
125 i-cache-sets = <192>; 109 i-cache-sets = <192>;
126 next-level-cache = <&c 110 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cp <<
128 #cooling-cells = <2>; <<
129 }; 111 };
130 112
131 cpu300: cpu@300 { !! 113 cpu@300 {
132 device_type = "cpu"; 114 device_type = "cpu";
133 compatible = "arm,cort 115 compatible = "arm,cortex-a72";
134 enable-method = "psci" 116 enable-method = "psci";
135 reg = <0x300>; 117 reg = <0x300>;
136 clocks = <&clockgen QO !! 118 clocks = <&clockgen 1 3>;
137 d-cache-size = <0x8000 119 d-cache-size = <0x8000>;
138 d-cache-line-size = <6 120 d-cache-line-size = <64>;
139 d-cache-sets = <128>; 121 d-cache-sets = <128>;
140 i-cache-size = <0xC000 122 i-cache-size = <0xC000>;
141 i-cache-line-size = <6 123 i-cache-line-size = <64>;
142 i-cache-sets = <192>; 124 i-cache-sets = <192>;
143 next-level-cache = <&c 125 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cp <<
145 #cooling-cells = <2>; <<
146 }; 126 };
147 127
148 cpu301: cpu@301 { !! 128 cpu@301 {
149 device_type = "cpu"; 129 device_type = "cpu";
150 compatible = "arm,cort 130 compatible = "arm,cortex-a72";
151 enable-method = "psci" 131 enable-method = "psci";
152 reg = <0x301>; 132 reg = <0x301>;
153 clocks = <&clockgen QO !! 133 clocks = <&clockgen 1 3>;
154 d-cache-size = <0x8000 134 d-cache-size = <0x8000>;
155 d-cache-line-size = <6 135 d-cache-line-size = <64>;
156 d-cache-sets = <128>; 136 d-cache-sets = <128>;
157 i-cache-size = <0xC000 137 i-cache-size = <0xC000>;
158 i-cache-line-size = <6 138 i-cache-line-size = <64>;
159 i-cache-sets = <192>; 139 i-cache-sets = <192>;
160 next-level-cache = <&c 140 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cp <<
162 #cooling-cells = <2>; <<
163 }; 141 };
164 142
165 cpu400: cpu@400 { !! 143 cpu@400 {
166 device_type = "cpu"; 144 device_type = "cpu";
167 compatible = "arm,cort 145 compatible = "arm,cortex-a72";
168 enable-method = "psci" 146 enable-method = "psci";
169 reg = <0x400>; 147 reg = <0x400>;
170 clocks = <&clockgen QO !! 148 clocks = <&clockgen 1 4>;
171 d-cache-size = <0x8000 149 d-cache-size = <0x8000>;
172 d-cache-line-size = <6 150 d-cache-line-size = <64>;
173 d-cache-sets = <128>; 151 d-cache-sets = <128>;
174 i-cache-size = <0xC000 152 i-cache-size = <0xC000>;
175 i-cache-line-size = <6 153 i-cache-line-size = <64>;
176 i-cache-sets = <192>; 154 i-cache-sets = <192>;
177 next-level-cache = <&c 155 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cp <<
179 #cooling-cells = <2>; <<
180 }; 156 };
181 157
182 cpu401: cpu@401 { !! 158 cpu@401 {
183 device_type = "cpu"; 159 device_type = "cpu";
184 compatible = "arm,cort 160 compatible = "arm,cortex-a72";
185 enable-method = "psci" 161 enable-method = "psci";
186 reg = <0x401>; 162 reg = <0x401>;
187 clocks = <&clockgen QO !! 163 clocks = <&clockgen 1 4>;
188 d-cache-size = <0x8000 164 d-cache-size = <0x8000>;
189 d-cache-line-size = <6 165 d-cache-line-size = <64>;
190 d-cache-sets = <128>; 166 d-cache-sets = <128>;
191 i-cache-size = <0xC000 167 i-cache-size = <0xC000>;
192 i-cache-line-size = <6 168 i-cache-line-size = <64>;
193 i-cache-sets = <192>; 169 i-cache-sets = <192>;
194 next-level-cache = <&c 170 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cp <<
196 #cooling-cells = <2>; <<
197 }; 171 };
198 172
199 cpu500: cpu@500 { !! 173 cpu@500 {
200 device_type = "cpu"; 174 device_type = "cpu";
201 compatible = "arm,cort 175 compatible = "arm,cortex-a72";
202 enable-method = "psci" 176 enable-method = "psci";
203 reg = <0x500>; 177 reg = <0x500>;
204 clocks = <&clockgen QO !! 178 clocks = <&clockgen 1 5>;
205 d-cache-size = <0x8000 179 d-cache-size = <0x8000>;
206 d-cache-line-size = <6 180 d-cache-line-size = <64>;
207 d-cache-sets = <128>; 181 d-cache-sets = <128>;
208 i-cache-size = <0xC000 182 i-cache-size = <0xC000>;
209 i-cache-line-size = <6 183 i-cache-line-size = <64>;
210 i-cache-sets = <192>; 184 i-cache-sets = <192>;
211 next-level-cache = <&c 185 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cp <<
213 #cooling-cells = <2>; <<
214 }; 186 };
215 187
216 cpu501: cpu@501 { !! 188 cpu@501 {
217 device_type = "cpu"; 189 device_type = "cpu";
218 compatible = "arm,cort 190 compatible = "arm,cortex-a72";
219 enable-method = "psci" 191 enable-method = "psci";
220 reg = <0x501>; 192 reg = <0x501>;
221 clocks = <&clockgen QO !! 193 clocks = <&clockgen 1 5>;
222 d-cache-size = <0x8000 194 d-cache-size = <0x8000>;
223 d-cache-line-size = <6 195 d-cache-line-size = <64>;
224 d-cache-sets = <128>; 196 d-cache-sets = <128>;
225 i-cache-size = <0xC000 197 i-cache-size = <0xC000>;
226 i-cache-line-size = <6 198 i-cache-line-size = <64>;
227 i-cache-sets = <192>; 199 i-cache-sets = <192>;
228 next-level-cache = <&c 200 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cp <<
230 #cooling-cells = <2>; <<
231 }; 201 };
232 202
233 cpu600: cpu@600 { !! 203 cpu@600 {
234 device_type = "cpu"; 204 device_type = "cpu";
235 compatible = "arm,cort 205 compatible = "arm,cortex-a72";
236 enable-method = "psci" 206 enable-method = "psci";
237 reg = <0x600>; 207 reg = <0x600>;
238 clocks = <&clockgen QO !! 208 clocks = <&clockgen 1 6>;
239 d-cache-size = <0x8000 209 d-cache-size = <0x8000>;
240 d-cache-line-size = <6 210 d-cache-line-size = <64>;
241 d-cache-sets = <128>; 211 d-cache-sets = <128>;
242 i-cache-size = <0xC000 212 i-cache-size = <0xC000>;
243 i-cache-line-size = <6 213 i-cache-line-size = <64>;
244 i-cache-sets = <192>; 214 i-cache-sets = <192>;
245 next-level-cache = <&c 215 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cp <<
247 #cooling-cells = <2>; <<
248 }; 216 };
249 217
250 cpu601: cpu@601 { !! 218 cpu@601 {
251 device_type = "cpu"; 219 device_type = "cpu";
252 compatible = "arm,cort 220 compatible = "arm,cortex-a72";
253 enable-method = "psci" 221 enable-method = "psci";
254 reg = <0x601>; 222 reg = <0x601>;
255 clocks = <&clockgen QO !! 223 clocks = <&clockgen 1 6>;
256 d-cache-size = <0x8000 224 d-cache-size = <0x8000>;
257 d-cache-line-size = <6 225 d-cache-line-size = <64>;
258 d-cache-sets = <128>; 226 d-cache-sets = <128>;
259 i-cache-size = <0xC000 227 i-cache-size = <0xC000>;
260 i-cache-line-size = <6 228 i-cache-line-size = <64>;
261 i-cache-sets = <192>; 229 i-cache-sets = <192>;
262 next-level-cache = <&c 230 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cp <<
264 #cooling-cells = <2>; <<
265 }; 231 };
266 232
267 cpu700: cpu@700 { !! 233 cpu@700 {
268 device_type = "cpu"; 234 device_type = "cpu";
269 compatible = "arm,cort 235 compatible = "arm,cortex-a72";
270 enable-method = "psci" 236 enable-method = "psci";
271 reg = <0x700>; 237 reg = <0x700>;
272 clocks = <&clockgen QO !! 238 clocks = <&clockgen 1 7>;
273 d-cache-size = <0x8000 239 d-cache-size = <0x8000>;
274 d-cache-line-size = <6 240 d-cache-line-size = <64>;
275 d-cache-sets = <128>; 241 d-cache-sets = <128>;
276 i-cache-size = <0xC000 242 i-cache-size = <0xC000>;
277 i-cache-line-size = <6 243 i-cache-line-size = <64>;
278 i-cache-sets = <192>; 244 i-cache-sets = <192>;
279 next-level-cache = <&c 245 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cp <<
281 #cooling-cells = <2>; <<
282 }; 246 };
283 247
284 cpu701: cpu@701 { !! 248 cpu@701 {
285 device_type = "cpu"; 249 device_type = "cpu";
286 compatible = "arm,cort 250 compatible = "arm,cortex-a72";
287 enable-method = "psci" 251 enable-method = "psci";
288 reg = <0x701>; 252 reg = <0x701>;
289 clocks = <&clockgen QO !! 253 clocks = <&clockgen 1 7>;
290 d-cache-size = <0x8000 254 d-cache-size = <0x8000>;
291 d-cache-line-size = <6 255 d-cache-line-size = <64>;
292 d-cache-sets = <128>; 256 d-cache-sets = <128>;
293 i-cache-size = <0xC000 257 i-cache-size = <0xC000>;
294 i-cache-line-size = <6 258 i-cache-line-size = <64>;
295 i-cache-sets = <192>; 259 i-cache-sets = <192>;
296 next-level-cache = <&c 260 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cp <<
298 #cooling-cells = <2>; <<
299 }; 261 };
300 262
301 cluster0_l2: l2-cache0 { 263 cluster0_l2: l2-cache0 {
302 compatible = "cache"; 264 compatible = "cache";
303 cache-unified; <<
304 cache-size = <0x100000 265 cache-size = <0x100000>;
305 cache-line-size = <64> 266 cache-line-size = <64>;
306 cache-sets = <1024>; 267 cache-sets = <1024>;
307 cache-level = <2>; 268 cache-level = <2>;
308 }; 269 };
309 270
310 cluster1_l2: l2-cache1 { 271 cluster1_l2: l2-cache1 {
311 compatible = "cache"; 272 compatible = "cache";
312 cache-unified; <<
313 cache-size = <0x100000 273 cache-size = <0x100000>;
314 cache-line-size = <64> 274 cache-line-size = <64>;
315 cache-sets = <1024>; 275 cache-sets = <1024>;
316 cache-level = <2>; 276 cache-level = <2>;
317 }; 277 };
318 278
319 cluster2_l2: l2-cache2 { 279 cluster2_l2: l2-cache2 {
320 compatible = "cache"; 280 compatible = "cache";
321 cache-unified; <<
322 cache-size = <0x100000 281 cache-size = <0x100000>;
323 cache-line-size = <64> 282 cache-line-size = <64>;
324 cache-sets = <1024>; 283 cache-sets = <1024>;
325 cache-level = <2>; 284 cache-level = <2>;
326 }; 285 };
327 286
328 cluster3_l2: l2-cache3 { 287 cluster3_l2: l2-cache3 {
329 compatible = "cache"; 288 compatible = "cache";
330 cache-unified; <<
331 cache-size = <0x100000 289 cache-size = <0x100000>;
332 cache-line-size = <64> 290 cache-line-size = <64>;
333 cache-sets = <1024>; 291 cache-sets = <1024>;
334 cache-level = <2>; 292 cache-level = <2>;
335 }; 293 };
336 294
337 cluster4_l2: l2-cache4 { 295 cluster4_l2: l2-cache4 {
338 compatible = "cache"; 296 compatible = "cache";
339 cache-unified; <<
340 cache-size = <0x100000 297 cache-size = <0x100000>;
341 cache-line-size = <64> 298 cache-line-size = <64>;
342 cache-sets = <1024>; 299 cache-sets = <1024>;
343 cache-level = <2>; 300 cache-level = <2>;
344 }; 301 };
345 302
346 cluster5_l2: l2-cache5 { 303 cluster5_l2: l2-cache5 {
347 compatible = "cache"; 304 compatible = "cache";
348 cache-unified; <<
349 cache-size = <0x100000 305 cache-size = <0x100000>;
350 cache-line-size = <64> 306 cache-line-size = <64>;
351 cache-sets = <1024>; 307 cache-sets = <1024>;
352 cache-level = <2>; 308 cache-level = <2>;
353 }; 309 };
354 310
355 cluster6_l2: l2-cache6 { 311 cluster6_l2: l2-cache6 {
356 compatible = "cache"; 312 compatible = "cache";
357 cache-unified; <<
358 cache-size = <0x100000 313 cache-size = <0x100000>;
359 cache-line-size = <64> 314 cache-line-size = <64>;
360 cache-sets = <1024>; 315 cache-sets = <1024>;
361 cache-level = <2>; 316 cache-level = <2>;
362 }; 317 };
363 318
364 cluster7_l2: l2-cache7 { 319 cluster7_l2: l2-cache7 {
365 compatible = "cache"; 320 compatible = "cache";
366 cache-unified; <<
367 cache-size = <0x100000 321 cache-size = <0x100000>;
368 cache-line-size = <64> 322 cache-line-size = <64>;
369 cache-sets = <1024>; 323 cache-sets = <1024>;
370 cache-level = <2>; 324 cache-level = <2>;
371 }; 325 };
372 <<
373 cpu_pw15: cpu-pw15 { <<
374 compatible = "arm,idle <<
375 idle-state-name = "PW1 <<
376 arm,psci-suspend-param <<
377 entry-latency-us = <20 <<
378 exit-latency-us = <200 <<
379 min-residency-us = <60 <<
380 }; <<
381 }; 326 };
382 327
383 gic: interrupt-controller@6000000 { 328 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3"; 329 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x1000 330 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x20 331 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
387 332 // SGI_base)
388 <0x0 0x0c0c0000 0 0x20 333 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x10 334 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20 335 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>; 336 #interrupt-cells = <3>;
392 #address-cells = <2>; 337 #address-cells = <2>;
393 #size-cells = <2>; 338 #size-cells = <2>;
394 ranges; 339 ranges;
395 interrupt-controller; 340 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TY 341 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
397 342
398 its: msi-controller@6020000 { !! 343 its: gic-its@6020000 {
399 compatible = "arm,gic- 344 compatible = "arm,gic-v3-its";
400 msi-controller; 345 msi-controller;
401 #msi-cells = <1>; <<
402 reg = <0x0 0x6020000 0 346 reg = <0x0 0x6020000 0 0x20000>;
403 }; 347 };
404 }; 348 };
405 349
406 timer { 350 timer {
407 compatible = "arm,armv8-timer" 351 compatible = "arm,armv8-timer";
408 interrupts = <GIC_PPI 13 IRQ_T 352 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 14 IRQ_T 353 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 11 IRQ_T 354 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_PPI 10 IRQ_T 355 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
412 }; 356 };
413 357
414 pmu { 358 pmu {
415 compatible = "arm,cortex-a72-p 359 compatible = "arm,cortex-a72-pmu";
416 interrupts = <GIC_PPI 7 IRQ_TY 360 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
417 }; 361 };
418 362
419 psci { 363 psci {
420 compatible = "arm,psci-0.2"; 364 compatible = "arm,psci-0.2";
421 method = "smc"; 365 method = "smc";
422 }; 366 };
423 367
424 memory@80000000 { 368 memory@80000000 {
425 // DRAM space - 1, size : 2 GB 369 // DRAM space - 1, size : 2 GB DRAM
426 device_type = "memory"; 370 device_type = "memory";
427 reg = <0x00000000 0x80000000 0 371 reg = <0x00000000 0x80000000 0 0x80000000>;
428 }; 372 };
429 373
430 ddr1: memory-controller@1080000 { 374 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory 375 compatible = "fsl,qoriq-memory-controller";
432 reg = <0x0 0x1080000 0x0 0x100 376 reg = <0x0 0x1080000 0x0 0x1000>;
433 interrupts = <GIC_SPI 17 IRQ_T 377 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
434 little-endian; 378 little-endian;
435 }; 379 };
436 380
437 ddr2: memory-controller@1090000 { 381 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory 382 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1090000 0x0 0x100 383 reg = <0x0 0x1090000 0x0 0x1000>;
440 interrupts = <GIC_SPI 18 IRQ_T 384 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
441 little-endian; 385 little-endian;
442 }; 386 };
443 387
444 // One clock unit-sysclk node which bo 388 // One clock unit-sysclk node which bootloader require during DT fix-up
445 sysclk: sysclk { 389 sysclk: sysclk {
446 compatible = "fixed-clock"; 390 compatible = "fixed-clock";
447 #clock-cells = <0>; 391 #clock-cells = <0>;
448 clock-frequency = <100000000>; 392 clock-frequency = <100000000>; // fixed up by bootloader
449 clock-output-names = "sysclk"; 393 clock-output-names = "sysclk";
450 }; 394 };
451 395
452 thermal-zones { <<
453 cluster6-7-thermal { <<
454 polling-delay-passive <<
455 polling-delay = <5000> <<
456 thermal-sensors = <&tm <<
457 <<
458 trips { <<
459 cluster6_7_ale <<
460 temper <<
461 hyster <<
462 type = <<
463 }; <<
464 <<
465 cluster6_7_cri <<
466 temper <<
467 hyster <<
468 type = <<
469 }; <<
470 }; <<
471 <<
472 cooling-maps { <<
473 map0 { <<
474 trip = <<
475 coolin <<
476 <<
477 <<
478 <<
479 <<
480 <<
481 <<
482 <<
483 <<
484 <<
485 <<
486 <<
487 <<
488 <<
489 <<
490 <<
491 <<
492 }; <<
493 }; <<
494 }; <<
495 <<
496 ddr-ctrl5-thermal { <<
497 polling-delay-passive <<
498 polling-delay = <5000> <<
499 thermal-sensors = <&tm <<
500 <<
501 trips { <<
502 ddr-cluster5-a <<
503 temper <<
504 hyster <<
505 type = <<
506 }; <<
507 <<
508 ddr-cluster5-c <<
509 temper <<
510 hyster <<
511 type = <<
512 }; <<
513 }; <<
514 }; <<
515 <<
516 wriop-thermal { <<
517 polling-delay-passive <<
518 polling-delay = <5000> <<
519 thermal-sensors = <&tm <<
520 <<
521 trips { <<
522 wriop-alert { <<
523 temper <<
524 hyster <<
525 type = <<
526 }; <<
527 <<
528 wriop-crit { <<
529 temper <<
530 hyster <<
531 type = <<
532 }; <<
533 }; <<
534 }; <<
535 <<
536 dce-thermal { <<
537 polling-delay-passive <<
538 polling-delay = <5000> <<
539 thermal-sensors = <&tm <<
540 <<
541 trips { <<
542 dce-qbman-aler <<
543 temper <<
544 hyster <<
545 type = <<
546 }; <<
547 <<
548 dce-qbman-crit <<
549 temper <<
550 hyster <<
551 type = <<
552 }; <<
553 }; <<
554 }; <<
555 <<
556 ccn-thermal { <<
557 polling-delay-passive <<
558 polling-delay = <5000> <<
559 thermal-sensors = <&tm <<
560 <<
561 trips { <<
562 ccn-dpaa-alert <<
563 temper <<
564 hyster <<
565 type = <<
566 }; <<
567 <<
568 ccn-dpaa-crit <<
569 temper <<
570 hyster <<
571 type = <<
572 }; <<
573 }; <<
574 }; <<
575 <<
576 cluster4-thermal { <<
577 polling-delay-passive <<
578 polling-delay = <5000> <<
579 thermal-sensors = <&tm <<
580 <<
581 trips { <<
582 clust4-hsio3-a <<
583 temper <<
584 hyster <<
585 type = <<
586 }; <<
587 <<
588 clust4-hsio3-c <<
589 temper <<
590 hyster <<
591 type = <<
592 }; <<
593 }; <<
594 }; <<
595 <<
596 cluster2-3-thermal { <<
597 polling-delay-passive <<
598 polling-delay = <5000> <<
599 thermal-sensors = <&tm <<
600 <<
601 trips { <<
602 cluster2-3-ale <<
603 temper <<
604 hyster <<
605 type = <<
606 }; <<
607 <<
608 cluster2-3-cri <<
609 temper <<
610 hyster <<
611 type = <<
612 }; <<
613 }; <<
614 }; <<
615 }; <<
616 <<
617 soc { 396 soc {
618 compatible = "simple-bus"; 397 compatible = "simple-bus";
619 #address-cells = <2>; 398 #address-cells = <2>;
620 #size-cells = <2>; 399 #size-cells = <2>;
621 ranges; 400 ranges;
622 dma-ranges = <0x0 0x0 0x0 0x0 401 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
623 402
624 serdes_1: phy@1ea0000 { <<
625 compatible = "fsl,lynx <<
626 reg = <0x0 0x1ea0000 0 <<
627 #phy-cells = <1>; <<
628 }; <<
629 <<
630 serdes_2: phy@1eb0000 { <<
631 compatible = "fsl,lynx <<
632 reg = <0x0 0x1eb0000 0 <<
633 #phy-cells = <1>; <<
634 status = "disabled"; <<
635 }; <<
636 <<
637 crypto: crypto@8000000 { 403 crypto: crypto@8000000 {
638 compatible = "fsl,sec- 404 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 fsl,sec-era = <10>; 405 fsl,sec-era = <10>;
640 #address-cells = <1>; 406 #address-cells = <1>;
641 #size-cells = <1>; 407 #size-cells = <1>;
642 ranges = <0x0 0x00 0x8 408 ranges = <0x0 0x00 0x8000000 0x100000>;
643 reg = <0x00 0x8000000 409 reg = <0x00 0x8000000 0x0 0x100000>;
644 interrupts = <GIC_SPI 410 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
645 dma-coherent; 411 dma-coherent;
646 status = "disabled"; 412 status = "disabled";
647 413
648 sec_jr0: jr@10000 { 414 sec_jr0: jr@10000 {
649 compatible = " 415 compatible = "fsl,sec-v5.0-job-ring",
650 " 416 "fsl,sec-v4.0-job-ring";
651 reg = <0x10000 !! 417 reg = <0x10000 0x10000>;
652 interrupts = < 418 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
653 }; 419 };
654 420
655 sec_jr1: jr@20000 { 421 sec_jr1: jr@20000 {
656 compatible = " 422 compatible = "fsl,sec-v5.0-job-ring",
657 " 423 "fsl,sec-v4.0-job-ring";
658 reg = <0x20000 !! 424 reg = <0x20000 0x10000>;
659 interrupts = < 425 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
660 }; 426 };
661 427
662 sec_jr2: jr@30000 { 428 sec_jr2: jr@30000 {
663 compatible = " 429 compatible = "fsl,sec-v5.0-job-ring",
664 " 430 "fsl,sec-v4.0-job-ring";
665 reg = <0x30000 !! 431 reg = <0x30000 0x10000>;
666 interrupts = < 432 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
667 }; 433 };
668 434
669 sec_jr3: jr@40000 { 435 sec_jr3: jr@40000 {
670 compatible = " 436 compatible = "fsl,sec-v5.0-job-ring",
671 " 437 "fsl,sec-v4.0-job-ring";
672 reg = <0x40000 !! 438 reg = <0x40000 0x10000>;
673 interrupts = < 439 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
674 }; 440 };
675 }; 441 };
676 442
677 clockgen: clock-controller@130 443 clockgen: clock-controller@1300000 {
678 compatible = "fsl,lx21 444 compatible = "fsl,lx2160a-clockgen";
679 reg = <0 0x1300000 0 0 445 reg = <0 0x1300000 0 0xa0000>;
680 #clock-cells = <2>; 446 #clock-cells = <2>;
681 clocks = <&sysclk>; 447 clocks = <&sysclk>;
682 }; 448 };
683 449
684 dcfg: syscon@1e00000 { 450 dcfg: syscon@1e00000 {
685 compatible = "fsl,lx21 451 compatible = "fsl,lx2160a-dcfg", "syscon";
686 reg = <0x0 0x1e00000 0 452 reg = <0x0 0x1e00000 0x0 0x10000>;
687 little-endian; 453 little-endian;
688 }; 454 };
689 455
690 sfp: efuse@1e80000 { <<
691 compatible = "fsl,ls10 <<
692 reg = <0x0 0x1e80000 0 <<
693 clocks = <&clockgen QO <<
694 QO <<
695 clock-names = "sfp"; <<
696 }; <<
697 <<
698 isc: syscon@1f70000 { <<
699 compatible = "fsl,lx21 <<
700 reg = <0x0 0x1f70000 0 <<
701 little-endian; <<
702 #address-cells = <1>; <<
703 #size-cells = <1>; <<
704 ranges = <0x0 0x0 0x1f <<
705 <<
706 extirq: interrupt-cont <<
707 compatible = " <<
708 #interrupt-cel <<
709 #address-cells <<
710 interrupt-cont <<
711 reg = <0x14 4> <<
712 interrupt-map <<
713 <0 0 & <<
714 <1 0 & <<
715 <2 0 & <<
716 <3 0 & <<
717 <4 0 & <<
718 <5 0 & <<
719 <6 0 & <<
720 <7 0 & <<
721 <8 0 & <<
722 <9 0 & <<
723 <10 0 <<
724 <11 0 <<
725 interrupt-map- <<
726 }; <<
727 }; <<
728 <<
729 tmu: tmu@1f80000 { <<
730 compatible = "fsl,qori <<
731 reg = <0x0 0x1f80000 0 <<
732 interrupts = <GIC_SPI <<
733 fsl,tmu-range = <0x800 <<
734 fsl,tmu-calibration = <<
735 /* Calibration <<
736 <0x00000000 0x <<
737 /* Calibration <<
738 <0x00000001 0x <<
739 little-endian; <<
740 #thermal-sensor-cells <<
741 }; <<
742 <<
743 i2c0: i2c@2000000 { 456 i2c0: i2c@2000000 {
744 compatible = "fsl,vf61 457 compatible = "fsl,vf610-i2c";
745 #address-cells = <1>; 458 #address-cells = <1>;
746 #size-cells = <0>; 459 #size-cells = <0>;
747 reg = <0x0 0x2000000 0 460 reg = <0x0 0x2000000 0x0 0x10000>;
748 interrupts = <GIC_SPI 461 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
749 clock-names = "ipg"; !! 462 clock-names = "i2c";
750 clocks = <&clockgen QO !! 463 clocks = <&clockgen 4 7>;
751 QO !! 464 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
752 pinctrl-names = "defau <<
753 pinctrl-0 = <&i2c0_scl <<
754 pinctrl-1 = <&i2c0_scl <<
755 scl-gpios = <&gpio0 3 <<
756 status = "disabled"; 465 status = "disabled";
757 }; 466 };
758 467
759 i2c1: i2c@2010000 { 468 i2c1: i2c@2010000 {
760 compatible = "fsl,vf61 469 compatible = "fsl,vf610-i2c";
761 #address-cells = <1>; 470 #address-cells = <1>;
762 #size-cells = <0>; 471 #size-cells = <0>;
763 reg = <0x0 0x2010000 0 472 reg = <0x0 0x2010000 0x0 0x10000>;
764 interrupts = <GIC_SPI 473 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
765 clock-names = "ipg"; !! 474 clock-names = "i2c";
766 clocks = <&clockgen QO !! 475 clocks = <&clockgen 4 7>;
767 QO <<
768 pinctrl-names = "defau <<
769 pinctrl-0 = <&i2c1_scl <<
770 pinctrl-1 = <&i2c1_scl <<
771 scl-gpios = <&gpio0 31 <<
772 status = "disabled"; 476 status = "disabled";
773 }; 477 };
774 478
775 i2c2: i2c@2020000 { 479 i2c2: i2c@2020000 {
776 compatible = "fsl,vf61 480 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>; 481 #address-cells = <1>;
778 #size-cells = <0>; 482 #size-cells = <0>;
779 reg = <0x0 0x2020000 0 483 reg = <0x0 0x2020000 0x0 0x10000>;
780 interrupts = <GIC_SPI 484 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
781 clock-names = "ipg"; !! 485 clock-names = "i2c";
782 clocks = <&clockgen QO !! 486 clocks = <&clockgen 4 7>;
783 QO <<
784 pinctrl-names = "defau <<
785 pinctrl-0 = <&i2c2_scl <<
786 pinctrl-1 = <&i2c2_scl <<
787 scl-gpios = <&gpio0 29 <<
788 status = "disabled"; 487 status = "disabled";
789 }; 488 };
790 489
791 i2c3: i2c@2030000 { 490 i2c3: i2c@2030000 {
792 compatible = "fsl,vf61 491 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>; 492 #address-cells = <1>;
794 #size-cells = <0>; 493 #size-cells = <0>;
795 reg = <0x0 0x2030000 0 494 reg = <0x0 0x2030000 0x0 0x10000>;
796 interrupts = <GIC_SPI 495 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
797 clock-names = "ipg"; !! 496 clock-names = "i2c";
798 clocks = <&clockgen QO !! 497 clocks = <&clockgen 4 7>;
799 QO <<
800 pinctrl-names = "defau <<
801 pinctrl-0 = <&i2c3_scl <<
802 pinctrl-1 = <&i2c3_scl <<
803 scl-gpios = <&gpio0 27 <<
804 status = "disabled"; 498 status = "disabled";
805 }; 499 };
806 500
807 i2c4: i2c@2040000 { 501 i2c4: i2c@2040000 {
808 compatible = "fsl,vf61 502 compatible = "fsl,vf610-i2c";
809 #address-cells = <1>; 503 #address-cells = <1>;
810 #size-cells = <0>; 504 #size-cells = <0>;
811 reg = <0x0 0x2040000 0 505 reg = <0x0 0x2040000 0x0 0x10000>;
812 interrupts = <GIC_SPI 506 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
813 clock-names = "ipg"; !! 507 clock-names = "i2c";
814 clocks = <&clockgen QO !! 508 clocks = <&clockgen 4 7>;
815 QO !! 509 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
816 pinctrl-names = "defau <<
817 pinctrl-0 = <&i2c4_scl <<
818 pinctrl-1 = <&i2c4_scl <<
819 scl-gpios = <&gpio0 25 <<
820 status = "disabled"; 510 status = "disabled";
821 }; 511 };
822 512
823 i2c5: i2c@2050000 { 513 i2c5: i2c@2050000 {
824 compatible = "fsl,vf61 514 compatible = "fsl,vf610-i2c";
825 #address-cells = <1>; 515 #address-cells = <1>;
826 #size-cells = <0>; 516 #size-cells = <0>;
827 reg = <0x0 0x2050000 0 517 reg = <0x0 0x2050000 0x0 0x10000>;
828 interrupts = <GIC_SPI 518 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
829 clock-names = "ipg"; !! 519 clock-names = "i2c";
830 clocks = <&clockgen QO !! 520 clocks = <&clockgen 4 7>;
831 QO <<
832 pinctrl-names = "defau <<
833 pinctrl-0 = <&i2c5_scl <<
834 pinctrl-1 = <&i2c5_scl <<
835 scl-gpios = <&gpio0 23 <<
836 status = "disabled"; 521 status = "disabled";
837 }; 522 };
838 523
839 i2c6: i2c@2060000 { 524 i2c6: i2c@2060000 {
840 compatible = "fsl,vf61 525 compatible = "fsl,vf610-i2c";
841 #address-cells = <1>; 526 #address-cells = <1>;
842 #size-cells = <0>; 527 #size-cells = <0>;
843 reg = <0x0 0x2060000 0 528 reg = <0x0 0x2060000 0x0 0x10000>;
844 interrupts = <GIC_SPI 529 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "ipg"; !! 530 clock-names = "i2c";
846 clocks = <&clockgen QO !! 531 clocks = <&clockgen 4 7>;
847 QO <<
848 pinctrl-names = "defau <<
849 pinctrl-0 = <&i2c6_scl <<
850 pinctrl-1 = <&i2c6_scl <<
851 scl-gpios = <&gpio1 16 <<
852 status = "disabled"; 532 status = "disabled";
853 }; 533 };
854 534
855 i2c7: i2c@2070000 { 535 i2c7: i2c@2070000 {
856 compatible = "fsl,vf61 536 compatible = "fsl,vf610-i2c";
857 #address-cells = <1>; 537 #address-cells = <1>;
858 #size-cells = <0>; 538 #size-cells = <0>;
859 reg = <0x0 0x2070000 0 539 reg = <0x0 0x2070000 0x0 0x10000>;
860 interrupts = <GIC_SPI 540 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
861 clock-names = "ipg"; !! 541 clock-names = "i2c";
862 clocks = <&clockgen QO !! 542 clocks = <&clockgen 4 7>;
863 QO <<
864 pinctrl-names = "defau <<
865 pinctrl-0 = <&i2c7_scl <<
866 pinctrl-1 = <&i2c7_scl <<
867 scl-gpios = <&gpio1 18 <<
868 status = "disabled"; 543 status = "disabled";
869 }; 544 };
870 545
871 fspi: spi@20c0000 { 546 fspi: spi@20c0000 {
872 compatible = "nxp,lx21 547 compatible = "nxp,lx2160a-fspi";
873 #address-cells = <1>; 548 #address-cells = <1>;
874 #size-cells = <0>; 549 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0 550 reg = <0x0 0x20c0000 0x0 0x10000>,
876 <0x0 0x20000000 551 <0x0 0x20000000 0x0 0x10000000>;
877 reg-names = "fspi_base 552 reg-names = "fspi_base", "fspi_mmap";
878 interrupts = <GIC_SPI 553 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clockgen QO !! 554 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
880 QO <<
881 <&clockgen QO <<
882 QO <<
883 clock-names = "fspi_en 555 clock-names = "fspi_en", "fspi";
884 status = "disabled"; 556 status = "disabled";
885 }; 557 };
886 558
887 dspi0: spi@2100000 { !! 559 esdhc0: esdhc@2140000 {
888 compatible = "fsl,lx21 !! 560 compatible = "fsl,esdhc";
889 #address-cells = <1>; <<
890 #size-cells = <0>; <<
891 reg = <0x0 0x2100000 0 <<
892 interrupts = <GIC_SPI <<
893 clocks = <&clockgen QO <<
894 QO <<
895 clock-names = "dspi"; <<
896 spi-num-chipselects = <<
897 bus-num = <0>; <<
898 status = "disabled"; <<
899 }; <<
900 <<
901 dspi1: spi@2110000 { <<
902 compatible = "fsl,lx21 <<
903 #address-cells = <1>; <<
904 #size-cells = <0>; <<
905 reg = <0x0 0x2110000 0 <<
906 interrupts = <GIC_SPI <<
907 clocks = <&clockgen QO <<
908 QO <<
909 clock-names = "dspi"; <<
910 spi-num-chipselects = <<
911 bus-num = <1>; <<
912 status = "disabled"; <<
913 }; <<
914 <<
915 dspi2: spi@2120000 { <<
916 compatible = "fsl,lx21 <<
917 #address-cells = <1>; <<
918 #size-cells = <0>; <<
919 reg = <0x0 0x2120000 0 <<
920 interrupts = <GIC_SPI <<
921 clocks = <&clockgen QO <<
922 QO <<
923 clock-names = "dspi"; <<
924 spi-num-chipselects = <<
925 bus-num = <2>; <<
926 status = "disabled"; <<
927 }; <<
928 <<
929 esdhc0: mmc@2140000 { <<
930 compatible = "fsl,ls20 <<
931 reg = <0x0 0x2140000 0 561 reg = <0x0 0x2140000 0x0 0x10000>;
932 interrupts = <GIC_SPI !! 562 interrupts = <0 28 0x4>; /* Level high type */
933 clocks = <&clockgen QO !! 563 clocks = <&clockgen 4 1>;
934 QO <<
935 dma-coherent; <<
936 voltage-ranges = <1800 564 voltage-ranges = <1800 1800 3300 3300>;
937 sdhci,auto-cmd12; 565 sdhci,auto-cmd12;
938 little-endian; 566 little-endian;
939 bus-width = <4>; 567 bus-width = <4>;
940 status = "disabled"; 568 status = "disabled";
941 }; 569 };
942 570
943 esdhc1: mmc@2150000 { !! 571 esdhc1: esdhc@2150000 {
944 compatible = "fsl,ls20 !! 572 compatible = "fsl,esdhc";
945 reg = <0x0 0x2150000 0 573 reg = <0x0 0x2150000 0x0 0x10000>;
946 interrupts = <GIC_SPI !! 574 interrupts = <0 63 0x4>; /* Level high type */
947 clocks = <&clockgen QO !! 575 clocks = <&clockgen 4 1>;
948 QO <<
949 dma-coherent; <<
950 voltage-ranges = <1800 576 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12; 577 sdhci,auto-cmd12;
952 broken-cd; 578 broken-cd;
953 little-endian; 579 little-endian;
954 bus-width = <4>; 580 bus-width = <4>;
955 status = "disabled"; 581 status = "disabled";
956 }; 582 };
957 583
958 can0: can@2180000 { <<
959 compatible = "fsl,lx21 <<
960 reg = <0x0 0x2180000 0 <<
961 interrupts = <GIC_SPI <<
962 clocks = <&clockgen QO <<
963 QO <<
964 <&clockgen QO <<
965 clock-names = "ipg", " <<
966 fsl,clk-source = /bits <<
967 status = "disabled"; <<
968 }; <<
969 <<
970 can1: can@2190000 { <<
971 compatible = "fsl,lx21 <<
972 reg = <0x0 0x2190000 0 <<
973 interrupts = <GIC_SPI <<
974 clocks = <&clockgen QO <<
975 QO <<
976 <&clockgen QO <<
977 clock-names = "ipg", " <<
978 fsl,clk-source = /bits <<
979 status = "disabled"; <<
980 }; <<
981 <<
982 uart0: serial@21c0000 { 584 uart0: serial@21c0000 {
983 compatible = "arm,pl01 !! 585 compatible = "arm,sbsa-uart","arm,pl011";
984 clocks = <&clockgen QO <<
985 QO <<
986 <&clockgen QO <<
987 QO <<
988 clock-names = "uartclk <<
989 reg = <0x0 0x21c0000 0 586 reg = <0x0 0x21c0000 0x0 0x1000>;
990 interrupts = <GIC_SPI 587 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> 588 current-speed = <115200>;
991 status = "disabled"; 589 status = "disabled";
992 }; 590 };
993 591
994 uart1: serial@21d0000 { 592 uart1: serial@21d0000 {
995 compatible = "arm,pl01 !! 593 compatible = "arm,sbsa-uart","arm,pl011";
996 clocks = <&clockgen QO <<
997 QO <<
998 <&clockgen QO <<
999 QO <<
1000 clock-names = "uartcl <<
1001 reg = <0x0 0x21d0000 594 reg = <0x0 0x21d0000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 595 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> 596 current-speed = <115200>;
1003 status = "disabled"; 597 status = "disabled";
1004 }; 598 };
1005 599
1006 uart2: serial@21e0000 { 600 uart2: serial@21e0000 {
1007 compatible = "arm,pl0 !! 601 compatible = "arm,sbsa-uart","arm,pl011";
1008 clocks = <&clockgen Q <<
1009 Q <<
1010 <&clockgen Q <<
1011 Q <<
1012 clock-names = "uartcl <<
1013 reg = <0x0 0x21e0000 602 reg = <0x0 0x21e0000 0x0 0x1000>;
1014 interrupts = <GIC_SPI 603 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 604 current-speed = <115200>;
1015 status = "disabled"; 605 status = "disabled";
1016 }; 606 };
1017 607
1018 uart3: serial@21f0000 { 608 uart3: serial@21f0000 {
1019 compatible = "arm,pl0 !! 609 compatible = "arm,sbsa-uart","arm,pl011";
1020 clocks = <&clockgen Q <<
1021 Q <<
1022 <&clockgen Q <<
1023 Q <<
1024 clock-names = "uartcl <<
1025 reg = <0x0 0x21f0000 610 reg = <0x0 0x21f0000 0x0 0x1000>;
1026 interrupts = <GIC_SPI 611 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> 612 current-speed = <115200>;
1027 status = "disabled"; 613 status = "disabled";
1028 }; 614 };
1029 615
1030 gpio0: gpio@2300000 { 616 gpio0: gpio@2300000 {
1031 compatible = "fsl,ls2 !! 617 compatible = "fsl,qoriq-gpio";
1032 reg = <0x0 0x2300000 618 reg = <0x0 0x2300000 0x0 0x10000>;
1033 interrupts = <GIC_SPI 619 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1034 gpio-controller; 620 gpio-controller;
1035 little-endian; 621 little-endian;
1036 #gpio-cells = <2>; 622 #gpio-cells = <2>;
1037 interrupt-controller; 623 interrupt-controller;
1038 #interrupt-cells = <2 624 #interrupt-cells = <2>;
1039 }; 625 };
1040 626
1041 gpio1: gpio@2310000 { 627 gpio1: gpio@2310000 {
1042 compatible = "fsl,ls2 !! 628 compatible = "fsl,qoriq-gpio";
1043 reg = <0x0 0x2310000 629 reg = <0x0 0x2310000 0x0 0x10000>;
1044 interrupts = <GIC_SPI 630 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1045 gpio-controller; 631 gpio-controller;
1046 little-endian; 632 little-endian;
1047 #gpio-cells = <2>; 633 #gpio-cells = <2>;
1048 interrupt-controller; 634 interrupt-controller;
1049 #interrupt-cells = <2 635 #interrupt-cells = <2>;
1050 }; 636 };
1051 637
1052 gpio2: gpio@2320000 { 638 gpio2: gpio@2320000 {
1053 compatible = "fsl,ls2 !! 639 compatible = "fsl,qoriq-gpio";
1054 reg = <0x0 0x2320000 640 reg = <0x0 0x2320000 0x0 0x10000>;
1055 interrupts = <GIC_SPI 641 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1056 gpio-controller; 642 gpio-controller;
1057 little-endian; 643 little-endian;
1058 #gpio-cells = <2>; 644 #gpio-cells = <2>;
1059 interrupt-controller; 645 interrupt-controller;
1060 #interrupt-cells = <2 646 #interrupt-cells = <2>;
1061 }; 647 };
1062 648
1063 gpio3: gpio@2330000 { 649 gpio3: gpio@2330000 {
1064 compatible = "fsl,ls2 !! 650 compatible = "fsl,qoriq-gpio";
1065 reg = <0x0 0x2330000 651 reg = <0x0 0x2330000 0x0 0x10000>;
1066 interrupts = <GIC_SPI 652 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1067 gpio-controller; 653 gpio-controller;
1068 little-endian; 654 little-endian;
1069 #gpio-cells = <2>; 655 #gpio-cells = <2>;
1070 interrupt-controller; 656 interrupt-controller;
1071 #interrupt-cells = <2 657 #interrupt-cells = <2>;
1072 }; 658 };
1073 659
1074 watchdog@23a0000 { 660 watchdog@23a0000 {
1075 compatible = "arm,sbs 661 compatible = "arm,sbsa-gwdt";
1076 reg = <0x0 0x23a0000 662 reg = <0x0 0x23a0000 0 0x1000>,
1077 <0x0 0x2390000 663 <0x0 0x2390000 0 0x1000>;
1078 interrupts = <GIC_SPI 664 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1079 timeout-sec = <30>; 665 timeout-sec = <30>;
1080 }; 666 };
1081 667
1082 rcpm: wakeup-controller@1e340 <<
1083 compatible = "fsl,lx2 <<
1084 reg = <0x0 0x1e34040 <<
1085 #fsl,rcpm-wakeup-cell <<
1086 little-endian; <<
1087 }; <<
1088 <<
1089 ftm_alarm0: rtc@2800000 { <<
1090 compatible = "fsl,lx2 <<
1091 reg = <0x0 0x2800000 <<
1092 fsl,rcpm-wakeup = <&r <<
1093 interrupts = <GIC_SPI <<
1094 }; <<
1095 <<
1096 usb0: usb@3100000 { 668 usb0: usb@3100000 {
1097 compatible = "snps,dw 669 compatible = "snps,dwc3";
1098 reg = <0x0 0x3100000 670 reg = <0x0 0x3100000 0x0 0x10000>;
1099 interrupts = <GIC_SPI 671 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1100 dr_mode = "host"; 672 dr_mode = "host";
1101 snps,quirk-frame-leng 673 snps,quirk-frame-length-adjustment = <0x20>;
1102 usb3-lpm-capable; <<
1103 snps,dis_rxdet_inp3_q 674 snps,dis_rxdet_inp3_quirk;
1104 snps,incr-burst-type- 675 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1105 status = "disabled"; 676 status = "disabled";
1106 }; 677 };
1107 678
1108 usb1: usb@3110000 { 679 usb1: usb@3110000 {
1109 compatible = "snps,dw 680 compatible = "snps,dwc3";
1110 reg = <0x0 0x3110000 681 reg = <0x0 0x3110000 0x0 0x10000>;
1111 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1112 dr_mode = "host"; 683 dr_mode = "host";
1113 snps,quirk-frame-leng 684 snps,quirk-frame-length-adjustment = <0x20>;
1114 usb3-lpm-capable; <<
1115 snps,dis_rxdet_inp3_q 685 snps,dis_rxdet_inp3_quirk;
1116 snps,incr-burst-type- 686 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1117 status = "disabled"; 687 status = "disabled";
1118 }; 688 };
1119 689
1120 sata0: sata@3200000 { <<
1121 compatible = "fsl,lx2 <<
1122 reg = <0x0 0x3200000 <<
1123 <0x7 0x100520 0 <<
1124 reg-names = "ahci", " <<
1125 interrupts = <GIC_SPI <<
1126 clocks = <&clockgen Q <<
1127 Q <<
1128 dma-coherent; <<
1129 status = "disabled"; <<
1130 }; <<
1131 <<
1132 sata1: sata@3210000 { <<
1133 compatible = "fsl,lx2 <<
1134 reg = <0x0 0x3210000 <<
1135 <0x7 0x100520 0 <<
1136 reg-names = "ahci", " <<
1137 interrupts = <GIC_SPI <<
1138 clocks = <&clockgen Q <<
1139 Q <<
1140 dma-coherent; <<
1141 status = "disabled"; <<
1142 }; <<
1143 <<
1144 sata2: sata@3220000 { <<
1145 compatible = "fsl,lx2 <<
1146 reg = <0x0 0x3220000 <<
1147 <0x7 0x100520 0 <<
1148 reg-names = "ahci", " <<
1149 interrupts = <GIC_SPI <<
1150 clocks = <&clockgen Q <<
1151 Q <<
1152 dma-coherent; <<
1153 status = "disabled"; <<
1154 }; <<
1155 <<
1156 sata3: sata@3230000 { <<
1157 compatible = "fsl,lx2 <<
1158 reg = <0x0 0x3230000 <<
1159 <0x7 0x100520 0 <<
1160 reg-names = "ahci", " <<
1161 interrupts = <GIC_SPI <<
1162 clocks = <&clockgen Q <<
1163 Q <<
1164 dma-coherent; <<
1165 status = "disabled"; <<
1166 }; <<
1167 <<
1168 pcie1: pcie@3400000 { <<
1169 compatible = "fsl,lx2 <<
1170 reg = <0x00 0x0340000 <<
1171 <0x80 0x0000000 <<
1172 reg-names = "csr_axi_ <<
1173 interrupts = <GIC_SPI <<
1174 <GIC_SPI <<
1175 <GIC_SPI <<
1176 interrupt-names = "ae <<
1177 #address-cells = <3>; <<
1178 #size-cells = <2>; <<
1179 device_type = "pci"; <<
1180 dma-coherent; <<
1181 apio-wins = <8>; <<
1182 ppio-wins = <8>; <<
1183 bus-range = <0x0 0xff <<
1184 ranges = <0x82000000 <<
1185 msi-parent = <&its 0> <<
1186 #interrupt-cells = <1 <<
1187 interrupt-map-mask = <<
1188 interrupt-map = <0000 <<
1189 <0000 <<
1190 <0000 <<
1191 <0000 <<
1192 iommu-map = <0 &smmu <<
1193 status = "disabled"; <<
1194 }; <<
1195 <<
1196 pcie2: pcie@3500000 { <<
1197 compatible = "fsl,lx2 <<
1198 reg = <0x00 0x0350000 <<
1199 <0x88 0x0000000 <<
1200 reg-names = "csr_axi_ <<
1201 interrupts = <GIC_SPI <<
1202 <GIC_SPI <<
1203 <GIC_SPI <<
1204 interrupt-names = "ae <<
1205 #address-cells = <3>; <<
1206 #size-cells = <2>; <<
1207 device_type = "pci"; <<
1208 dma-coherent; <<
1209 apio-wins = <8>; <<
1210 ppio-wins = <8>; <<
1211 bus-range = <0x0 0xff <<
1212 ranges = <0x82000000 <<
1213 msi-parent = <&its 0> <<
1214 #interrupt-cells = <1 <<
1215 interrupt-map-mask = <<
1216 interrupt-map = <0000 <<
1217 <0000 <<
1218 <0000 <<
1219 <0000 <<
1220 iommu-map = <0 &smmu <<
1221 status = "disabled"; <<
1222 }; <<
1223 <<
1224 pcie3: pcie@3600000 { <<
1225 compatible = "fsl,lx2 <<
1226 reg = <0x00 0x0360000 <<
1227 <0x90 0x0000000 <<
1228 reg-names = "csr_axi_ <<
1229 interrupts = <GIC_SPI <<
1230 <GIC_SPI <<
1231 <GIC_SPI <<
1232 interrupt-names = "ae <<
1233 #address-cells = <3>; <<
1234 #size-cells = <2>; <<
1235 device_type = "pci"; <<
1236 dma-coherent; <<
1237 apio-wins = <256>; <<
1238 ppio-wins = <24>; <<
1239 bus-range = <0x0 0xff <<
1240 ranges = <0x82000000 <<
1241 msi-parent = <&its 0> <<
1242 #interrupt-cells = <1 <<
1243 interrupt-map-mask = <<
1244 interrupt-map = <0000 <<
1245 <0000 <<
1246 <0000 <<
1247 <0000 <<
1248 iommu-map = <0 &smmu <<
1249 status = "disabled"; <<
1250 }; <<
1251 <<
1252 pcie4: pcie@3700000 { <<
1253 compatible = "fsl,lx2 <<
1254 reg = <0x00 0x0370000 <<
1255 <0x98 0x0000000 <<
1256 reg-names = "csr_axi_ <<
1257 interrupts = <GIC_SPI <<
1258 <GIC_SPI <<
1259 <GIC_SPI <<
1260 interrupt-names = "ae <<
1261 #address-cells = <3>; <<
1262 #size-cells = <2>; <<
1263 device_type = "pci"; <<
1264 dma-coherent; <<
1265 apio-wins = <8>; <<
1266 ppio-wins = <8>; <<
1267 bus-range = <0x0 0xff <<
1268 ranges = <0x82000000 <<
1269 msi-parent = <&its 0> <<
1270 #interrupt-cells = <1 <<
1271 interrupt-map-mask = <<
1272 interrupt-map = <0000 <<
1273 <0000 <<
1274 <0000 <<
1275 <0000 <<
1276 iommu-map = <0 &smmu <<
1277 status = "disabled"; <<
1278 }; <<
1279 <<
1280 pcie5: pcie@3800000 { <<
1281 compatible = "fsl,lx2 <<
1282 reg = <0x00 0x0380000 <<
1283 <0xa0 0x0000000 <<
1284 reg-names = "csr_axi_ <<
1285 interrupts = <GIC_SPI <<
1286 <GIC_SPI <<
1287 <GIC_SPI <<
1288 interrupt-names = "ae <<
1289 #address-cells = <3>; <<
1290 #size-cells = <2>; <<
1291 device_type = "pci"; <<
1292 dma-coherent; <<
1293 apio-wins = <256>; <<
1294 ppio-wins = <24>; <<
1295 bus-range = <0x0 0xff <<
1296 ranges = <0x82000000 <<
1297 msi-parent = <&its 0> <<
1298 #interrupt-cells = <1 <<
1299 interrupt-map-mask = <<
1300 interrupt-map = <0000 <<
1301 <0000 <<
1302 <0000 <<
1303 <0000 <<
1304 iommu-map = <0 &smmu <<
1305 status = "disabled"; <<
1306 }; <<
1307 <<
1308 pcie6: pcie@3900000 { <<
1309 compatible = "fsl,lx2 <<
1310 reg = <0x00 0x0390000 <<
1311 <0xa8 0x0000000 <<
1312 reg-names = "csr_axi_ <<
1313 interrupts = <GIC_SPI <<
1314 <GIC_SPI <<
1315 <GIC_SPI <<
1316 interrupt-names = "ae <<
1317 #address-cells = <3>; <<
1318 #size-cells = <2>; <<
1319 device_type = "pci"; <<
1320 dma-coherent; <<
1321 apio-wins = <8>; <<
1322 ppio-wins = <8>; <<
1323 bus-range = <0x0 0xff <<
1324 ranges = <0x82000000 <<
1325 msi-parent = <&its 0> <<
1326 #interrupt-cells = <1 <<
1327 interrupt-map-mask = <<
1328 interrupt-map = <0000 <<
1329 <0000 <<
1330 <0000 <<
1331 <0000 <<
1332 iommu-map = <0 &smmu <<
1333 status = "disabled"; <<
1334 }; <<
1335 <<
1336 smmu: iommu@5000000 { 690 smmu: iommu@5000000 {
1337 compatible = "arm,mmu 691 compatible = "arm,mmu-500";
1338 reg = <0 0x5000000 0 692 reg = <0 0x5000000 0 0x800000>;
1339 #iommu-cells = <1>; 693 #iommu-cells = <1>;
1340 #global-interrupts = 694 #global-interrupts = <14>;
1341 // globa 695 // global secure fault
1342 interrupts = <GIC_SPI 696 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1343 // combi 697 // combined secure
1344 <GIC_SPI 698 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1345 // globa 699 // global non-secure fault
1346 <GIC_SPI 700 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1347 // combi 701 // combined non-secure
1348 <GIC_SPI 702 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1349 // perfo 703 // performance counter interrupts 0-9
1350 <GIC_SPI 704 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 705 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 706 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 707 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 708 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 709 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 710 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 711 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 712 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 713 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1360 // per c 714 // per context interrupt, 64 interrupts
1361 <GIC_SPI 715 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 716 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 717 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 718 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 719 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 720 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 721 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 722 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 723 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 724 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 725 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 726 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 727 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 728 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 729 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 730 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 731 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 732 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 733 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 734 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 735 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 736 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 737 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 738 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 739 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 740 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 741 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 742 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 743 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 744 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 745 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 746 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 747 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 748 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 749 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 750 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 751 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 752 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 753 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 754 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 755 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 756 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 757 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 758 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 759 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 760 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 761 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 762 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 763 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 764 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 765 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 766 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 767 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 768 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 769 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 770 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 771 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 772 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 773 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 774 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 775 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 776 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 777 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 778 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1425 dma-coherent; 779 dma-coherent;
1426 }; 780 };
1427 781
1428 console@8340020 { <<
1429 compatible = "fsl,dpa <<
1430 reg = <0x00000000 0x0 <<
1431 }; <<
1432 <<
1433 ptp-timer@8b95000 { <<
1434 compatible = "fsl,dpa <<
1435 reg = <0x0 0x8b95000 <<
1436 clocks = <&clockgen Q <<
1437 Q <<
1438 little-endian; <<
1439 fsl,extts-fifo; <<
1440 }; <<
1441 <<
1442 /* WRIOP0: 0x8b8_0000, E-MDIO <<
1443 emdio1: mdio@8b96000 { <<
1444 compatible = "fsl,fma <<
1445 reg = <0x0 0x8b96000 <<
1446 interrupts = <GIC_SPI <<
1447 #address-cells = <1>; <<
1448 #size-cells = <0>; <<
1449 little-endian; <<
1450 clock-frequency = <25 <<
1451 clocks = <&clockgen Q <<
1452 Q <<
1453 status = "disabled"; <<
1454 }; <<
1455 <<
1456 emdio2: mdio@8b97000 { <<
1457 compatible = "fsl,fma <<
1458 reg = <0x0 0x8b97000 <<
1459 interrupts = <GIC_SPI <<
1460 little-endian; <<
1461 #address-cells = <1>; <<
1462 #size-cells = <0>; <<
1463 clock-frequency = <25 <<
1464 clocks = <&clockgen Q <<
1465 Q <<
1466 status = "disabled"; <<
1467 }; <<
1468 <<
1469 pcs_mdio1: mdio@8c07000 { <<
1470 compatible = "fsl,fma <<
1471 reg = <0x0 0x8c07000 <<
1472 little-endian; <<
1473 #address-cells = <1>; <<
1474 #size-cells = <0>; <<
1475 status = "disabled"; <<
1476 <<
1477 pcs1: ethernet-phy@0 <<
1478 reg = <0>; <<
1479 }; <<
1480 }; <<
1481 <<
1482 pcs_mdio2: mdio@8c0b000 { <<
1483 compatible = "fsl,fma <<
1484 reg = <0x0 0x8c0b000 <<
1485 little-endian; <<
1486 #address-cells = <1>; <<
1487 #size-cells = <0>; <<
1488 status = "disabled"; <<
1489 <<
1490 pcs2: ethernet-phy@0 <<
1491 reg = <0>; <<
1492 }; <<
1493 }; <<
1494 <<
1495 pcs_mdio3: mdio@8c0f000 { <<
1496 compatible = "fsl,fma <<
1497 reg = <0x0 0x8c0f000 <<
1498 little-endian; <<
1499 #address-cells = <1>; <<
1500 #size-cells = <0>; <<
1501 status = "disabled"; <<
1502 <<
1503 pcs3: ethernet-phy@0 <<
1504 reg = <0>; <<
1505 }; <<
1506 }; <<
1507 <<
1508 pcs_mdio4: mdio@8c13000 { <<
1509 compatible = "fsl,fma <<
1510 reg = <0x0 0x8c13000 <<
1511 little-endian; <<
1512 #address-cells = <1>; <<
1513 #size-cells = <0>; <<
1514 status = "disabled"; <<
1515 <<
1516 pcs4: ethernet-phy@0 <<
1517 reg = <0>; <<
1518 }; <<
1519 }; <<
1520 <<
1521 pcs_mdio5: mdio@8c17000 { <<
1522 compatible = "fsl,fma <<
1523 reg = <0x0 0x8c17000 <<
1524 little-endian; <<
1525 #address-cells = <1>; <<
1526 #size-cells = <0>; <<
1527 status = "disabled"; <<
1528 <<
1529 pcs5: ethernet-phy@0 <<
1530 reg = <0>; <<
1531 }; <<
1532 }; <<
1533 <<
1534 pcs_mdio6: mdio@8c1b000 { <<
1535 compatible = "fsl,fma <<
1536 reg = <0x0 0x8c1b000 <<
1537 little-endian; <<
1538 #address-cells = <1>; <<
1539 #size-cells = <0>; <<
1540 status = "disabled"; <<
1541 <<
1542 pcs6: ethernet-phy@0 <<
1543 reg = <0>; <<
1544 }; <<
1545 }; <<
1546 <<
1547 pcs_mdio7: mdio@8c1f000 { <<
1548 compatible = "fsl,fma <<
1549 reg = <0x0 0x8c1f000 <<
1550 little-endian; <<
1551 #address-cells = <1>; <<
1552 #size-cells = <0>; <<
1553 status = "disabled"; <<
1554 <<
1555 pcs7: ethernet-phy@0 <<
1556 reg = <0>; <<
1557 }; <<
1558 }; <<
1559 <<
1560 pcs_mdio8: mdio@8c23000 { <<
1561 compatible = "fsl,fma <<
1562 reg = <0x0 0x8c23000 <<
1563 little-endian; <<
1564 #address-cells = <1>; <<
1565 #size-cells = <0>; <<
1566 status = "disabled"; <<
1567 <<
1568 pcs8: ethernet-phy@0 <<
1569 reg = <0>; <<
1570 }; <<
1571 }; <<
1572 <<
1573 pcs_mdio9: mdio@8c27000 { <<
1574 compatible = "fsl,fma <<
1575 reg = <0x0 0x8c27000 <<
1576 little-endian; <<
1577 #address-cells = <1>; <<
1578 #size-cells = <0>; <<
1579 status = "disabled"; <<
1580 <<
1581 pcs9: ethernet-phy@0 <<
1582 reg = <0>; <<
1583 }; <<
1584 }; <<
1585 <<
1586 pcs_mdio10: mdio@8c2b000 { <<
1587 compatible = "fsl,fma <<
1588 reg = <0x0 0x8c2b000 <<
1589 little-endian; <<
1590 #address-cells = <1>; <<
1591 #size-cells = <0>; <<
1592 status = "disabled"; <<
1593 <<
1594 pcs10: ethernet-phy@0 <<
1595 reg = <0>; <<
1596 }; <<
1597 }; <<
1598 <<
1599 pcs_mdio11: mdio@8c2f000 { <<
1600 compatible = "fsl,fma <<
1601 reg = <0x0 0x8c2f000 <<
1602 little-endian; <<
1603 #address-cells = <1>; <<
1604 #size-cells = <0>; <<
1605 status = "disabled"; <<
1606 <<
1607 pcs11: ethernet-phy@0 <<
1608 reg = <0>; <<
1609 }; <<
1610 }; <<
1611 <<
1612 pcs_mdio12: mdio@8c33000 { <<
1613 compatible = "fsl,fma <<
1614 reg = <0x0 0x8c33000 <<
1615 little-endian; <<
1616 #address-cells = <1>; <<
1617 #size-cells = <0>; <<
1618 status = "disabled"; <<
1619 <<
1620 pcs12: ethernet-phy@0 <<
1621 reg = <0>; <<
1622 }; <<
1623 }; <<
1624 <<
1625 pcs_mdio13: mdio@8c37000 { <<
1626 compatible = "fsl,fma <<
1627 reg = <0x0 0x8c37000 <<
1628 little-endian; <<
1629 #address-cells = <1>; <<
1630 #size-cells = <0>; <<
1631 status = "disabled"; <<
1632 <<
1633 pcs13: ethernet-phy@0 <<
1634 reg = <0>; <<
1635 }; <<
1636 }; <<
1637 <<
1638 pcs_mdio14: mdio@8c3b000 { <<
1639 compatible = "fsl,fma <<
1640 reg = <0x0 0x8c3b000 <<
1641 little-endian; <<
1642 #address-cells = <1>; <<
1643 #size-cells = <0>; <<
1644 status = "disabled"; <<
1645 <<
1646 pcs14: ethernet-phy@0 <<
1647 reg = <0>; <<
1648 }; <<
1649 }; <<
1650 <<
1651 pcs_mdio15: mdio@8c3f000 { <<
1652 compatible = "fsl,fma <<
1653 reg = <0x0 0x8c3f000 <<
1654 little-endian; <<
1655 #address-cells = <1>; <<
1656 #size-cells = <0>; <<
1657 status = "disabled"; <<
1658 <<
1659 pcs15: ethernet-phy@0 <<
1660 reg = <0>; <<
1661 }; <<
1662 }; <<
1663 <<
1664 pcs_mdio16: mdio@8c43000 { <<
1665 compatible = "fsl,fma <<
1666 reg = <0x0 0x8c43000 <<
1667 little-endian; <<
1668 #address-cells = <1>; <<
1669 #size-cells = <0>; <<
1670 status = "disabled"; <<
1671 <<
1672 pcs16: ethernet-phy@0 <<
1673 reg = <0>; <<
1674 }; <<
1675 }; <<
1676 <<
1677 pcs_mdio17: mdio@8c47000 { <<
1678 compatible = "fsl,fma <<
1679 reg = <0x0 0x8c47000 <<
1680 little-endian; <<
1681 #address-cells = <1>; <<
1682 #size-cells = <0>; <<
1683 status = "disabled"; <<
1684 <<
1685 pcs17: ethernet-phy@0 <<
1686 reg = <0>; <<
1687 }; <<
1688 }; <<
1689 <<
1690 pcs_mdio18: mdio@8c4b000 { <<
1691 compatible = "fsl,fma <<
1692 reg = <0x0 0x8c4b000 <<
1693 little-endian; <<
1694 #address-cells = <1>; <<
1695 #size-cells = <0>; <<
1696 status = "disabled"; <<
1697 <<
1698 pcs18: ethernet-phy@0 <<
1699 reg = <0>; <<
1700 }; <<
1701 }; <<
1702 <<
1703 pinmux_i2crv: pinmux@70010012 <<
1704 compatible = "pinctrl <<
1705 reg = <0x00000007 0x0 <<
1706 #address-cells = <1>; <<
1707 #size-cells = <0>; <<
1708 pinctrl-single,bit-pe <<
1709 pinctrl-single,regist <<
1710 pinctrl-single,functi <<
1711 <<
1712 i2c1_scl: i2c1-scl-pi <<
1713 pinctrl-singl <<
1714 }; <<
1715 <<
1716 i2c1_scl_gpio: i2c1-s <<
1717 pinctrl-singl <<
1718 }; <<
1719 <<
1720 i2c2_scl: i2c2-scl-pi <<
1721 pinctrl-singl <<
1722 }; <<
1723 <<
1724 i2c2_scl_gpio: i2c2-s <<
1725 pinctrl-singl <<
1726 }; <<
1727 <<
1728 i2c3_scl: i2c3-scl-pi <<
1729 pinctrl-singl <<
1730 }; <<
1731 <<
1732 i2c3_scl_gpio: i2c3-s <<
1733 pinctrl-singl <<
1734 }; <<
1735 <<
1736 i2c4_scl: i2c4-scl-pi <<
1737 pinctrl-singl <<
1738 }; <<
1739 <<
1740 i2c4_scl_gpio: i2c4-s <<
1741 pinctrl-singl <<
1742 }; <<
1743 <<
1744 i2c5_scl: i2c5-scl-pi <<
1745 pinctrl-singl <<
1746 }; <<
1747 <<
1748 i2c5_scl_gpio: i2c5-s <<
1749 pinctrl-singl <<
1750 }; <<
1751 <<
1752 i2c6_scl: i2c6-scl-pi <<
1753 pinctrl-singl <<
1754 }; <<
1755 <<
1756 i2c6_scl_gpio: i2c6-s <<
1757 pinctrl-singl <<
1758 }; <<
1759 <<
1760 i2c7_scl: i2c7-scl-pi <<
1761 pinctrl-singl <<
1762 }; <<
1763 <<
1764 i2c7_scl_gpio: i2c7-s <<
1765 pinctrl-singl <<
1766 }; <<
1767 <<
1768 i2c0_scl: i2c0-scl-pi <<
1769 pinctrl-singl <<
1770 }; <<
1771 <<
1772 i2c0_scl_gpio: i2c0-s <<
1773 pinctrl-singl <<
1774 }; <<
1775 }; <<
1776 <<
1777 fsl_mc: fsl-mc@80c000000 { 782 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qor 783 compatible = "fsl,qoriq-mc";
1779 reg = <0x00000008 0x0 784 reg = <0x00000008 0x0c000000 0 0x40>,
1780 <0x00000000 0x0 785 <0x00000000 0x08340000 0 0x40000>;
1781 msi-parent = <&its 0> !! 786 msi-parent = <&its>;
1782 /* iommu-map property 787 /* iommu-map property is fixed up by u-boot */
1783 iommu-map = <0 &smmu 788 iommu-map = <0 &smmu 0 0>;
1784 dma-coherent; 789 dma-coherent;
1785 #address-cells = <3>; 790 #address-cells = <3>;
1786 #size-cells = <1>; 791 #size-cells = <1>;
1787 792
1788 /* 793 /*
1789 * Region type 0x0 - 794 * Region type 0x0 - MC portals
1790 * Region type 0x1 - 795 * Region type 0x1 - QBMAN portals
1791 */ 796 */
1792 ranges = <0x0 0x0 0x0 797 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1793 0x1 0x0 0x0 798 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1794 799
1795 /* 800 /*
1796 * Define the maximum 801 * Define the maximum number of MACs present on the SoC.
1797 */ 802 */
1798 dpmacs { 803 dpmacs {
1799 #address-cell 804 #address-cells = <1>;
1800 #size-cells = 805 #size-cells = <0>;
1801 806
1802 dpmac1: ether !! 807 dpmac1: dpmac@1 {
1803 compa 808 compatible = "fsl,qoriq-mc-dpmac";
1804 reg = 809 reg = <0x1>;
1805 pcs-h <<
1806 }; 810 };
1807 811
1808 dpmac2: ether !! 812 dpmac2: dpmac@2 {
1809 compa 813 compatible = "fsl,qoriq-mc-dpmac";
1810 reg = 814 reg = <0x2>;
1811 pcs-h <<
1812 }; 815 };
1813 816
1814 dpmac3: ether !! 817 dpmac3: dpmac@3 {
1815 compa 818 compatible = "fsl,qoriq-mc-dpmac";
1816 reg = 819 reg = <0x3>;
1817 pcs-h <<
1818 }; 820 };
1819 821
1820 dpmac4: ether !! 822 dpmac4: dpmac@4 {
1821 compa 823 compatible = "fsl,qoriq-mc-dpmac";
1822 reg = 824 reg = <0x4>;
1823 pcs-h <<
1824 }; 825 };
1825 826
1826 dpmac5: ether !! 827 dpmac5: dpmac@5 {
1827 compa 828 compatible = "fsl,qoriq-mc-dpmac";
1828 reg = 829 reg = <0x5>;
1829 pcs-h <<
1830 }; 830 };
1831 831
1832 dpmac6: ether !! 832 dpmac6: dpmac@6 {
1833 compa 833 compatible = "fsl,qoriq-mc-dpmac";
1834 reg = 834 reg = <0x6>;
1835 pcs-h <<
1836 }; 835 };
1837 836
1838 dpmac7: ether !! 837 dpmac7: dpmac@7 {
1839 compa 838 compatible = "fsl,qoriq-mc-dpmac";
1840 reg = 839 reg = <0x7>;
1841 pcs-h <<
1842 }; 840 };
1843 841
1844 dpmac8: ether !! 842 dpmac8: dpmac@8 {
1845 compa 843 compatible = "fsl,qoriq-mc-dpmac";
1846 reg = 844 reg = <0x8>;
1847 pcs-h <<
1848 }; 845 };
1849 846
1850 dpmac9: ether !! 847 dpmac9: dpmac@9 {
1851 compa 848 compatible = "fsl,qoriq-mc-dpmac";
1852 reg = 849 reg = <0x9>;
1853 pcs-h <<
1854 }; 850 };
1855 851
1856 dpmac10: ethe !! 852 dpmac10: dpmac@a {
1857 compa 853 compatible = "fsl,qoriq-mc-dpmac";
1858 reg = 854 reg = <0xa>;
1859 pcs-h <<
1860 }; 855 };
1861 856
1862 dpmac11: ethe !! 857 dpmac11: dpmac@b {
1863 compa 858 compatible = "fsl,qoriq-mc-dpmac";
1864 reg = 859 reg = <0xb>;
1865 pcs-h <<
1866 }; 860 };
1867 861
1868 dpmac12: ethe !! 862 dpmac12: dpmac@c {
1869 compa 863 compatible = "fsl,qoriq-mc-dpmac";
1870 reg = 864 reg = <0xc>;
1871 pcs-h <<
1872 }; 865 };
1873 866
1874 dpmac13: ethe !! 867 dpmac13: dpmac@d {
1875 compa 868 compatible = "fsl,qoriq-mc-dpmac";
1876 reg = 869 reg = <0xd>;
1877 pcs-h <<
1878 }; 870 };
1879 871
1880 dpmac14: ethe !! 872 dpmac14: dpmac@e {
1881 compa 873 compatible = "fsl,qoriq-mc-dpmac";
1882 reg = 874 reg = <0xe>;
1883 pcs-h <<
1884 }; 875 };
1885 876
1886 dpmac15: ethe !! 877 dpmac15: dpmac@f {
1887 compa 878 compatible = "fsl,qoriq-mc-dpmac";
1888 reg = 879 reg = <0xf>;
1889 pcs-h <<
1890 }; 880 };
1891 881
1892 dpmac16: ethe !! 882 dpmac16: dpmac@10 {
1893 compa 883 compatible = "fsl,qoriq-mc-dpmac";
1894 reg = 884 reg = <0x10>;
1895 pcs-h <<
1896 }; 885 };
1897 886
1898 dpmac17: ethe !! 887 dpmac17: dpmac@11 {
1899 compa 888 compatible = "fsl,qoriq-mc-dpmac";
1900 reg = 889 reg = <0x11>;
1901 pcs-h <<
1902 }; 890 };
1903 891
1904 dpmac18: ethe !! 892 dpmac18: dpmac@12 {
1905 compa 893 compatible = "fsl,qoriq-mc-dpmac";
1906 reg = 894 reg = <0x12>;
1907 pcs-h <<
1908 }; 895 };
1909 }; 896 };
1910 }; <<
1911 }; <<
1912 <<
1913 firmware { <<
1914 optee: optee { <<
1915 compatible = "linaro, <<
1916 method = "smc"; <<
1917 status = "disabled"; <<
1918 }; 897 };
1919 }; 898 };
1920 }; 899 };
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