1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree Include file for Layerscape-LX2 3 // Device Tree Include file for Layerscape-LX2160A family SoC.
4 // 4 //
5 // Copyright 2018-2020 NXP !! 5 // Copyright 2018 NXP
6 6
7 #include <dt-bindings/clock/fsl,qoriq-clockgen <<
8 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 8 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h> 9 #include <dt-bindings/thermal/thermal.h>
11 10
12 /memreserve/ 0x80000000 0x00010000; 11 /memreserve/ 0x80000000 0x00010000;
13 12
14 / { 13 / {
15 compatible = "fsl,lx2160a"; 14 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
17 #address-cells = <2>; 16 #address-cells = <2>;
18 #size-cells = <2>; 17 #size-cells = <2>;
19 18
20 aliases { <<
21 rtc1 = &ftm_alarm0; <<
22 }; <<
23 <<
24 cpus { 19 cpus {
25 #address-cells = <1>; 20 #address-cells = <1>;
26 #size-cells = <0>; 21 #size-cells = <0>;
27 22
28 // 8 clusters having 2 Cortex- 23 // 8 clusters having 2 Cortex-A72 cores each
29 cpu0: cpu@0 { 24 cpu0: cpu@0 {
30 device_type = "cpu"; 25 device_type = "cpu";
31 compatible = "arm,cort 26 compatible = "arm,cortex-a72";
32 enable-method = "psci" 27 enable-method = "psci";
33 reg = <0x0>; 28 reg = <0x0>;
34 clocks = <&clockgen QO !! 29 clocks = <&clockgen 1 0>;
35 d-cache-size = <0x8000 30 d-cache-size = <0x8000>;
36 d-cache-line-size = <6 31 d-cache-line-size = <64>;
37 d-cache-sets = <128>; 32 d-cache-sets = <128>;
38 i-cache-size = <0xC000 33 i-cache-size = <0xC000>;
39 i-cache-line-size = <6 34 i-cache-line-size = <64>;
40 i-cache-sets = <192>; 35 i-cache-sets = <192>;
41 next-level-cache = <&c 36 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cp 37 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>; 38 #cooling-cells = <2>;
44 }; 39 };
45 40
46 cpu1: cpu@1 { 41 cpu1: cpu@1 {
47 device_type = "cpu"; 42 device_type = "cpu";
48 compatible = "arm,cort 43 compatible = "arm,cortex-a72";
49 enable-method = "psci" 44 enable-method = "psci";
50 reg = <0x1>; 45 reg = <0x1>;
51 clocks = <&clockgen QO !! 46 clocks = <&clockgen 1 0>;
52 d-cache-size = <0x8000 47 d-cache-size = <0x8000>;
53 d-cache-line-size = <6 48 d-cache-line-size = <64>;
54 d-cache-sets = <128>; 49 d-cache-sets = <128>;
55 i-cache-size = <0xC000 50 i-cache-size = <0xC000>;
56 i-cache-line-size = <6 51 i-cache-line-size = <64>;
57 i-cache-sets = <192>; 52 i-cache-sets = <192>;
58 next-level-cache = <&c 53 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cp 54 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>; 55 #cooling-cells = <2>;
61 }; 56 };
62 57
63 cpu100: cpu@100 { 58 cpu100: cpu@100 {
64 device_type = "cpu"; 59 device_type = "cpu";
65 compatible = "arm,cort 60 compatible = "arm,cortex-a72";
66 enable-method = "psci" 61 enable-method = "psci";
67 reg = <0x100>; 62 reg = <0x100>;
68 clocks = <&clockgen QO !! 63 clocks = <&clockgen 1 1>;
69 d-cache-size = <0x8000 64 d-cache-size = <0x8000>;
70 d-cache-line-size = <6 65 d-cache-line-size = <64>;
71 d-cache-sets = <128>; 66 d-cache-sets = <128>;
72 i-cache-size = <0xC000 67 i-cache-size = <0xC000>;
73 i-cache-line-size = <6 68 i-cache-line-size = <64>;
74 i-cache-sets = <192>; 69 i-cache-sets = <192>;
75 next-level-cache = <&c 70 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cp 71 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>; 72 #cooling-cells = <2>;
78 }; 73 };
79 74
80 cpu101: cpu@101 { 75 cpu101: cpu@101 {
81 device_type = "cpu"; 76 device_type = "cpu";
82 compatible = "arm,cort 77 compatible = "arm,cortex-a72";
83 enable-method = "psci" 78 enable-method = "psci";
84 reg = <0x101>; 79 reg = <0x101>;
85 clocks = <&clockgen QO !! 80 clocks = <&clockgen 1 1>;
86 d-cache-size = <0x8000 81 d-cache-size = <0x8000>;
87 d-cache-line-size = <6 82 d-cache-line-size = <64>;
88 d-cache-sets = <128>; 83 d-cache-sets = <128>;
89 i-cache-size = <0xC000 84 i-cache-size = <0xC000>;
90 i-cache-line-size = <6 85 i-cache-line-size = <64>;
91 i-cache-sets = <192>; 86 i-cache-sets = <192>;
92 next-level-cache = <&c 87 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cp 88 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>; 89 #cooling-cells = <2>;
95 }; 90 };
96 91
97 cpu200: cpu@200 { 92 cpu200: cpu@200 {
98 device_type = "cpu"; 93 device_type = "cpu";
99 compatible = "arm,cort 94 compatible = "arm,cortex-a72";
100 enable-method = "psci" 95 enable-method = "psci";
101 reg = <0x200>; 96 reg = <0x200>;
102 clocks = <&clockgen QO !! 97 clocks = <&clockgen 1 2>;
103 d-cache-size = <0x8000 98 d-cache-size = <0x8000>;
104 d-cache-line-size = <6 99 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 100 d-cache-sets = <128>;
106 i-cache-size = <0xC000 101 i-cache-size = <0xC000>;
107 i-cache-line-size = <6 102 i-cache-line-size = <64>;
108 i-cache-sets = <192>; 103 i-cache-sets = <192>;
109 next-level-cache = <&c 104 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cp 105 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>; 106 #cooling-cells = <2>;
112 }; 107 };
113 108
114 cpu201: cpu@201 { 109 cpu201: cpu@201 {
115 device_type = "cpu"; 110 device_type = "cpu";
116 compatible = "arm,cort 111 compatible = "arm,cortex-a72";
117 enable-method = "psci" 112 enable-method = "psci";
118 reg = <0x201>; 113 reg = <0x201>;
119 clocks = <&clockgen QO !! 114 clocks = <&clockgen 1 2>;
120 d-cache-size = <0x8000 115 d-cache-size = <0x8000>;
121 d-cache-line-size = <6 116 d-cache-line-size = <64>;
122 d-cache-sets = <128>; 117 d-cache-sets = <128>;
123 i-cache-size = <0xC000 118 i-cache-size = <0xC000>;
124 i-cache-line-size = <6 119 i-cache-line-size = <64>;
125 i-cache-sets = <192>; 120 i-cache-sets = <192>;
126 next-level-cache = <&c 121 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cp 122 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>; 123 #cooling-cells = <2>;
129 }; 124 };
130 125
131 cpu300: cpu@300 { 126 cpu300: cpu@300 {
132 device_type = "cpu"; 127 device_type = "cpu";
133 compatible = "arm,cort 128 compatible = "arm,cortex-a72";
134 enable-method = "psci" 129 enable-method = "psci";
135 reg = <0x300>; 130 reg = <0x300>;
136 clocks = <&clockgen QO !! 131 clocks = <&clockgen 1 3>;
137 d-cache-size = <0x8000 132 d-cache-size = <0x8000>;
138 d-cache-line-size = <6 133 d-cache-line-size = <64>;
139 d-cache-sets = <128>; 134 d-cache-sets = <128>;
140 i-cache-size = <0xC000 135 i-cache-size = <0xC000>;
141 i-cache-line-size = <6 136 i-cache-line-size = <64>;
142 i-cache-sets = <192>; 137 i-cache-sets = <192>;
143 next-level-cache = <&c 138 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cp 139 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>; 140 #cooling-cells = <2>;
146 }; 141 };
147 142
148 cpu301: cpu@301 { 143 cpu301: cpu@301 {
149 device_type = "cpu"; 144 device_type = "cpu";
150 compatible = "arm,cort 145 compatible = "arm,cortex-a72";
151 enable-method = "psci" 146 enable-method = "psci";
152 reg = <0x301>; 147 reg = <0x301>;
153 clocks = <&clockgen QO !! 148 clocks = <&clockgen 1 3>;
154 d-cache-size = <0x8000 149 d-cache-size = <0x8000>;
155 d-cache-line-size = <6 150 d-cache-line-size = <64>;
156 d-cache-sets = <128>; 151 d-cache-sets = <128>;
157 i-cache-size = <0xC000 152 i-cache-size = <0xC000>;
158 i-cache-line-size = <6 153 i-cache-line-size = <64>;
159 i-cache-sets = <192>; 154 i-cache-sets = <192>;
160 next-level-cache = <&c 155 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cp 156 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>; 157 #cooling-cells = <2>;
163 }; 158 };
164 159
165 cpu400: cpu@400 { 160 cpu400: cpu@400 {
166 device_type = "cpu"; 161 device_type = "cpu";
167 compatible = "arm,cort 162 compatible = "arm,cortex-a72";
168 enable-method = "psci" 163 enable-method = "psci";
169 reg = <0x400>; 164 reg = <0x400>;
170 clocks = <&clockgen QO !! 165 clocks = <&clockgen 1 4>;
171 d-cache-size = <0x8000 166 d-cache-size = <0x8000>;
172 d-cache-line-size = <6 167 d-cache-line-size = <64>;
173 d-cache-sets = <128>; 168 d-cache-sets = <128>;
174 i-cache-size = <0xC000 169 i-cache-size = <0xC000>;
175 i-cache-line-size = <6 170 i-cache-line-size = <64>;
176 i-cache-sets = <192>; 171 i-cache-sets = <192>;
177 next-level-cache = <&c 172 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cp 173 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>; 174 #cooling-cells = <2>;
180 }; 175 };
181 176
182 cpu401: cpu@401 { 177 cpu401: cpu@401 {
183 device_type = "cpu"; 178 device_type = "cpu";
184 compatible = "arm,cort 179 compatible = "arm,cortex-a72";
185 enable-method = "psci" 180 enable-method = "psci";
186 reg = <0x401>; 181 reg = <0x401>;
187 clocks = <&clockgen QO !! 182 clocks = <&clockgen 1 4>;
188 d-cache-size = <0x8000 183 d-cache-size = <0x8000>;
189 d-cache-line-size = <6 184 d-cache-line-size = <64>;
190 d-cache-sets = <128>; 185 d-cache-sets = <128>;
191 i-cache-size = <0xC000 186 i-cache-size = <0xC000>;
192 i-cache-line-size = <6 187 i-cache-line-size = <64>;
193 i-cache-sets = <192>; 188 i-cache-sets = <192>;
194 next-level-cache = <&c 189 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cp 190 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>; 191 #cooling-cells = <2>;
197 }; 192 };
198 193
199 cpu500: cpu@500 { 194 cpu500: cpu@500 {
200 device_type = "cpu"; 195 device_type = "cpu";
201 compatible = "arm,cort 196 compatible = "arm,cortex-a72";
202 enable-method = "psci" 197 enable-method = "psci";
203 reg = <0x500>; 198 reg = <0x500>;
204 clocks = <&clockgen QO !! 199 clocks = <&clockgen 1 5>;
205 d-cache-size = <0x8000 200 d-cache-size = <0x8000>;
206 d-cache-line-size = <6 201 d-cache-line-size = <64>;
207 d-cache-sets = <128>; 202 d-cache-sets = <128>;
208 i-cache-size = <0xC000 203 i-cache-size = <0xC000>;
209 i-cache-line-size = <6 204 i-cache-line-size = <64>;
210 i-cache-sets = <192>; 205 i-cache-sets = <192>;
211 next-level-cache = <&c 206 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cp 207 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>; 208 #cooling-cells = <2>;
214 }; 209 };
215 210
216 cpu501: cpu@501 { 211 cpu501: cpu@501 {
217 device_type = "cpu"; 212 device_type = "cpu";
218 compatible = "arm,cort 213 compatible = "arm,cortex-a72";
219 enable-method = "psci" 214 enable-method = "psci";
220 reg = <0x501>; 215 reg = <0x501>;
221 clocks = <&clockgen QO !! 216 clocks = <&clockgen 1 5>;
222 d-cache-size = <0x8000 217 d-cache-size = <0x8000>;
223 d-cache-line-size = <6 218 d-cache-line-size = <64>;
224 d-cache-sets = <128>; 219 d-cache-sets = <128>;
225 i-cache-size = <0xC000 220 i-cache-size = <0xC000>;
226 i-cache-line-size = <6 221 i-cache-line-size = <64>;
227 i-cache-sets = <192>; 222 i-cache-sets = <192>;
228 next-level-cache = <&c 223 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cp 224 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>; 225 #cooling-cells = <2>;
231 }; 226 };
232 227
233 cpu600: cpu@600 { 228 cpu600: cpu@600 {
234 device_type = "cpu"; 229 device_type = "cpu";
235 compatible = "arm,cort 230 compatible = "arm,cortex-a72";
236 enable-method = "psci" 231 enable-method = "psci";
237 reg = <0x600>; 232 reg = <0x600>;
238 clocks = <&clockgen QO !! 233 clocks = <&clockgen 1 6>;
239 d-cache-size = <0x8000 234 d-cache-size = <0x8000>;
240 d-cache-line-size = <6 235 d-cache-line-size = <64>;
241 d-cache-sets = <128>; 236 d-cache-sets = <128>;
242 i-cache-size = <0xC000 237 i-cache-size = <0xC000>;
243 i-cache-line-size = <6 238 i-cache-line-size = <64>;
244 i-cache-sets = <192>; 239 i-cache-sets = <192>;
245 next-level-cache = <&c 240 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cp 241 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>; 242 #cooling-cells = <2>;
248 }; 243 };
249 244
250 cpu601: cpu@601 { 245 cpu601: cpu@601 {
251 device_type = "cpu"; 246 device_type = "cpu";
252 compatible = "arm,cort 247 compatible = "arm,cortex-a72";
253 enable-method = "psci" 248 enable-method = "psci";
254 reg = <0x601>; 249 reg = <0x601>;
255 clocks = <&clockgen QO !! 250 clocks = <&clockgen 1 6>;
256 d-cache-size = <0x8000 251 d-cache-size = <0x8000>;
257 d-cache-line-size = <6 252 d-cache-line-size = <64>;
258 d-cache-sets = <128>; 253 d-cache-sets = <128>;
259 i-cache-size = <0xC000 254 i-cache-size = <0xC000>;
260 i-cache-line-size = <6 255 i-cache-line-size = <64>;
261 i-cache-sets = <192>; 256 i-cache-sets = <192>;
262 next-level-cache = <&c 257 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cp 258 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>; 259 #cooling-cells = <2>;
265 }; 260 };
266 261
267 cpu700: cpu@700 { 262 cpu700: cpu@700 {
268 device_type = "cpu"; 263 device_type = "cpu";
269 compatible = "arm,cort 264 compatible = "arm,cortex-a72";
270 enable-method = "psci" 265 enable-method = "psci";
271 reg = <0x700>; 266 reg = <0x700>;
272 clocks = <&clockgen QO !! 267 clocks = <&clockgen 1 7>;
273 d-cache-size = <0x8000 268 d-cache-size = <0x8000>;
274 d-cache-line-size = <6 269 d-cache-line-size = <64>;
275 d-cache-sets = <128>; 270 d-cache-sets = <128>;
276 i-cache-size = <0xC000 271 i-cache-size = <0xC000>;
277 i-cache-line-size = <6 272 i-cache-line-size = <64>;
278 i-cache-sets = <192>; 273 i-cache-sets = <192>;
279 next-level-cache = <&c 274 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cp 275 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>; 276 #cooling-cells = <2>;
282 }; 277 };
283 278
284 cpu701: cpu@701 { 279 cpu701: cpu@701 {
285 device_type = "cpu"; 280 device_type = "cpu";
286 compatible = "arm,cort 281 compatible = "arm,cortex-a72";
287 enable-method = "psci" 282 enable-method = "psci";
288 reg = <0x701>; 283 reg = <0x701>;
289 clocks = <&clockgen QO !! 284 clocks = <&clockgen 1 7>;
290 d-cache-size = <0x8000 285 d-cache-size = <0x8000>;
291 d-cache-line-size = <6 286 d-cache-line-size = <64>;
292 d-cache-sets = <128>; 287 d-cache-sets = <128>;
293 i-cache-size = <0xC000 288 i-cache-size = <0xC000>;
294 i-cache-line-size = <6 289 i-cache-line-size = <64>;
295 i-cache-sets = <192>; 290 i-cache-sets = <192>;
296 next-level-cache = <&c 291 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cp 292 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>; 293 #cooling-cells = <2>;
299 }; 294 };
300 295
301 cluster0_l2: l2-cache0 { 296 cluster0_l2: l2-cache0 {
302 compatible = "cache"; 297 compatible = "cache";
303 cache-unified; <<
304 cache-size = <0x100000 298 cache-size = <0x100000>;
305 cache-line-size = <64> 299 cache-line-size = <64>;
306 cache-sets = <1024>; 300 cache-sets = <1024>;
307 cache-level = <2>; 301 cache-level = <2>;
308 }; 302 };
309 303
310 cluster1_l2: l2-cache1 { 304 cluster1_l2: l2-cache1 {
311 compatible = "cache"; 305 compatible = "cache";
312 cache-unified; <<
313 cache-size = <0x100000 306 cache-size = <0x100000>;
314 cache-line-size = <64> 307 cache-line-size = <64>;
315 cache-sets = <1024>; 308 cache-sets = <1024>;
316 cache-level = <2>; 309 cache-level = <2>;
317 }; 310 };
318 311
319 cluster2_l2: l2-cache2 { 312 cluster2_l2: l2-cache2 {
320 compatible = "cache"; 313 compatible = "cache";
321 cache-unified; <<
322 cache-size = <0x100000 314 cache-size = <0x100000>;
323 cache-line-size = <64> 315 cache-line-size = <64>;
324 cache-sets = <1024>; 316 cache-sets = <1024>;
325 cache-level = <2>; 317 cache-level = <2>;
326 }; 318 };
327 319
328 cluster3_l2: l2-cache3 { 320 cluster3_l2: l2-cache3 {
329 compatible = "cache"; 321 compatible = "cache";
330 cache-unified; <<
331 cache-size = <0x100000 322 cache-size = <0x100000>;
332 cache-line-size = <64> 323 cache-line-size = <64>;
333 cache-sets = <1024>; 324 cache-sets = <1024>;
334 cache-level = <2>; 325 cache-level = <2>;
335 }; 326 };
336 327
337 cluster4_l2: l2-cache4 { 328 cluster4_l2: l2-cache4 {
338 compatible = "cache"; 329 compatible = "cache";
339 cache-unified; <<
340 cache-size = <0x100000 330 cache-size = <0x100000>;
341 cache-line-size = <64> 331 cache-line-size = <64>;
342 cache-sets = <1024>; 332 cache-sets = <1024>;
343 cache-level = <2>; 333 cache-level = <2>;
344 }; 334 };
345 335
346 cluster5_l2: l2-cache5 { 336 cluster5_l2: l2-cache5 {
347 compatible = "cache"; 337 compatible = "cache";
348 cache-unified; <<
349 cache-size = <0x100000 338 cache-size = <0x100000>;
350 cache-line-size = <64> 339 cache-line-size = <64>;
351 cache-sets = <1024>; 340 cache-sets = <1024>;
352 cache-level = <2>; 341 cache-level = <2>;
353 }; 342 };
354 343
355 cluster6_l2: l2-cache6 { 344 cluster6_l2: l2-cache6 {
356 compatible = "cache"; 345 compatible = "cache";
357 cache-unified; <<
358 cache-size = <0x100000 346 cache-size = <0x100000>;
359 cache-line-size = <64> 347 cache-line-size = <64>;
360 cache-sets = <1024>; 348 cache-sets = <1024>;
361 cache-level = <2>; 349 cache-level = <2>;
362 }; 350 };
363 351
364 cluster7_l2: l2-cache7 { 352 cluster7_l2: l2-cache7 {
365 compatible = "cache"; 353 compatible = "cache";
366 cache-unified; <<
367 cache-size = <0x100000 354 cache-size = <0x100000>;
368 cache-line-size = <64> 355 cache-line-size = <64>;
369 cache-sets = <1024>; 356 cache-sets = <1024>;
370 cache-level = <2>; 357 cache-level = <2>;
371 }; 358 };
372 359
373 cpu_pw15: cpu-pw15 { 360 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle 361 compatible = "arm,idle-state";
375 idle-state-name = "PW1 362 idle-state-name = "PW15";
376 arm,psci-suspend-param 363 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <20 364 entry-latency-us = <2000>;
378 exit-latency-us = <200 365 exit-latency-us = <2000>;
379 min-residency-us = <60 366 min-residency-us = <6000>;
380 }; 367 };
381 }; 368 };
382 369
383 gic: interrupt-controller@6000000 { 370 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3"; 371 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x1000 372 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x20 373 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
387 374 // SGI_base)
388 <0x0 0x0c0c0000 0 0x20 375 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x10 376 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20 377 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>; 378 #interrupt-cells = <3>;
392 #address-cells = <2>; 379 #address-cells = <2>;
393 #size-cells = <2>; 380 #size-cells = <2>;
394 ranges; 381 ranges;
395 interrupt-controller; 382 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TY 383 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
397 384
398 its: msi-controller@6020000 { !! 385 its: gic-its@6020000 {
399 compatible = "arm,gic- 386 compatible = "arm,gic-v3-its";
400 msi-controller; 387 msi-controller;
401 #msi-cells = <1>; <<
402 reg = <0x0 0x6020000 0 388 reg = <0x0 0x6020000 0 0x20000>;
403 }; 389 };
404 }; 390 };
405 391
406 timer { 392 timer {
407 compatible = "arm,armv8-timer" 393 compatible = "arm,armv8-timer";
408 interrupts = <GIC_PPI 13 IRQ_T 394 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 14 IRQ_T 395 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 11 IRQ_T 396 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_PPI 10 IRQ_T 397 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
412 }; 398 };
413 399
414 pmu { 400 pmu {
415 compatible = "arm,cortex-a72-p 401 compatible = "arm,cortex-a72-pmu";
416 interrupts = <GIC_PPI 7 IRQ_TY 402 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
417 }; 403 };
418 404
419 psci { 405 psci {
420 compatible = "arm,psci-0.2"; 406 compatible = "arm,psci-0.2";
421 method = "smc"; 407 method = "smc";
422 }; 408 };
423 409
424 memory@80000000 { 410 memory@80000000 {
425 // DRAM space - 1, size : 2 GB 411 // DRAM space - 1, size : 2 GB DRAM
426 device_type = "memory"; 412 device_type = "memory";
427 reg = <0x00000000 0x80000000 0 413 reg = <0x00000000 0x80000000 0 0x80000000>;
428 }; 414 };
429 415
430 ddr1: memory-controller@1080000 { 416 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory 417 compatible = "fsl,qoriq-memory-controller";
432 reg = <0x0 0x1080000 0x0 0x100 418 reg = <0x0 0x1080000 0x0 0x1000>;
433 interrupts = <GIC_SPI 17 IRQ_T 419 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
434 little-endian; 420 little-endian;
435 }; 421 };
436 422
437 ddr2: memory-controller@1090000 { 423 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory 424 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1090000 0x0 0x100 425 reg = <0x0 0x1090000 0x0 0x1000>;
440 interrupts = <GIC_SPI 18 IRQ_T 426 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
441 little-endian; 427 little-endian;
442 }; 428 };
443 429
444 // One clock unit-sysclk node which bo 430 // One clock unit-sysclk node which bootloader require during DT fix-up
445 sysclk: sysclk { 431 sysclk: sysclk {
446 compatible = "fixed-clock"; 432 compatible = "fixed-clock";
447 #clock-cells = <0>; 433 #clock-cells = <0>;
448 clock-frequency = <100000000>; 434 clock-frequency = <100000000>; // fixed up by bootloader
449 clock-output-names = "sysclk"; 435 clock-output-names = "sysclk";
450 }; 436 };
451 437
452 thermal-zones { 438 thermal-zones {
453 cluster6-7-thermal { !! 439 cluster6-7 {
454 polling-delay-passive 440 polling-delay-passive = <1000>;
455 polling-delay = <5000> 441 polling-delay = <5000>;
456 thermal-sensors = <&tm 442 thermal-sensors = <&tmu 0>;
457 443
458 trips { 444 trips {
459 cluster6_7_ale 445 cluster6_7_alert: cluster6-7-alert {
460 temper 446 temperature = <85000>;
461 hyster 447 hysteresis = <2000>;
462 type = 448 type = "passive";
463 }; 449 };
464 450
465 cluster6_7_cri 451 cluster6_7_crit: cluster6-7-crit {
466 temper 452 temperature = <95000>;
467 hyster 453 hysteresis = <2000>;
468 type = 454 type = "critical";
469 }; 455 };
470 }; 456 };
471 457
472 cooling-maps { 458 cooling-maps {
473 map0 { 459 map0 {
474 trip = 460 trip = <&cluster6_7_alert>;
475 coolin 461 cooling-device =
476 462 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 463 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 464 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 465 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 466 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 467 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 468 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
483 469 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
484 470 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
485 471 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
486 472 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
487 473 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
488 474 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 475 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 476 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 477 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
492 }; 478 };
493 }; 479 };
494 }; 480 };
495 481
496 ddr-ctrl5-thermal { !! 482 ddr-cluster5 {
497 polling-delay-passive 483 polling-delay-passive = <1000>;
498 polling-delay = <5000> 484 polling-delay = <5000>;
499 thermal-sensors = <&tm 485 thermal-sensors = <&tmu 1>;
500 486
501 trips { 487 trips {
502 ddr-cluster5-a 488 ddr-cluster5-alert {
503 temper 489 temperature = <85000>;
504 hyster 490 hysteresis = <2000>;
505 type = 491 type = "passive";
506 }; 492 };
507 493
508 ddr-cluster5-c 494 ddr-cluster5-crit {
509 temper 495 temperature = <95000>;
510 hyster 496 hysteresis = <2000>;
511 type = 497 type = "critical";
512 }; 498 };
513 }; 499 };
514 }; 500 };
515 501
516 wriop-thermal { !! 502 wriop {
517 polling-delay-passive 503 polling-delay-passive = <1000>;
518 polling-delay = <5000> 504 polling-delay = <5000>;
519 thermal-sensors = <&tm 505 thermal-sensors = <&tmu 2>;
520 506
521 trips { 507 trips {
522 wriop-alert { 508 wriop-alert {
523 temper 509 temperature = <85000>;
524 hyster 510 hysteresis = <2000>;
525 type = 511 type = "passive";
526 }; 512 };
527 513
528 wriop-crit { 514 wriop-crit {
529 temper 515 temperature = <95000>;
530 hyster 516 hysteresis = <2000>;
531 type = 517 type = "critical";
532 }; 518 };
533 }; 519 };
534 }; 520 };
535 521
536 dce-thermal { !! 522 dce-qbman-hsio2 {
537 polling-delay-passive 523 polling-delay-passive = <1000>;
538 polling-delay = <5000> 524 polling-delay = <5000>;
539 thermal-sensors = <&tm 525 thermal-sensors = <&tmu 3>;
540 526
541 trips { 527 trips {
542 dce-qbman-aler 528 dce-qbman-alert {
543 temper 529 temperature = <85000>;
544 hyster 530 hysteresis = <2000>;
545 type = 531 type = "passive";
546 }; 532 };
547 533
548 dce-qbman-crit 534 dce-qbman-crit {
549 temper 535 temperature = <95000>;
550 hyster 536 hysteresis = <2000>;
551 type = 537 type = "critical";
552 }; 538 };
553 }; 539 };
554 }; 540 };
555 541
556 ccn-thermal { !! 542 ccn-dpaa-tbu {
557 polling-delay-passive 543 polling-delay-passive = <1000>;
558 polling-delay = <5000> 544 polling-delay = <5000>;
559 thermal-sensors = <&tm 545 thermal-sensors = <&tmu 4>;
560 546
561 trips { 547 trips {
562 ccn-dpaa-alert 548 ccn-dpaa-alert {
563 temper 549 temperature = <85000>;
564 hyster 550 hysteresis = <2000>;
565 type = 551 type = "passive";
566 }; 552 };
567 553
568 ccn-dpaa-crit 554 ccn-dpaa-crit {
569 temper 555 temperature = <95000>;
570 hyster 556 hysteresis = <2000>;
571 type = 557 type = "critical";
572 }; 558 };
573 }; 559 };
574 }; 560 };
575 561
576 cluster4-thermal { !! 562 cluster4-hsio3 {
577 polling-delay-passive 563 polling-delay-passive = <1000>;
578 polling-delay = <5000> 564 polling-delay = <5000>;
579 thermal-sensors = <&tm 565 thermal-sensors = <&tmu 5>;
580 566
581 trips { 567 trips {
582 clust4-hsio3-a 568 clust4-hsio3-alert {
583 temper 569 temperature = <85000>;
584 hyster 570 hysteresis = <2000>;
585 type = 571 type = "passive";
586 }; 572 };
587 573
588 clust4-hsio3-c 574 clust4-hsio3-crit {
589 temper 575 temperature = <95000>;
590 hyster 576 hysteresis = <2000>;
591 type = 577 type = "critical";
592 }; 578 };
593 }; 579 };
594 }; 580 };
595 581
596 cluster2-3-thermal { !! 582 cluster2-3 {
597 polling-delay-passive 583 polling-delay-passive = <1000>;
598 polling-delay = <5000> 584 polling-delay = <5000>;
599 thermal-sensors = <&tm 585 thermal-sensors = <&tmu 6>;
600 586
601 trips { 587 trips {
602 cluster2-3-ale 588 cluster2-3-alert {
603 temper 589 temperature = <85000>;
604 hyster 590 hysteresis = <2000>;
605 type = 591 type = "passive";
606 }; 592 };
607 593
608 cluster2-3-cri 594 cluster2-3-crit {
609 temper 595 temperature = <95000>;
610 hyster 596 hysteresis = <2000>;
611 type = 597 type = "critical";
612 }; 598 };
613 }; 599 };
614 }; 600 };
615 }; 601 };
616 602
617 soc { 603 soc {
618 compatible = "simple-bus"; 604 compatible = "simple-bus";
619 #address-cells = <2>; 605 #address-cells = <2>;
620 #size-cells = <2>; 606 #size-cells = <2>;
621 ranges; 607 ranges;
622 dma-ranges = <0x0 0x0 0x0 0x0 608 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
623 609
624 serdes_1: phy@1ea0000 { <<
625 compatible = "fsl,lynx <<
626 reg = <0x0 0x1ea0000 0 <<
627 #phy-cells = <1>; <<
628 }; <<
629 <<
630 serdes_2: phy@1eb0000 { <<
631 compatible = "fsl,lynx <<
632 reg = <0x0 0x1eb0000 0 <<
633 #phy-cells = <1>; <<
634 status = "disabled"; <<
635 }; <<
636 <<
637 crypto: crypto@8000000 { 610 crypto: crypto@8000000 {
638 compatible = "fsl,sec- 611 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 fsl,sec-era = <10>; 612 fsl,sec-era = <10>;
640 #address-cells = <1>; 613 #address-cells = <1>;
641 #size-cells = <1>; 614 #size-cells = <1>;
642 ranges = <0x0 0x00 0x8 615 ranges = <0x0 0x00 0x8000000 0x100000>;
643 reg = <0x00 0x8000000 616 reg = <0x00 0x8000000 0x0 0x100000>;
644 interrupts = <GIC_SPI 617 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
645 dma-coherent; 618 dma-coherent;
646 status = "disabled"; 619 status = "disabled";
647 620
648 sec_jr0: jr@10000 { 621 sec_jr0: jr@10000 {
649 compatible = " 622 compatible = "fsl,sec-v5.0-job-ring",
650 " 623 "fsl,sec-v4.0-job-ring";
651 reg = <0x10000 !! 624 reg = <0x10000 0x10000>;
652 interrupts = < 625 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
653 }; 626 };
654 627
655 sec_jr1: jr@20000 { 628 sec_jr1: jr@20000 {
656 compatible = " 629 compatible = "fsl,sec-v5.0-job-ring",
657 " 630 "fsl,sec-v4.0-job-ring";
658 reg = <0x20000 !! 631 reg = <0x20000 0x10000>;
659 interrupts = < 632 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
660 }; 633 };
661 634
662 sec_jr2: jr@30000 { 635 sec_jr2: jr@30000 {
663 compatible = " 636 compatible = "fsl,sec-v5.0-job-ring",
664 " 637 "fsl,sec-v4.0-job-ring";
665 reg = <0x30000 !! 638 reg = <0x30000 0x10000>;
666 interrupts = < 639 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
667 }; 640 };
668 641
669 sec_jr3: jr@40000 { 642 sec_jr3: jr@40000 {
670 compatible = " 643 compatible = "fsl,sec-v5.0-job-ring",
671 " 644 "fsl,sec-v4.0-job-ring";
672 reg = <0x40000 !! 645 reg = <0x40000 0x10000>;
673 interrupts = < 646 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
674 }; 647 };
675 }; 648 };
676 649
677 clockgen: clock-controller@130 650 clockgen: clock-controller@1300000 {
678 compatible = "fsl,lx21 651 compatible = "fsl,lx2160a-clockgen";
679 reg = <0 0x1300000 0 0 652 reg = <0 0x1300000 0 0xa0000>;
680 #clock-cells = <2>; 653 #clock-cells = <2>;
681 clocks = <&sysclk>; 654 clocks = <&sysclk>;
682 }; 655 };
683 656
684 dcfg: syscon@1e00000 { 657 dcfg: syscon@1e00000 {
685 compatible = "fsl,lx21 658 compatible = "fsl,lx2160a-dcfg", "syscon";
686 reg = <0x0 0x1e00000 0 659 reg = <0x0 0x1e00000 0x0 0x10000>;
687 little-endian; 660 little-endian;
688 }; 661 };
689 662
690 sfp: efuse@1e80000 { <<
691 compatible = "fsl,ls10 <<
692 reg = <0x0 0x1e80000 0 <<
693 clocks = <&clockgen QO <<
694 QO <<
695 clock-names = "sfp"; <<
696 }; <<
697 <<
698 isc: syscon@1f70000 { <<
699 compatible = "fsl,lx21 <<
700 reg = <0x0 0x1f70000 0 <<
701 little-endian; <<
702 #address-cells = <1>; <<
703 #size-cells = <1>; <<
704 ranges = <0x0 0x0 0x1f <<
705 <<
706 extirq: interrupt-cont <<
707 compatible = " <<
708 #interrupt-cel <<
709 #address-cells <<
710 interrupt-cont <<
711 reg = <0x14 4> <<
712 interrupt-map <<
713 <0 0 & <<
714 <1 0 & <<
715 <2 0 & <<
716 <3 0 & <<
717 <4 0 & <<
718 <5 0 & <<
719 <6 0 & <<
720 <7 0 & <<
721 <8 0 & <<
722 <9 0 & <<
723 <10 0 <<
724 <11 0 <<
725 interrupt-map- <<
726 }; <<
727 }; <<
728 <<
729 tmu: tmu@1f80000 { 663 tmu: tmu@1f80000 {
730 compatible = "fsl,qori 664 compatible = "fsl,qoriq-tmu";
731 reg = <0x0 0x1f80000 0 665 reg = <0x0 0x1f80000 0x0 0x10000>;
732 interrupts = <GIC_SPI 666 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
733 fsl,tmu-range = <0x800 667 fsl,tmu-range = <0x800000e6 0x8001017d>;
734 fsl,tmu-calibration = 668 fsl,tmu-calibration =
735 /* Calibration 669 /* Calibration data group 1 */
736 <0x00000000 0x !! 670 <0x00000000 0x00000035
737 /* Calibration 671 /* Calibration data group 2 */
738 <0x00000001 0x !! 672 0x00000001 0x00000154>;
739 little-endian; 673 little-endian;
740 #thermal-sensor-cells 674 #thermal-sensor-cells = <1>;
741 }; 675 };
742 676
743 i2c0: i2c@2000000 { 677 i2c0: i2c@2000000 {
744 compatible = "fsl,vf61 678 compatible = "fsl,vf610-i2c";
745 #address-cells = <1>; 679 #address-cells = <1>;
746 #size-cells = <0>; 680 #size-cells = <0>;
747 reg = <0x0 0x2000000 0 681 reg = <0x0 0x2000000 0x0 0x10000>;
748 interrupts = <GIC_SPI 682 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
749 clock-names = "ipg"; !! 683 clock-names = "i2c";
750 clocks = <&clockgen QO !! 684 clocks = <&clockgen 4 15>;
751 QO !! 685 scl-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
752 pinctrl-names = "defau <<
753 pinctrl-0 = <&i2c0_scl <<
754 pinctrl-1 = <&i2c0_scl <<
755 scl-gpios = <&gpio0 3 <<
756 status = "disabled"; 686 status = "disabled";
757 }; 687 };
758 688
759 i2c1: i2c@2010000 { 689 i2c1: i2c@2010000 {
760 compatible = "fsl,vf61 690 compatible = "fsl,vf610-i2c";
761 #address-cells = <1>; 691 #address-cells = <1>;
762 #size-cells = <0>; 692 #size-cells = <0>;
763 reg = <0x0 0x2010000 0 693 reg = <0x0 0x2010000 0x0 0x10000>;
764 interrupts = <GIC_SPI 694 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
765 clock-names = "ipg"; !! 695 clock-names = "i2c";
766 clocks = <&clockgen QO !! 696 clocks = <&clockgen 4 15>;
767 QO <<
768 pinctrl-names = "defau <<
769 pinctrl-0 = <&i2c1_scl <<
770 pinctrl-1 = <&i2c1_scl <<
771 scl-gpios = <&gpio0 31 <<
772 status = "disabled"; 697 status = "disabled";
773 }; 698 };
774 699
775 i2c2: i2c@2020000 { 700 i2c2: i2c@2020000 {
776 compatible = "fsl,vf61 701 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>; 702 #address-cells = <1>;
778 #size-cells = <0>; 703 #size-cells = <0>;
779 reg = <0x0 0x2020000 0 704 reg = <0x0 0x2020000 0x0 0x10000>;
780 interrupts = <GIC_SPI 705 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
781 clock-names = "ipg"; !! 706 clock-names = "i2c";
782 clocks = <&clockgen QO !! 707 clocks = <&clockgen 4 15>;
783 QO <<
784 pinctrl-names = "defau <<
785 pinctrl-0 = <&i2c2_scl <<
786 pinctrl-1 = <&i2c2_scl <<
787 scl-gpios = <&gpio0 29 <<
788 status = "disabled"; 708 status = "disabled";
789 }; 709 };
790 710
791 i2c3: i2c@2030000 { 711 i2c3: i2c@2030000 {
792 compatible = "fsl,vf61 712 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>; 713 #address-cells = <1>;
794 #size-cells = <0>; 714 #size-cells = <0>;
795 reg = <0x0 0x2030000 0 715 reg = <0x0 0x2030000 0x0 0x10000>;
796 interrupts = <GIC_SPI 716 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
797 clock-names = "ipg"; !! 717 clock-names = "i2c";
798 clocks = <&clockgen QO !! 718 clocks = <&clockgen 4 15>;
799 QO <<
800 pinctrl-names = "defau <<
801 pinctrl-0 = <&i2c3_scl <<
802 pinctrl-1 = <&i2c3_scl <<
803 scl-gpios = <&gpio0 27 <<
804 status = "disabled"; 719 status = "disabled";
805 }; 720 };
806 721
807 i2c4: i2c@2040000 { 722 i2c4: i2c@2040000 {
808 compatible = "fsl,vf61 723 compatible = "fsl,vf610-i2c";
809 #address-cells = <1>; 724 #address-cells = <1>;
810 #size-cells = <0>; 725 #size-cells = <0>;
811 reg = <0x0 0x2040000 0 726 reg = <0x0 0x2040000 0x0 0x10000>;
812 interrupts = <GIC_SPI 727 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
813 clock-names = "ipg"; !! 728 clock-names = "i2c";
814 clocks = <&clockgen QO !! 729 clocks = <&clockgen 4 15>;
815 QO !! 730 scl-gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>;
816 pinctrl-names = "defau <<
817 pinctrl-0 = <&i2c4_scl <<
818 pinctrl-1 = <&i2c4_scl <<
819 scl-gpios = <&gpio0 25 <<
820 status = "disabled"; 731 status = "disabled";
821 }; 732 };
822 733
823 i2c5: i2c@2050000 { 734 i2c5: i2c@2050000 {
824 compatible = "fsl,vf61 735 compatible = "fsl,vf610-i2c";
825 #address-cells = <1>; 736 #address-cells = <1>;
826 #size-cells = <0>; 737 #size-cells = <0>;
827 reg = <0x0 0x2050000 0 738 reg = <0x0 0x2050000 0x0 0x10000>;
828 interrupts = <GIC_SPI 739 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
829 clock-names = "ipg"; !! 740 clock-names = "i2c";
830 clocks = <&clockgen QO !! 741 clocks = <&clockgen 4 15>;
831 QO <<
832 pinctrl-names = "defau <<
833 pinctrl-0 = <&i2c5_scl <<
834 pinctrl-1 = <&i2c5_scl <<
835 scl-gpios = <&gpio0 23 <<
836 status = "disabled"; 742 status = "disabled";
837 }; 743 };
838 744
839 i2c6: i2c@2060000 { 745 i2c6: i2c@2060000 {
840 compatible = "fsl,vf61 746 compatible = "fsl,vf610-i2c";
841 #address-cells = <1>; 747 #address-cells = <1>;
842 #size-cells = <0>; 748 #size-cells = <0>;
843 reg = <0x0 0x2060000 0 749 reg = <0x0 0x2060000 0x0 0x10000>;
844 interrupts = <GIC_SPI 750 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "ipg"; !! 751 clock-names = "i2c";
846 clocks = <&clockgen QO !! 752 clocks = <&clockgen 4 15>;
847 QO <<
848 pinctrl-names = "defau <<
849 pinctrl-0 = <&i2c6_scl <<
850 pinctrl-1 = <&i2c6_scl <<
851 scl-gpios = <&gpio1 16 <<
852 status = "disabled"; 753 status = "disabled";
853 }; 754 };
854 755
855 i2c7: i2c@2070000 { 756 i2c7: i2c@2070000 {
856 compatible = "fsl,vf61 757 compatible = "fsl,vf610-i2c";
857 #address-cells = <1>; 758 #address-cells = <1>;
858 #size-cells = <0>; 759 #size-cells = <0>;
859 reg = <0x0 0x2070000 0 760 reg = <0x0 0x2070000 0x0 0x10000>;
860 interrupts = <GIC_SPI 761 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
861 clock-names = "ipg"; !! 762 clock-names = "i2c";
862 clocks = <&clockgen QO !! 763 clocks = <&clockgen 4 15>;
863 QO <<
864 pinctrl-names = "defau <<
865 pinctrl-0 = <&i2c7_scl <<
866 pinctrl-1 = <&i2c7_scl <<
867 scl-gpios = <&gpio1 18 <<
868 status = "disabled"; 764 status = "disabled";
869 }; 765 };
870 766
871 fspi: spi@20c0000 { 767 fspi: spi@20c0000 {
872 compatible = "nxp,lx21 768 compatible = "nxp,lx2160a-fspi";
873 #address-cells = <1>; 769 #address-cells = <1>;
874 #size-cells = <0>; 770 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0 771 reg = <0x0 0x20c0000 0x0 0x10000>,
876 <0x0 0x20000000 772 <0x0 0x20000000 0x0 0x10000000>;
877 reg-names = "fspi_base 773 reg-names = "fspi_base", "fspi_mmap";
878 interrupts = <GIC_SPI 774 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clockgen QO !! 775 clocks = <&clockgen 4 3>, <&clockgen 4 3>;
880 QO <<
881 <&clockgen QO <<
882 QO <<
883 clock-names = "fspi_en 776 clock-names = "fspi_en", "fspi";
884 status = "disabled"; 777 status = "disabled";
885 }; 778 };
886 779
887 dspi0: spi@2100000 { !! 780 esdhc0: esdhc@2140000 {
888 compatible = "fsl,lx21 !! 781 compatible = "fsl,esdhc";
889 #address-cells = <1>; <<
890 #size-cells = <0>; <<
891 reg = <0x0 0x2100000 0 <<
892 interrupts = <GIC_SPI <<
893 clocks = <&clockgen QO <<
894 QO <<
895 clock-names = "dspi"; <<
896 spi-num-chipselects = <<
897 bus-num = <0>; <<
898 status = "disabled"; <<
899 }; <<
900 <<
901 dspi1: spi@2110000 { <<
902 compatible = "fsl,lx21 <<
903 #address-cells = <1>; <<
904 #size-cells = <0>; <<
905 reg = <0x0 0x2110000 0 <<
906 interrupts = <GIC_SPI <<
907 clocks = <&clockgen QO <<
908 QO <<
909 clock-names = "dspi"; <<
910 spi-num-chipselects = <<
911 bus-num = <1>; <<
912 status = "disabled"; <<
913 }; <<
914 <<
915 dspi2: spi@2120000 { <<
916 compatible = "fsl,lx21 <<
917 #address-cells = <1>; <<
918 #size-cells = <0>; <<
919 reg = <0x0 0x2120000 0 <<
920 interrupts = <GIC_SPI <<
921 clocks = <&clockgen QO <<
922 QO <<
923 clock-names = "dspi"; <<
924 spi-num-chipselects = <<
925 bus-num = <2>; <<
926 status = "disabled"; <<
927 }; <<
928 <<
929 esdhc0: mmc@2140000 { <<
930 compatible = "fsl,ls20 <<
931 reg = <0x0 0x2140000 0 782 reg = <0x0 0x2140000 0x0 0x10000>;
932 interrupts = <GIC_SPI !! 783 interrupts = <0 28 0x4>; /* Level high type */
933 clocks = <&clockgen QO !! 784 clocks = <&clockgen 4 1>;
934 QO <<
935 dma-coherent; 785 dma-coherent;
936 voltage-ranges = <1800 786 voltage-ranges = <1800 1800 3300 3300>;
937 sdhci,auto-cmd12; 787 sdhci,auto-cmd12;
938 little-endian; 788 little-endian;
939 bus-width = <4>; 789 bus-width = <4>;
940 status = "disabled"; 790 status = "disabled";
941 }; 791 };
942 792
943 esdhc1: mmc@2150000 { !! 793 esdhc1: esdhc@2150000 {
944 compatible = "fsl,ls20 !! 794 compatible = "fsl,esdhc";
945 reg = <0x0 0x2150000 0 795 reg = <0x0 0x2150000 0x0 0x10000>;
946 interrupts = <GIC_SPI !! 796 interrupts = <0 63 0x4>; /* Level high type */
947 clocks = <&clockgen QO !! 797 clocks = <&clockgen 4 1>;
948 QO <<
949 dma-coherent; 798 dma-coherent;
950 voltage-ranges = <1800 799 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12; 800 sdhci,auto-cmd12;
952 broken-cd; 801 broken-cd;
953 little-endian; 802 little-endian;
954 bus-width = <4>; 803 bus-width = <4>;
955 status = "disabled"; 804 status = "disabled";
956 }; 805 };
957 806
958 can0: can@2180000 { <<
959 compatible = "fsl,lx21 <<
960 reg = <0x0 0x2180000 0 <<
961 interrupts = <GIC_SPI <<
962 clocks = <&clockgen QO <<
963 QO <<
964 <&clockgen QO <<
965 clock-names = "ipg", " <<
966 fsl,clk-source = /bits <<
967 status = "disabled"; <<
968 }; <<
969 <<
970 can1: can@2190000 { <<
971 compatible = "fsl,lx21 <<
972 reg = <0x0 0x2190000 0 <<
973 interrupts = <GIC_SPI <<
974 clocks = <&clockgen QO <<
975 QO <<
976 <&clockgen QO <<
977 clock-names = "ipg", " <<
978 fsl,clk-source = /bits <<
979 status = "disabled"; <<
980 }; <<
981 <<
982 uart0: serial@21c0000 { 807 uart0: serial@21c0000 {
983 compatible = "arm,pl01 !! 808 compatible = "arm,sbsa-uart","arm,pl011";
984 clocks = <&clockgen QO <<
985 QO <<
986 <&clockgen QO <<
987 QO <<
988 clock-names = "uartclk <<
989 reg = <0x0 0x21c0000 0 809 reg = <0x0 0x21c0000 0x0 0x1000>;
990 interrupts = <GIC_SPI 810 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> 811 current-speed = <115200>;
991 status = "disabled"; 812 status = "disabled";
992 }; 813 };
993 814
994 uart1: serial@21d0000 { 815 uart1: serial@21d0000 {
995 compatible = "arm,pl01 !! 816 compatible = "arm,sbsa-uart","arm,pl011";
996 clocks = <&clockgen QO <<
997 QO <<
998 <&clockgen QO <<
999 QO <<
1000 clock-names = "uartcl <<
1001 reg = <0x0 0x21d0000 817 reg = <0x0 0x21d0000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 818 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> 819 current-speed = <115200>;
1003 status = "disabled"; 820 status = "disabled";
1004 }; 821 };
1005 822
1006 uart2: serial@21e0000 { 823 uart2: serial@21e0000 {
1007 compatible = "arm,pl0 !! 824 compatible = "arm,sbsa-uart","arm,pl011";
1008 clocks = <&clockgen Q <<
1009 Q <<
1010 <&clockgen Q <<
1011 Q <<
1012 clock-names = "uartcl <<
1013 reg = <0x0 0x21e0000 825 reg = <0x0 0x21e0000 0x0 0x1000>;
1014 interrupts = <GIC_SPI 826 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 827 current-speed = <115200>;
1015 status = "disabled"; 828 status = "disabled";
1016 }; 829 };
1017 830
1018 uart3: serial@21f0000 { 831 uart3: serial@21f0000 {
1019 compatible = "arm,pl0 !! 832 compatible = "arm,sbsa-uart","arm,pl011";
1020 clocks = <&clockgen Q <<
1021 Q <<
1022 <&clockgen Q <<
1023 Q <<
1024 clock-names = "uartcl <<
1025 reg = <0x0 0x21f0000 833 reg = <0x0 0x21f0000 0x0 0x1000>;
1026 interrupts = <GIC_SPI 834 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> 835 current-speed = <115200>;
1027 status = "disabled"; 836 status = "disabled";
1028 }; 837 };
1029 838
1030 gpio0: gpio@2300000 { 839 gpio0: gpio@2300000 {
1031 compatible = "fsl,ls2 !! 840 compatible = "fsl,qoriq-gpio";
1032 reg = <0x0 0x2300000 841 reg = <0x0 0x2300000 0x0 0x10000>;
1033 interrupts = <GIC_SPI 842 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1034 gpio-controller; 843 gpio-controller;
1035 little-endian; 844 little-endian;
1036 #gpio-cells = <2>; 845 #gpio-cells = <2>;
1037 interrupt-controller; 846 interrupt-controller;
1038 #interrupt-cells = <2 847 #interrupt-cells = <2>;
1039 }; 848 };
1040 849
1041 gpio1: gpio@2310000 { 850 gpio1: gpio@2310000 {
1042 compatible = "fsl,ls2 !! 851 compatible = "fsl,qoriq-gpio";
1043 reg = <0x0 0x2310000 852 reg = <0x0 0x2310000 0x0 0x10000>;
1044 interrupts = <GIC_SPI 853 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1045 gpio-controller; 854 gpio-controller;
1046 little-endian; 855 little-endian;
1047 #gpio-cells = <2>; 856 #gpio-cells = <2>;
1048 interrupt-controller; 857 interrupt-controller;
1049 #interrupt-cells = <2 858 #interrupt-cells = <2>;
1050 }; 859 };
1051 860
1052 gpio2: gpio@2320000 { 861 gpio2: gpio@2320000 {
1053 compatible = "fsl,ls2 !! 862 compatible = "fsl,qoriq-gpio";
1054 reg = <0x0 0x2320000 863 reg = <0x0 0x2320000 0x0 0x10000>;
1055 interrupts = <GIC_SPI 864 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1056 gpio-controller; 865 gpio-controller;
1057 little-endian; 866 little-endian;
1058 #gpio-cells = <2>; 867 #gpio-cells = <2>;
1059 interrupt-controller; 868 interrupt-controller;
1060 #interrupt-cells = <2 869 #interrupt-cells = <2>;
1061 }; 870 };
1062 871
1063 gpio3: gpio@2330000 { 872 gpio3: gpio@2330000 {
1064 compatible = "fsl,ls2 !! 873 compatible = "fsl,qoriq-gpio";
1065 reg = <0x0 0x2330000 874 reg = <0x0 0x2330000 0x0 0x10000>;
1066 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1067 gpio-controller; 876 gpio-controller;
1068 little-endian; 877 little-endian;
1069 #gpio-cells = <2>; 878 #gpio-cells = <2>;
1070 interrupt-controller; 879 interrupt-controller;
1071 #interrupt-cells = <2 880 #interrupt-cells = <2>;
1072 }; 881 };
1073 882
1074 watchdog@23a0000 { 883 watchdog@23a0000 {
1075 compatible = "arm,sbs 884 compatible = "arm,sbsa-gwdt";
1076 reg = <0x0 0x23a0000 885 reg = <0x0 0x23a0000 0 0x1000>,
1077 <0x0 0x2390000 886 <0x0 0x2390000 0 0x1000>;
1078 interrupts = <GIC_SPI 887 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1079 timeout-sec = <30>; 888 timeout-sec = <30>;
1080 }; 889 };
1081 890
1082 rcpm: wakeup-controller@1e340 <<
1083 compatible = "fsl,lx2 <<
1084 reg = <0x0 0x1e34040 <<
1085 #fsl,rcpm-wakeup-cell <<
1086 little-endian; <<
1087 }; <<
1088 <<
1089 ftm_alarm0: rtc@2800000 { <<
1090 compatible = "fsl,lx2 <<
1091 reg = <0x0 0x2800000 <<
1092 fsl,rcpm-wakeup = <&r <<
1093 interrupts = <GIC_SPI <<
1094 }; <<
1095 <<
1096 usb0: usb@3100000 { 891 usb0: usb@3100000 {
1097 compatible = "snps,dw 892 compatible = "snps,dwc3";
1098 reg = <0x0 0x3100000 893 reg = <0x0 0x3100000 0x0 0x10000>;
1099 interrupts = <GIC_SPI 894 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1100 dr_mode = "host"; 895 dr_mode = "host";
1101 snps,quirk-frame-leng 896 snps,quirk-frame-length-adjustment = <0x20>;
1102 usb3-lpm-capable; <<
1103 snps,dis_rxdet_inp3_q 897 snps,dis_rxdet_inp3_quirk;
1104 snps,incr-burst-type- 898 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1105 status = "disabled"; 899 status = "disabled";
1106 }; 900 };
1107 901
1108 usb1: usb@3110000 { 902 usb1: usb@3110000 {
1109 compatible = "snps,dw 903 compatible = "snps,dwc3";
1110 reg = <0x0 0x3110000 904 reg = <0x0 0x3110000 0x0 0x10000>;
1111 interrupts = <GIC_SPI 905 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1112 dr_mode = "host"; 906 dr_mode = "host";
1113 snps,quirk-frame-leng 907 snps,quirk-frame-length-adjustment = <0x20>;
1114 usb3-lpm-capable; <<
1115 snps,dis_rxdet_inp3_q 908 snps,dis_rxdet_inp3_quirk;
1116 snps,incr-burst-type- 909 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1117 status = "disabled"; 910 status = "disabled";
1118 }; 911 };
1119 912
1120 sata0: sata@3200000 { 913 sata0: sata@3200000 {
1121 compatible = "fsl,lx2 914 compatible = "fsl,lx2160a-ahci";
1122 reg = <0x0 0x3200000 915 reg = <0x0 0x3200000 0x0 0x10000>,
1123 <0x7 0x100520 0 916 <0x7 0x100520 0x0 0x4>;
1124 reg-names = "ahci", " 917 reg-names = "ahci", "sata-ecc";
1125 interrupts = <GIC_SPI 918 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clockgen Q !! 919 clocks = <&clockgen 4 3>;
1127 Q <<
1128 dma-coherent; 920 dma-coherent;
1129 status = "disabled"; 921 status = "disabled";
1130 }; 922 };
1131 923
1132 sata1: sata@3210000 { 924 sata1: sata@3210000 {
1133 compatible = "fsl,lx2 925 compatible = "fsl,lx2160a-ahci";
1134 reg = <0x0 0x3210000 926 reg = <0x0 0x3210000 0x0 0x10000>,
1135 <0x7 0x100520 0 927 <0x7 0x100520 0x0 0x4>;
1136 reg-names = "ahci", " 928 reg-names = "ahci", "sata-ecc";
1137 interrupts = <GIC_SPI 929 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1138 clocks = <&clockgen Q !! 930 clocks = <&clockgen 4 3>;
1139 Q <<
1140 dma-coherent; 931 dma-coherent;
1141 status = "disabled"; 932 status = "disabled";
1142 }; 933 };
1143 934
1144 sata2: sata@3220000 { 935 sata2: sata@3220000 {
1145 compatible = "fsl,lx2 936 compatible = "fsl,lx2160a-ahci";
1146 reg = <0x0 0x3220000 937 reg = <0x0 0x3220000 0x0 0x10000>,
1147 <0x7 0x100520 0 938 <0x7 0x100520 0x0 0x4>;
1148 reg-names = "ahci", " 939 reg-names = "ahci", "sata-ecc";
1149 interrupts = <GIC_SPI 940 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clockgen Q !! 941 clocks = <&clockgen 4 3>;
1151 Q <<
1152 dma-coherent; 942 dma-coherent;
1153 status = "disabled"; 943 status = "disabled";
1154 }; 944 };
1155 945
1156 sata3: sata@3230000 { 946 sata3: sata@3230000 {
1157 compatible = "fsl,lx2 947 compatible = "fsl,lx2160a-ahci";
1158 reg = <0x0 0x3230000 948 reg = <0x0 0x3230000 0x0 0x10000>,
1159 <0x7 0x100520 0 949 <0x7 0x100520 0x0 0x4>;
1160 reg-names = "ahci", " 950 reg-names = "ahci", "sata-ecc";
1161 interrupts = <GIC_SPI 951 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clockgen Q !! 952 clocks = <&clockgen 4 3>;
1163 Q <<
1164 dma-coherent; 953 dma-coherent;
1165 status = "disabled"; 954 status = "disabled";
1166 }; 955 };
1167 956
1168 pcie1: pcie@3400000 { !! 957 pcie@3400000 {
1169 compatible = "fsl,lx2 958 compatible = "fsl,lx2160a-pcie";
1170 reg = <0x00 0x0340000 !! 959 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
1171 <0x80 0x0000000 !! 960 0x80 0x00000000 0x0 0x00001000>; /* configuration space */
1172 reg-names = "csr_axi_ 961 reg-names = "csr_axi_slave", "config_axi_slave";
1173 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1174 <GIC_SPI 963 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1175 <GIC_SPI 964 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1176 interrupt-names = "ae 965 interrupt-names = "aer", "pme", "intr";
1177 #address-cells = <3>; 966 #address-cells = <3>;
1178 #size-cells = <2>; 967 #size-cells = <2>;
1179 device_type = "pci"; 968 device_type = "pci";
1180 dma-coherent; 969 dma-coherent;
1181 apio-wins = <8>; 970 apio-wins = <8>;
1182 ppio-wins = <8>; 971 ppio-wins = <8>;
1183 bus-range = <0x0 0xff 972 bus-range = <0x0 0xff>;
1184 ranges = <0x82000000 973 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1185 msi-parent = <&its 0> !! 974 msi-parent = <&its>;
1186 #interrupt-cells = <1 975 #interrupt-cells = <1>;
1187 interrupt-map-mask = 976 interrupt-map-mask = <0 0 0 7>;
1188 interrupt-map = <0000 977 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1189 <0000 978 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1190 <0000 979 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1191 <0000 980 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1192 iommu-map = <0 &smmu 981 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1193 status = "disabled"; 982 status = "disabled";
1194 }; 983 };
1195 984
1196 pcie2: pcie@3500000 { !! 985 pcie@3500000 {
1197 compatible = "fsl,lx2 986 compatible = "fsl,lx2160a-pcie";
1198 reg = <0x00 0x0350000 !! 987 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
1199 <0x88 0x0000000 !! 988 0x88 0x00000000 0x0 0x00001000>; /* configuration space */
1200 reg-names = "csr_axi_ 989 reg-names = "csr_axi_slave", "config_axi_slave";
1201 interrupts = <GIC_SPI 990 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1202 <GIC_SPI 991 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1203 <GIC_SPI 992 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1204 interrupt-names = "ae 993 interrupt-names = "aer", "pme", "intr";
1205 #address-cells = <3>; 994 #address-cells = <3>;
1206 #size-cells = <2>; 995 #size-cells = <2>;
1207 device_type = "pci"; 996 device_type = "pci";
1208 dma-coherent; 997 dma-coherent;
1209 apio-wins = <8>; 998 apio-wins = <8>;
1210 ppio-wins = <8>; 999 ppio-wins = <8>;
1211 bus-range = <0x0 0xff 1000 bus-range = <0x0 0xff>;
1212 ranges = <0x82000000 1001 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1213 msi-parent = <&its 0> !! 1002 msi-parent = <&its>;
1214 #interrupt-cells = <1 1003 #interrupt-cells = <1>;
1215 interrupt-map-mask = 1004 interrupt-map-mask = <0 0 0 7>;
1216 interrupt-map = <0000 1005 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1217 <0000 1006 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1218 <0000 1007 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1219 <0000 1008 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1220 iommu-map = <0 &smmu 1009 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1221 status = "disabled"; 1010 status = "disabled";
1222 }; 1011 };
1223 1012
1224 pcie3: pcie@3600000 { !! 1013 pcie@3600000 {
1225 compatible = "fsl,lx2 1014 compatible = "fsl,lx2160a-pcie";
1226 reg = <0x00 0x0360000 !! 1015 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
1227 <0x90 0x0000000 !! 1016 0x90 0x00000000 0x0 0x00001000>; /* configuration space */
1228 reg-names = "csr_axi_ 1017 reg-names = "csr_axi_slave", "config_axi_slave";
1229 interrupts = <GIC_SPI 1018 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1230 <GIC_SPI 1019 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1231 <GIC_SPI 1020 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1232 interrupt-names = "ae 1021 interrupt-names = "aer", "pme", "intr";
1233 #address-cells = <3>; 1022 #address-cells = <3>;
1234 #size-cells = <2>; 1023 #size-cells = <2>;
1235 device_type = "pci"; 1024 device_type = "pci";
1236 dma-coherent; 1025 dma-coherent;
1237 apio-wins = <256>; 1026 apio-wins = <256>;
1238 ppio-wins = <24>; 1027 ppio-wins = <24>;
1239 bus-range = <0x0 0xff 1028 bus-range = <0x0 0xff>;
1240 ranges = <0x82000000 1029 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1241 msi-parent = <&its 0> !! 1030 msi-parent = <&its>;
1242 #interrupt-cells = <1 1031 #interrupt-cells = <1>;
1243 interrupt-map-mask = 1032 interrupt-map-mask = <0 0 0 7>;
1244 interrupt-map = <0000 1033 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245 <0000 1034 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1246 <0000 1035 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1247 <0000 1036 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1248 iommu-map = <0 &smmu 1037 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1249 status = "disabled"; 1038 status = "disabled";
1250 }; 1039 };
1251 1040
1252 pcie4: pcie@3700000 { !! 1041 pcie@3700000 {
1253 compatible = "fsl,lx2 1042 compatible = "fsl,lx2160a-pcie";
1254 reg = <0x00 0x0370000 !! 1043 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
1255 <0x98 0x0000000 !! 1044 0x98 0x00000000 0x0 0x00001000>; /* configuration space */
1256 reg-names = "csr_axi_ 1045 reg-names = "csr_axi_slave", "config_axi_slave";
1257 interrupts = <GIC_SPI 1046 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1258 <GIC_SPI 1047 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1259 <GIC_SPI 1048 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1260 interrupt-names = "ae 1049 interrupt-names = "aer", "pme", "intr";
1261 #address-cells = <3>; 1050 #address-cells = <3>;
1262 #size-cells = <2>; 1051 #size-cells = <2>;
1263 device_type = "pci"; 1052 device_type = "pci";
1264 dma-coherent; 1053 dma-coherent;
1265 apio-wins = <8>; 1054 apio-wins = <8>;
1266 ppio-wins = <8>; 1055 ppio-wins = <8>;
1267 bus-range = <0x0 0xff 1056 bus-range = <0x0 0xff>;
1268 ranges = <0x82000000 1057 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1269 msi-parent = <&its 0> !! 1058 msi-parent = <&its>;
1270 #interrupt-cells = <1 1059 #interrupt-cells = <1>;
1271 interrupt-map-mask = 1060 interrupt-map-mask = <0 0 0 7>;
1272 interrupt-map = <0000 1061 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1273 <0000 1062 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1274 <0000 1063 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1275 <0000 1064 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1276 iommu-map = <0 &smmu 1065 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1277 status = "disabled"; 1066 status = "disabled";
1278 }; 1067 };
1279 1068
1280 pcie5: pcie@3800000 { !! 1069 pcie@3800000 {
1281 compatible = "fsl,lx2 1070 compatible = "fsl,lx2160a-pcie";
1282 reg = <0x00 0x0380000 !! 1071 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
1283 <0xa0 0x0000000 !! 1072 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */
1284 reg-names = "csr_axi_ 1073 reg-names = "csr_axi_slave", "config_axi_slave";
1285 interrupts = <GIC_SPI 1074 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1286 <GIC_SPI 1075 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1287 <GIC_SPI 1076 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1288 interrupt-names = "ae 1077 interrupt-names = "aer", "pme", "intr";
1289 #address-cells = <3>; 1078 #address-cells = <3>;
1290 #size-cells = <2>; 1079 #size-cells = <2>;
1291 device_type = "pci"; 1080 device_type = "pci";
1292 dma-coherent; 1081 dma-coherent;
1293 apio-wins = <256>; 1082 apio-wins = <256>;
1294 ppio-wins = <24>; 1083 ppio-wins = <24>;
1295 bus-range = <0x0 0xff 1084 bus-range = <0x0 0xff>;
1296 ranges = <0x82000000 1085 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1297 msi-parent = <&its 0> !! 1086 msi-parent = <&its>;
1298 #interrupt-cells = <1 1087 #interrupt-cells = <1>;
1299 interrupt-map-mask = 1088 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0000 1089 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1301 <0000 1090 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1302 <0000 1091 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1303 <0000 1092 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1304 iommu-map = <0 &smmu 1093 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1305 status = "disabled"; 1094 status = "disabled";
1306 }; 1095 };
1307 1096
1308 pcie6: pcie@3900000 { !! 1097 pcie@3900000 {
1309 compatible = "fsl,lx2 1098 compatible = "fsl,lx2160a-pcie";
1310 reg = <0x00 0x0390000 !! 1099 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
1311 <0xa8 0x0000000 !! 1100 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */
1312 reg-names = "csr_axi_ 1101 reg-names = "csr_axi_slave", "config_axi_slave";
1313 interrupts = <GIC_SPI 1102 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1314 <GIC_SPI 1103 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1315 <GIC_SPI 1104 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1316 interrupt-names = "ae 1105 interrupt-names = "aer", "pme", "intr";
1317 #address-cells = <3>; 1106 #address-cells = <3>;
1318 #size-cells = <2>; 1107 #size-cells = <2>;
1319 device_type = "pci"; 1108 device_type = "pci";
1320 dma-coherent; 1109 dma-coherent;
1321 apio-wins = <8>; 1110 apio-wins = <8>;
1322 ppio-wins = <8>; 1111 ppio-wins = <8>;
1323 bus-range = <0x0 0xff 1112 bus-range = <0x0 0xff>;
1324 ranges = <0x82000000 1113 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1325 msi-parent = <&its 0> !! 1114 msi-parent = <&its>;
1326 #interrupt-cells = <1 1115 #interrupt-cells = <1>;
1327 interrupt-map-mask = 1116 interrupt-map-mask = <0 0 0 7>;
1328 interrupt-map = <0000 1117 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1329 <0000 1118 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1330 <0000 1119 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1331 <0000 1120 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1332 iommu-map = <0 &smmu 1121 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1333 status = "disabled"; 1122 status = "disabled";
1334 }; 1123 };
1335 1124
1336 smmu: iommu@5000000 { 1125 smmu: iommu@5000000 {
1337 compatible = "arm,mmu 1126 compatible = "arm,mmu-500";
1338 reg = <0 0x5000000 0 1127 reg = <0 0x5000000 0 0x800000>;
1339 #iommu-cells = <1>; 1128 #iommu-cells = <1>;
1340 #global-interrupts = 1129 #global-interrupts = <14>;
1341 // globa 1130 // global secure fault
1342 interrupts = <GIC_SPI 1131 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1343 // combi 1132 // combined secure
1344 <GIC_SPI 1133 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1345 // globa 1134 // global non-secure fault
1346 <GIC_SPI 1135 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1347 // combi 1136 // combined non-secure
1348 <GIC_SPI 1137 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1349 // perfo 1138 // performance counter interrupts 0-9
1350 <GIC_SPI 1139 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 1140 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 1141 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 1142 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 1143 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 1144 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 1145 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 1146 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 1147 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 1148 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1360 // per c 1149 // per context interrupt, 64 interrupts
1361 <GIC_SPI 1150 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 1151 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 1152 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1153 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1154 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1155 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1156 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1157 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1158 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1159 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1160 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1161 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1162 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1163 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1164 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1165 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1166 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1167 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1168 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1169 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1170 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1171 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1172 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1173 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1174 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1175 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1176 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1177 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1178 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1179 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1180 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1181 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1182 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1183 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1184 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1185 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1186 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1187 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1188 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1189 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1190 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1191 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1192 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1193 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1194 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1195 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1196 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1197 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1198 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1199 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1200 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1201 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1202 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1203 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 1204 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 1205 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 1206 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 1207 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 1208 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 1209 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 1210 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 1211 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 1212 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 1213 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1425 dma-coherent; 1214 dma-coherent;
1426 }; 1215 };
1427 1216
1428 console@8340020 { 1217 console@8340020 {
1429 compatible = "fsl,dpa 1218 compatible = "fsl,dpaa2-console";
1430 reg = <0x00000000 0x0 1219 reg = <0x00000000 0x08340020 0 0x2>;
1431 }; 1220 };
1432 1221
1433 ptp-timer@8b95000 { 1222 ptp-timer@8b95000 {
1434 compatible = "fsl,dpa 1223 compatible = "fsl,dpaa2-ptp";
1435 reg = <0x0 0x8b95000 1224 reg = <0x0 0x8b95000 0x0 0x100>;
1436 clocks = <&clockgen Q !! 1225 clocks = <&clockgen 4 1>;
1437 Q <<
1438 little-endian; 1226 little-endian;
1439 fsl,extts-fifo; 1227 fsl,extts-fifo;
1440 }; 1228 };
1441 1229
1442 /* WRIOP0: 0x8b8_0000, E-MDIO 1230 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1443 emdio1: mdio@8b96000 { 1231 emdio1: mdio@8b96000 {
1444 compatible = "fsl,fma 1232 compatible = "fsl,fman-memac-mdio";
1445 reg = <0x0 0x8b96000 1233 reg = <0x0 0x8b96000 0x0 0x1000>;
1446 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1447 #address-cells = <1>; 1235 #address-cells = <1>;
1448 #size-cells = <0>; 1236 #size-cells = <0>;
1449 little-endian; 1237 little-endian;
1450 clock-frequency = <25 <<
1451 clocks = <&clockgen Q <<
1452 Q <<
1453 status = "disabled"; 1238 status = "disabled";
1454 }; 1239 };
1455 1240
1456 emdio2: mdio@8b97000 { 1241 emdio2: mdio@8b97000 {
1457 compatible = "fsl,fma 1242 compatible = "fsl,fman-memac-mdio";
1458 reg = <0x0 0x8b97000 1243 reg = <0x0 0x8b97000 0x0 0x1000>;
1459 interrupts = <GIC_SPI 1244 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1460 little-endian; 1245 little-endian;
1461 #address-cells = <1>; 1246 #address-cells = <1>;
1462 #size-cells = <0>; 1247 #size-cells = <0>;
1463 clock-frequency = <25 <<
1464 clocks = <&clockgen Q <<
1465 Q <<
1466 status = "disabled"; <<
1467 }; <<
1468 <<
1469 pcs_mdio1: mdio@8c07000 { <<
1470 compatible = "fsl,fma <<
1471 reg = <0x0 0x8c07000 <<
1472 little-endian; <<
1473 #address-cells = <1>; <<
1474 #size-cells = <0>; <<
1475 status = "disabled"; <<
1476 <<
1477 pcs1: ethernet-phy@0 <<
1478 reg = <0>; <<
1479 }; <<
1480 }; <<
1481 <<
1482 pcs_mdio2: mdio@8c0b000 { <<
1483 compatible = "fsl,fma <<
1484 reg = <0x0 0x8c0b000 <<
1485 little-endian; <<
1486 #address-cells = <1>; <<
1487 #size-cells = <0>; <<
1488 status = "disabled"; <<
1489 <<
1490 pcs2: ethernet-phy@0 <<
1491 reg = <0>; <<
1492 }; <<
1493 }; <<
1494 <<
1495 pcs_mdio3: mdio@8c0f000 { <<
1496 compatible = "fsl,fma <<
1497 reg = <0x0 0x8c0f000 <<
1498 little-endian; <<
1499 #address-cells = <1>; <<
1500 #size-cells = <0>; <<
1501 status = "disabled"; <<
1502 <<
1503 pcs3: ethernet-phy@0 <<
1504 reg = <0>; <<
1505 }; <<
1506 }; <<
1507 <<
1508 pcs_mdio4: mdio@8c13000 { <<
1509 compatible = "fsl,fma <<
1510 reg = <0x0 0x8c13000 <<
1511 little-endian; <<
1512 #address-cells = <1>; <<
1513 #size-cells = <0>; <<
1514 status = "disabled"; <<
1515 <<
1516 pcs4: ethernet-phy@0 <<
1517 reg = <0>; <<
1518 }; <<
1519 }; <<
1520 <<
1521 pcs_mdio5: mdio@8c17000 { <<
1522 compatible = "fsl,fma <<
1523 reg = <0x0 0x8c17000 <<
1524 little-endian; <<
1525 #address-cells = <1>; <<
1526 #size-cells = <0>; <<
1527 status = "disabled"; <<
1528 <<
1529 pcs5: ethernet-phy@0 <<
1530 reg = <0>; <<
1531 }; <<
1532 }; <<
1533 <<
1534 pcs_mdio6: mdio@8c1b000 { <<
1535 compatible = "fsl,fma <<
1536 reg = <0x0 0x8c1b000 <<
1537 little-endian; <<
1538 #address-cells = <1>; <<
1539 #size-cells = <0>; <<
1540 status = "disabled"; <<
1541 <<
1542 pcs6: ethernet-phy@0 <<
1543 reg = <0>; <<
1544 }; <<
1545 }; <<
1546 <<
1547 pcs_mdio7: mdio@8c1f000 { <<
1548 compatible = "fsl,fma <<
1549 reg = <0x0 0x8c1f000 <<
1550 little-endian; <<
1551 #address-cells = <1>; <<
1552 #size-cells = <0>; <<
1553 status = "disabled"; <<
1554 <<
1555 pcs7: ethernet-phy@0 <<
1556 reg = <0>; <<
1557 }; <<
1558 }; <<
1559 <<
1560 pcs_mdio8: mdio@8c23000 { <<
1561 compatible = "fsl,fma <<
1562 reg = <0x0 0x8c23000 <<
1563 little-endian; <<
1564 #address-cells = <1>; <<
1565 #size-cells = <0>; <<
1566 status = "disabled"; <<
1567 <<
1568 pcs8: ethernet-phy@0 <<
1569 reg = <0>; <<
1570 }; <<
1571 }; <<
1572 <<
1573 pcs_mdio9: mdio@8c27000 { <<
1574 compatible = "fsl,fma <<
1575 reg = <0x0 0x8c27000 <<
1576 little-endian; <<
1577 #address-cells = <1>; <<
1578 #size-cells = <0>; <<
1579 status = "disabled"; <<
1580 <<
1581 pcs9: ethernet-phy@0 <<
1582 reg = <0>; <<
1583 }; <<
1584 }; <<
1585 <<
1586 pcs_mdio10: mdio@8c2b000 { <<
1587 compatible = "fsl,fma <<
1588 reg = <0x0 0x8c2b000 <<
1589 little-endian; <<
1590 #address-cells = <1>; <<
1591 #size-cells = <0>; <<
1592 status = "disabled"; <<
1593 <<
1594 pcs10: ethernet-phy@0 <<
1595 reg = <0>; <<
1596 }; <<
1597 }; <<
1598 <<
1599 pcs_mdio11: mdio@8c2f000 { <<
1600 compatible = "fsl,fma <<
1601 reg = <0x0 0x8c2f000 <<
1602 little-endian; <<
1603 #address-cells = <1>; <<
1604 #size-cells = <0>; <<
1605 status = "disabled"; <<
1606 <<
1607 pcs11: ethernet-phy@0 <<
1608 reg = <0>; <<
1609 }; <<
1610 }; <<
1611 <<
1612 pcs_mdio12: mdio@8c33000 { <<
1613 compatible = "fsl,fma <<
1614 reg = <0x0 0x8c33000 <<
1615 little-endian; <<
1616 #address-cells = <1>; <<
1617 #size-cells = <0>; <<
1618 status = "disabled"; <<
1619 <<
1620 pcs12: ethernet-phy@0 <<
1621 reg = <0>; <<
1622 }; <<
1623 }; <<
1624 <<
1625 pcs_mdio13: mdio@8c37000 { <<
1626 compatible = "fsl,fma <<
1627 reg = <0x0 0x8c37000 <<
1628 little-endian; <<
1629 #address-cells = <1>; <<
1630 #size-cells = <0>; <<
1631 status = "disabled"; <<
1632 <<
1633 pcs13: ethernet-phy@0 <<
1634 reg = <0>; <<
1635 }; <<
1636 }; <<
1637 <<
1638 pcs_mdio14: mdio@8c3b000 { <<
1639 compatible = "fsl,fma <<
1640 reg = <0x0 0x8c3b000 <<
1641 little-endian; <<
1642 #address-cells = <1>; <<
1643 #size-cells = <0>; <<
1644 status = "disabled"; <<
1645 <<
1646 pcs14: ethernet-phy@0 <<
1647 reg = <0>; <<
1648 }; <<
1649 }; <<
1650 <<
1651 pcs_mdio15: mdio@8c3f000 { <<
1652 compatible = "fsl,fma <<
1653 reg = <0x0 0x8c3f000 <<
1654 little-endian; <<
1655 #address-cells = <1>; <<
1656 #size-cells = <0>; <<
1657 status = "disabled"; <<
1658 <<
1659 pcs15: ethernet-phy@0 <<
1660 reg = <0>; <<
1661 }; <<
1662 }; <<
1663 <<
1664 pcs_mdio16: mdio@8c43000 { <<
1665 compatible = "fsl,fma <<
1666 reg = <0x0 0x8c43000 <<
1667 little-endian; <<
1668 #address-cells = <1>; <<
1669 #size-cells = <0>; <<
1670 status = "disabled"; <<
1671 <<
1672 pcs16: ethernet-phy@0 <<
1673 reg = <0>; <<
1674 }; <<
1675 }; <<
1676 <<
1677 pcs_mdio17: mdio@8c47000 { <<
1678 compatible = "fsl,fma <<
1679 reg = <0x0 0x8c47000 <<
1680 little-endian; <<
1681 #address-cells = <1>; <<
1682 #size-cells = <0>; <<
1683 status = "disabled"; 1248 status = "disabled";
1684 <<
1685 pcs17: ethernet-phy@0 <<
1686 reg = <0>; <<
1687 }; <<
1688 }; <<
1689 <<
1690 pcs_mdio18: mdio@8c4b000 { <<
1691 compatible = "fsl,fma <<
1692 reg = <0x0 0x8c4b000 <<
1693 little-endian; <<
1694 #address-cells = <1>; <<
1695 #size-cells = <0>; <<
1696 status = "disabled"; <<
1697 <<
1698 pcs18: ethernet-phy@0 <<
1699 reg = <0>; <<
1700 }; <<
1701 }; <<
1702 <<
1703 pinmux_i2crv: pinmux@70010012 <<
1704 compatible = "pinctrl <<
1705 reg = <0x00000007 0x0 <<
1706 #address-cells = <1>; <<
1707 #size-cells = <0>; <<
1708 pinctrl-single,bit-pe <<
1709 pinctrl-single,regist <<
1710 pinctrl-single,functi <<
1711 <<
1712 i2c1_scl: i2c1-scl-pi <<
1713 pinctrl-singl <<
1714 }; <<
1715 <<
1716 i2c1_scl_gpio: i2c1-s <<
1717 pinctrl-singl <<
1718 }; <<
1719 <<
1720 i2c2_scl: i2c2-scl-pi <<
1721 pinctrl-singl <<
1722 }; <<
1723 <<
1724 i2c2_scl_gpio: i2c2-s <<
1725 pinctrl-singl <<
1726 }; <<
1727 <<
1728 i2c3_scl: i2c3-scl-pi <<
1729 pinctrl-singl <<
1730 }; <<
1731 <<
1732 i2c3_scl_gpio: i2c3-s <<
1733 pinctrl-singl <<
1734 }; <<
1735 <<
1736 i2c4_scl: i2c4-scl-pi <<
1737 pinctrl-singl <<
1738 }; <<
1739 <<
1740 i2c4_scl_gpio: i2c4-s <<
1741 pinctrl-singl <<
1742 }; <<
1743 <<
1744 i2c5_scl: i2c5-scl-pi <<
1745 pinctrl-singl <<
1746 }; <<
1747 <<
1748 i2c5_scl_gpio: i2c5-s <<
1749 pinctrl-singl <<
1750 }; <<
1751 <<
1752 i2c6_scl: i2c6-scl-pi <<
1753 pinctrl-singl <<
1754 }; <<
1755 <<
1756 i2c6_scl_gpio: i2c6-s <<
1757 pinctrl-singl <<
1758 }; <<
1759 <<
1760 i2c7_scl: i2c7-scl-pi <<
1761 pinctrl-singl <<
1762 }; <<
1763 <<
1764 i2c7_scl_gpio: i2c7-s <<
1765 pinctrl-singl <<
1766 }; <<
1767 <<
1768 i2c0_scl: i2c0-scl-pi <<
1769 pinctrl-singl <<
1770 }; <<
1771 <<
1772 i2c0_scl_gpio: i2c0-s <<
1773 pinctrl-singl <<
1774 }; <<
1775 }; 1249 };
1776 1250
1777 fsl_mc: fsl-mc@80c000000 { 1251 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qor 1252 compatible = "fsl,qoriq-mc";
1779 reg = <0x00000008 0x0 1253 reg = <0x00000008 0x0c000000 0 0x40>,
1780 <0x00000000 0x0 1254 <0x00000000 0x08340000 0 0x40000>;
1781 msi-parent = <&its 0> !! 1255 msi-parent = <&its>;
1782 /* iommu-map property 1256 /* iommu-map property is fixed up by u-boot */
1783 iommu-map = <0 &smmu 1257 iommu-map = <0 &smmu 0 0>;
1784 dma-coherent; 1258 dma-coherent;
1785 #address-cells = <3>; 1259 #address-cells = <3>;
1786 #size-cells = <1>; 1260 #size-cells = <1>;
1787 1261
1788 /* 1262 /*
1789 * Region type 0x0 - 1263 * Region type 0x0 - MC portals
1790 * Region type 0x1 - 1264 * Region type 0x1 - QBMAN portals
1791 */ 1265 */
1792 ranges = <0x0 0x0 0x0 1266 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1793 0x1 0x0 0x0 1267 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1794 1268
1795 /* 1269 /*
1796 * Define the maximum 1270 * Define the maximum number of MACs present on the SoC.
1797 */ 1271 */
1798 dpmacs { 1272 dpmacs {
1799 #address-cell 1273 #address-cells = <1>;
1800 #size-cells = 1274 #size-cells = <0>;
1801 1275
1802 dpmac1: ether !! 1276 dpmac1: dpmac@1 {
1803 compa 1277 compatible = "fsl,qoriq-mc-dpmac";
1804 reg = 1278 reg = <0x1>;
1805 pcs-h <<
1806 }; 1279 };
1807 1280
1808 dpmac2: ether !! 1281 dpmac2: dpmac@2 {
1809 compa 1282 compatible = "fsl,qoriq-mc-dpmac";
1810 reg = 1283 reg = <0x2>;
1811 pcs-h <<
1812 }; 1284 };
1813 1285
1814 dpmac3: ether !! 1286 dpmac3: dpmac@3 {
1815 compa 1287 compatible = "fsl,qoriq-mc-dpmac";
1816 reg = 1288 reg = <0x3>;
1817 pcs-h <<
1818 }; 1289 };
1819 1290
1820 dpmac4: ether !! 1291 dpmac4: dpmac@4 {
1821 compa 1292 compatible = "fsl,qoriq-mc-dpmac";
1822 reg = 1293 reg = <0x4>;
1823 pcs-h <<
1824 }; 1294 };
1825 1295
1826 dpmac5: ether !! 1296 dpmac5: dpmac@5 {
1827 compa 1297 compatible = "fsl,qoriq-mc-dpmac";
1828 reg = 1298 reg = <0x5>;
1829 pcs-h <<
1830 }; 1299 };
1831 1300
1832 dpmac6: ether !! 1301 dpmac6: dpmac@6 {
1833 compa 1302 compatible = "fsl,qoriq-mc-dpmac";
1834 reg = 1303 reg = <0x6>;
1835 pcs-h <<
1836 }; 1304 };
1837 1305
1838 dpmac7: ether !! 1306 dpmac7: dpmac@7 {
1839 compa 1307 compatible = "fsl,qoriq-mc-dpmac";
1840 reg = 1308 reg = <0x7>;
1841 pcs-h <<
1842 }; 1309 };
1843 1310
1844 dpmac8: ether !! 1311 dpmac8: dpmac@8 {
1845 compa 1312 compatible = "fsl,qoriq-mc-dpmac";
1846 reg = 1313 reg = <0x8>;
1847 pcs-h <<
1848 }; 1314 };
1849 1315
1850 dpmac9: ether !! 1316 dpmac9: dpmac@9 {
1851 compa 1317 compatible = "fsl,qoriq-mc-dpmac";
1852 reg = 1318 reg = <0x9>;
1853 pcs-h <<
1854 }; 1319 };
1855 1320
1856 dpmac10: ethe !! 1321 dpmac10: dpmac@a {
1857 compa 1322 compatible = "fsl,qoriq-mc-dpmac";
1858 reg = 1323 reg = <0xa>;
1859 pcs-h <<
1860 }; 1324 };
1861 1325
1862 dpmac11: ethe !! 1326 dpmac11: dpmac@b {
1863 compa 1327 compatible = "fsl,qoriq-mc-dpmac";
1864 reg = 1328 reg = <0xb>;
1865 pcs-h <<
1866 }; 1329 };
1867 1330
1868 dpmac12: ethe !! 1331 dpmac12: dpmac@c {
1869 compa 1332 compatible = "fsl,qoriq-mc-dpmac";
1870 reg = 1333 reg = <0xc>;
1871 pcs-h <<
1872 }; 1334 };
1873 1335
1874 dpmac13: ethe !! 1336 dpmac13: dpmac@d {
1875 compa 1337 compatible = "fsl,qoriq-mc-dpmac";
1876 reg = 1338 reg = <0xd>;
1877 pcs-h <<
1878 }; 1339 };
1879 1340
1880 dpmac14: ethe !! 1341 dpmac14: dpmac@e {
1881 compa 1342 compatible = "fsl,qoriq-mc-dpmac";
1882 reg = 1343 reg = <0xe>;
1883 pcs-h <<
1884 }; 1344 };
1885 1345
1886 dpmac15: ethe !! 1346 dpmac15: dpmac@f {
1887 compa 1347 compatible = "fsl,qoriq-mc-dpmac";
1888 reg = 1348 reg = <0xf>;
1889 pcs-h <<
1890 }; 1349 };
1891 1350
1892 dpmac16: ethe !! 1351 dpmac16: dpmac@10 {
1893 compa 1352 compatible = "fsl,qoriq-mc-dpmac";
1894 reg = 1353 reg = <0x10>;
1895 pcs-h <<
1896 }; 1354 };
1897 1355
1898 dpmac17: ethe !! 1356 dpmac17: dpmac@11 {
1899 compa 1357 compatible = "fsl,qoriq-mc-dpmac";
1900 reg = 1358 reg = <0x11>;
1901 pcs-h <<
1902 }; 1359 };
1903 1360
1904 dpmac18: ethe !! 1361 dpmac18: dpmac@12 {
1905 compa 1362 compatible = "fsl,qoriq-mc-dpmac";
1906 reg = 1363 reg = <0x12>;
1907 pcs-h <<
1908 }; 1364 };
1909 }; 1365 };
1910 }; <<
1911 }; <<
1912 <<
1913 firmware { <<
1914 optee: optee { <<
1915 compatible = "linaro, <<
1916 method = "smc"; <<
1917 status = "disabled"; <<
1918 }; 1366 };
1919 }; 1367 };
1920 }; 1368 };
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