1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree Include file for Layerscape-LX2 3 // Device Tree Include file for Layerscape-LX2160A family SoC.
4 // 4 //
5 // Copyright 2018-2020 NXP 5 // Copyright 2018-2020 NXP
6 6
7 #include <dt-bindings/clock/fsl,qoriq-clockgen 7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
11 11
12 /memreserve/ 0x80000000 0x00010000; 12 /memreserve/ 0x80000000 0x00010000;
13 13
14 / { 14 / {
15 compatible = "fsl,lx2160a"; 15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 rtc1 = &ftm_alarm0; 21 rtc1 = &ftm_alarm0;
22 }; 22 };
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 27
28 // 8 clusters having 2 Cortex- 28 // 8 clusters having 2 Cortex-A72 cores each
29 cpu0: cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cort 31 compatible = "arm,cortex-a72";
32 enable-method = "psci" 32 enable-method = "psci";
33 reg = <0x0>; 33 reg = <0x0>;
34 clocks = <&clockgen QO 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000 35 d-cache-size = <0x8000>;
36 d-cache-line-size = <6 36 d-cache-line-size = <64>;
37 d-cache-sets = <128>; 37 d-cache-sets = <128>;
38 i-cache-size = <0xC000 38 i-cache-size = <0xC000>;
39 i-cache-line-size = <6 39 i-cache-line-size = <64>;
40 i-cache-sets = <192>; 40 i-cache-sets = <192>;
41 next-level-cache = <&c 41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cp 42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>; 43 #cooling-cells = <2>;
44 }; 44 };
45 45
46 cpu1: cpu@1 { 46 cpu1: cpu@1 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a72";
49 enable-method = "psci" 49 enable-method = "psci";
50 reg = <0x1>; 50 reg = <0x1>;
51 clocks = <&clockgen QO 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000 52 d-cache-size = <0x8000>;
53 d-cache-line-size = <6 53 d-cache-line-size = <64>;
54 d-cache-sets = <128>; 54 d-cache-sets = <128>;
55 i-cache-size = <0xC000 55 i-cache-size = <0xC000>;
56 i-cache-line-size = <6 56 i-cache-line-size = <64>;
57 i-cache-sets = <192>; 57 i-cache-sets = <192>;
58 next-level-cache = <&c 58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cp 59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>; 60 #cooling-cells = <2>;
61 }; 61 };
62 62
63 cpu100: cpu@100 { 63 cpu100: cpu@100 {
64 device_type = "cpu"; 64 device_type = "cpu";
65 compatible = "arm,cort 65 compatible = "arm,cortex-a72";
66 enable-method = "psci" 66 enable-method = "psci";
67 reg = <0x100>; 67 reg = <0x100>;
68 clocks = <&clockgen QO 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69 d-cache-size = <0x8000 69 d-cache-size = <0x8000>;
70 d-cache-line-size = <6 70 d-cache-line-size = <64>;
71 d-cache-sets = <128>; 71 d-cache-sets = <128>;
72 i-cache-size = <0xC000 72 i-cache-size = <0xC000>;
73 i-cache-line-size = <6 73 i-cache-line-size = <64>;
74 i-cache-sets = <192>; 74 i-cache-sets = <192>;
75 next-level-cache = <&c 75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cp 76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>; 77 #cooling-cells = <2>;
78 }; 78 };
79 79
80 cpu101: cpu@101 { 80 cpu101: cpu@101 {
81 device_type = "cpu"; 81 device_type = "cpu";
82 compatible = "arm,cort 82 compatible = "arm,cortex-a72";
83 enable-method = "psci" 83 enable-method = "psci";
84 reg = <0x101>; 84 reg = <0x101>;
85 clocks = <&clockgen QO 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86 d-cache-size = <0x8000 86 d-cache-size = <0x8000>;
87 d-cache-line-size = <6 87 d-cache-line-size = <64>;
88 d-cache-sets = <128>; 88 d-cache-sets = <128>;
89 i-cache-size = <0xC000 89 i-cache-size = <0xC000>;
90 i-cache-line-size = <6 90 i-cache-line-size = <64>;
91 i-cache-sets = <192>; 91 i-cache-sets = <192>;
92 next-level-cache = <&c 92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cp 93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>; 94 #cooling-cells = <2>;
95 }; 95 };
96 96
97 cpu200: cpu@200 { 97 cpu200: cpu@200 {
98 device_type = "cpu"; 98 device_type = "cpu";
99 compatible = "arm,cort 99 compatible = "arm,cortex-a72";
100 enable-method = "psci" 100 enable-method = "psci";
101 reg = <0x200>; 101 reg = <0x200>;
102 clocks = <&clockgen QO 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103 d-cache-size = <0x8000 103 d-cache-size = <0x8000>;
104 d-cache-line-size = <6 104 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 105 d-cache-sets = <128>;
106 i-cache-size = <0xC000 106 i-cache-size = <0xC000>;
107 i-cache-line-size = <6 107 i-cache-line-size = <64>;
108 i-cache-sets = <192>; 108 i-cache-sets = <192>;
109 next-level-cache = <&c 109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cp 110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>; 111 #cooling-cells = <2>;
112 }; 112 };
113 113
114 cpu201: cpu@201 { 114 cpu201: cpu@201 {
115 device_type = "cpu"; 115 device_type = "cpu";
116 compatible = "arm,cort 116 compatible = "arm,cortex-a72";
117 enable-method = "psci" 117 enable-method = "psci";
118 reg = <0x201>; 118 reg = <0x201>;
119 clocks = <&clockgen QO 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120 d-cache-size = <0x8000 120 d-cache-size = <0x8000>;
121 d-cache-line-size = <6 121 d-cache-line-size = <64>;
122 d-cache-sets = <128>; 122 d-cache-sets = <128>;
123 i-cache-size = <0xC000 123 i-cache-size = <0xC000>;
124 i-cache-line-size = <6 124 i-cache-line-size = <64>;
125 i-cache-sets = <192>; 125 i-cache-sets = <192>;
126 next-level-cache = <&c 126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cp 127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>; 128 #cooling-cells = <2>;
129 }; 129 };
130 130
131 cpu300: cpu@300 { 131 cpu300: cpu@300 {
132 device_type = "cpu"; 132 device_type = "cpu";
133 compatible = "arm,cort 133 compatible = "arm,cortex-a72";
134 enable-method = "psci" 134 enable-method = "psci";
135 reg = <0x300>; 135 reg = <0x300>;
136 clocks = <&clockgen QO 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137 d-cache-size = <0x8000 137 d-cache-size = <0x8000>;
138 d-cache-line-size = <6 138 d-cache-line-size = <64>;
139 d-cache-sets = <128>; 139 d-cache-sets = <128>;
140 i-cache-size = <0xC000 140 i-cache-size = <0xC000>;
141 i-cache-line-size = <6 141 i-cache-line-size = <64>;
142 i-cache-sets = <192>; 142 i-cache-sets = <192>;
143 next-level-cache = <&c 143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cp 144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>; 145 #cooling-cells = <2>;
146 }; 146 };
147 147
148 cpu301: cpu@301 { 148 cpu301: cpu@301 {
149 device_type = "cpu"; 149 device_type = "cpu";
150 compatible = "arm,cort 150 compatible = "arm,cortex-a72";
151 enable-method = "psci" 151 enable-method = "psci";
152 reg = <0x301>; 152 reg = <0x301>;
153 clocks = <&clockgen QO 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154 d-cache-size = <0x8000 154 d-cache-size = <0x8000>;
155 d-cache-line-size = <6 155 d-cache-line-size = <64>;
156 d-cache-sets = <128>; 156 d-cache-sets = <128>;
157 i-cache-size = <0xC000 157 i-cache-size = <0xC000>;
158 i-cache-line-size = <6 158 i-cache-line-size = <64>;
159 i-cache-sets = <192>; 159 i-cache-sets = <192>;
160 next-level-cache = <&c 160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cp 161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>; 162 #cooling-cells = <2>;
163 }; 163 };
164 164
165 cpu400: cpu@400 { 165 cpu400: cpu@400 {
166 device_type = "cpu"; 166 device_type = "cpu";
167 compatible = "arm,cort 167 compatible = "arm,cortex-a72";
168 enable-method = "psci" 168 enable-method = "psci";
169 reg = <0x400>; 169 reg = <0x400>;
170 clocks = <&clockgen QO 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171 d-cache-size = <0x8000 171 d-cache-size = <0x8000>;
172 d-cache-line-size = <6 172 d-cache-line-size = <64>;
173 d-cache-sets = <128>; 173 d-cache-sets = <128>;
174 i-cache-size = <0xC000 174 i-cache-size = <0xC000>;
175 i-cache-line-size = <6 175 i-cache-line-size = <64>;
176 i-cache-sets = <192>; 176 i-cache-sets = <192>;
177 next-level-cache = <&c 177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cp 178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>; 179 #cooling-cells = <2>;
180 }; 180 };
181 181
182 cpu401: cpu@401 { 182 cpu401: cpu@401 {
183 device_type = "cpu"; 183 device_type = "cpu";
184 compatible = "arm,cort 184 compatible = "arm,cortex-a72";
185 enable-method = "psci" 185 enable-method = "psci";
186 reg = <0x401>; 186 reg = <0x401>;
187 clocks = <&clockgen QO 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188 d-cache-size = <0x8000 188 d-cache-size = <0x8000>;
189 d-cache-line-size = <6 189 d-cache-line-size = <64>;
190 d-cache-sets = <128>; 190 d-cache-sets = <128>;
191 i-cache-size = <0xC000 191 i-cache-size = <0xC000>;
192 i-cache-line-size = <6 192 i-cache-line-size = <64>;
193 i-cache-sets = <192>; 193 i-cache-sets = <192>;
194 next-level-cache = <&c 194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cp 195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>; 196 #cooling-cells = <2>;
197 }; 197 };
198 198
199 cpu500: cpu@500 { 199 cpu500: cpu@500 {
200 device_type = "cpu"; 200 device_type = "cpu";
201 compatible = "arm,cort 201 compatible = "arm,cortex-a72";
202 enable-method = "psci" 202 enable-method = "psci";
203 reg = <0x500>; 203 reg = <0x500>;
204 clocks = <&clockgen QO 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205 d-cache-size = <0x8000 205 d-cache-size = <0x8000>;
206 d-cache-line-size = <6 206 d-cache-line-size = <64>;
207 d-cache-sets = <128>; 207 d-cache-sets = <128>;
208 i-cache-size = <0xC000 208 i-cache-size = <0xC000>;
209 i-cache-line-size = <6 209 i-cache-line-size = <64>;
210 i-cache-sets = <192>; 210 i-cache-sets = <192>;
211 next-level-cache = <&c 211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cp 212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>; 213 #cooling-cells = <2>;
214 }; 214 };
215 215
216 cpu501: cpu@501 { 216 cpu501: cpu@501 {
217 device_type = "cpu"; 217 device_type = "cpu";
218 compatible = "arm,cort 218 compatible = "arm,cortex-a72";
219 enable-method = "psci" 219 enable-method = "psci";
220 reg = <0x501>; 220 reg = <0x501>;
221 clocks = <&clockgen QO 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222 d-cache-size = <0x8000 222 d-cache-size = <0x8000>;
223 d-cache-line-size = <6 223 d-cache-line-size = <64>;
224 d-cache-sets = <128>; 224 d-cache-sets = <128>;
225 i-cache-size = <0xC000 225 i-cache-size = <0xC000>;
226 i-cache-line-size = <6 226 i-cache-line-size = <64>;
227 i-cache-sets = <192>; 227 i-cache-sets = <192>;
228 next-level-cache = <&c 228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cp 229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>; 230 #cooling-cells = <2>;
231 }; 231 };
232 232
233 cpu600: cpu@600 { 233 cpu600: cpu@600 {
234 device_type = "cpu"; 234 device_type = "cpu";
235 compatible = "arm,cort 235 compatible = "arm,cortex-a72";
236 enable-method = "psci" 236 enable-method = "psci";
237 reg = <0x600>; 237 reg = <0x600>;
238 clocks = <&clockgen QO 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239 d-cache-size = <0x8000 239 d-cache-size = <0x8000>;
240 d-cache-line-size = <6 240 d-cache-line-size = <64>;
241 d-cache-sets = <128>; 241 d-cache-sets = <128>;
242 i-cache-size = <0xC000 242 i-cache-size = <0xC000>;
243 i-cache-line-size = <6 243 i-cache-line-size = <64>;
244 i-cache-sets = <192>; 244 i-cache-sets = <192>;
245 next-level-cache = <&c 245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cp 246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>; 247 #cooling-cells = <2>;
248 }; 248 };
249 249
250 cpu601: cpu@601 { 250 cpu601: cpu@601 {
251 device_type = "cpu"; 251 device_type = "cpu";
252 compatible = "arm,cort 252 compatible = "arm,cortex-a72";
253 enable-method = "psci" 253 enable-method = "psci";
254 reg = <0x601>; 254 reg = <0x601>;
255 clocks = <&clockgen QO 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256 d-cache-size = <0x8000 256 d-cache-size = <0x8000>;
257 d-cache-line-size = <6 257 d-cache-line-size = <64>;
258 d-cache-sets = <128>; 258 d-cache-sets = <128>;
259 i-cache-size = <0xC000 259 i-cache-size = <0xC000>;
260 i-cache-line-size = <6 260 i-cache-line-size = <64>;
261 i-cache-sets = <192>; 261 i-cache-sets = <192>;
262 next-level-cache = <&c 262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cp 263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>; 264 #cooling-cells = <2>;
265 }; 265 };
266 266
267 cpu700: cpu@700 { 267 cpu700: cpu@700 {
268 device_type = "cpu"; 268 device_type = "cpu";
269 compatible = "arm,cort 269 compatible = "arm,cortex-a72";
270 enable-method = "psci" 270 enable-method = "psci";
271 reg = <0x700>; 271 reg = <0x700>;
272 clocks = <&clockgen QO 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273 d-cache-size = <0x8000 273 d-cache-size = <0x8000>;
274 d-cache-line-size = <6 274 d-cache-line-size = <64>;
275 d-cache-sets = <128>; 275 d-cache-sets = <128>;
276 i-cache-size = <0xC000 276 i-cache-size = <0xC000>;
277 i-cache-line-size = <6 277 i-cache-line-size = <64>;
278 i-cache-sets = <192>; 278 i-cache-sets = <192>;
279 next-level-cache = <&c 279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cp 280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>; 281 #cooling-cells = <2>;
282 }; 282 };
283 283
284 cpu701: cpu@701 { 284 cpu701: cpu@701 {
285 device_type = "cpu"; 285 device_type = "cpu";
286 compatible = "arm,cort 286 compatible = "arm,cortex-a72";
287 enable-method = "psci" 287 enable-method = "psci";
288 reg = <0x701>; 288 reg = <0x701>;
289 clocks = <&clockgen QO 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290 d-cache-size = <0x8000 290 d-cache-size = <0x8000>;
291 d-cache-line-size = <6 291 d-cache-line-size = <64>;
292 d-cache-sets = <128>; 292 d-cache-sets = <128>;
293 i-cache-size = <0xC000 293 i-cache-size = <0xC000>;
294 i-cache-line-size = <6 294 i-cache-line-size = <64>;
295 i-cache-sets = <192>; 295 i-cache-sets = <192>;
296 next-level-cache = <&c 296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cp 297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>; 298 #cooling-cells = <2>;
299 }; 299 };
300 300
301 cluster0_l2: l2-cache0 { 301 cluster0_l2: l2-cache0 {
302 compatible = "cache"; 302 compatible = "cache";
303 cache-unified; 303 cache-unified;
304 cache-size = <0x100000 304 cache-size = <0x100000>;
305 cache-line-size = <64> 305 cache-line-size = <64>;
306 cache-sets = <1024>; 306 cache-sets = <1024>;
307 cache-level = <2>; 307 cache-level = <2>;
308 }; 308 };
309 309
310 cluster1_l2: l2-cache1 { 310 cluster1_l2: l2-cache1 {
311 compatible = "cache"; 311 compatible = "cache";
312 cache-unified; 312 cache-unified;
313 cache-size = <0x100000 313 cache-size = <0x100000>;
314 cache-line-size = <64> 314 cache-line-size = <64>;
315 cache-sets = <1024>; 315 cache-sets = <1024>;
316 cache-level = <2>; 316 cache-level = <2>;
317 }; 317 };
318 318
319 cluster2_l2: l2-cache2 { 319 cluster2_l2: l2-cache2 {
320 compatible = "cache"; 320 compatible = "cache";
321 cache-unified; 321 cache-unified;
322 cache-size = <0x100000 322 cache-size = <0x100000>;
323 cache-line-size = <64> 323 cache-line-size = <64>;
324 cache-sets = <1024>; 324 cache-sets = <1024>;
325 cache-level = <2>; 325 cache-level = <2>;
326 }; 326 };
327 327
328 cluster3_l2: l2-cache3 { 328 cluster3_l2: l2-cache3 {
329 compatible = "cache"; 329 compatible = "cache";
330 cache-unified; 330 cache-unified;
331 cache-size = <0x100000 331 cache-size = <0x100000>;
332 cache-line-size = <64> 332 cache-line-size = <64>;
333 cache-sets = <1024>; 333 cache-sets = <1024>;
334 cache-level = <2>; 334 cache-level = <2>;
335 }; 335 };
336 336
337 cluster4_l2: l2-cache4 { 337 cluster4_l2: l2-cache4 {
338 compatible = "cache"; 338 compatible = "cache";
339 cache-unified; 339 cache-unified;
340 cache-size = <0x100000 340 cache-size = <0x100000>;
341 cache-line-size = <64> 341 cache-line-size = <64>;
342 cache-sets = <1024>; 342 cache-sets = <1024>;
343 cache-level = <2>; 343 cache-level = <2>;
344 }; 344 };
345 345
346 cluster5_l2: l2-cache5 { 346 cluster5_l2: l2-cache5 {
347 compatible = "cache"; 347 compatible = "cache";
348 cache-unified; 348 cache-unified;
349 cache-size = <0x100000 349 cache-size = <0x100000>;
350 cache-line-size = <64> 350 cache-line-size = <64>;
351 cache-sets = <1024>; 351 cache-sets = <1024>;
352 cache-level = <2>; 352 cache-level = <2>;
353 }; 353 };
354 354
355 cluster6_l2: l2-cache6 { 355 cluster6_l2: l2-cache6 {
356 compatible = "cache"; 356 compatible = "cache";
357 cache-unified; 357 cache-unified;
358 cache-size = <0x100000 358 cache-size = <0x100000>;
359 cache-line-size = <64> 359 cache-line-size = <64>;
360 cache-sets = <1024>; 360 cache-sets = <1024>;
361 cache-level = <2>; 361 cache-level = <2>;
362 }; 362 };
363 363
364 cluster7_l2: l2-cache7 { 364 cluster7_l2: l2-cache7 {
365 compatible = "cache"; 365 compatible = "cache";
366 cache-unified; 366 cache-unified;
367 cache-size = <0x100000 367 cache-size = <0x100000>;
368 cache-line-size = <64> 368 cache-line-size = <64>;
369 cache-sets = <1024>; 369 cache-sets = <1024>;
370 cache-level = <2>; 370 cache-level = <2>;
371 }; 371 };
372 372
373 cpu_pw15: cpu-pw15 { 373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle 374 compatible = "arm,idle-state";
375 idle-state-name = "PW1 375 idle-state-name = "PW15";
376 arm,psci-suspend-param 376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <20 377 entry-latency-us = <2000>;
378 exit-latency-us = <200 378 exit-latency-us = <2000>;
379 min-residency-us = <60 379 min-residency-us = <6000>;
380 }; 380 };
381 }; 381 };
382 382
383 gic: interrupt-controller@6000000 { 383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3"; 384 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x1000 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x20 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
387 387 // SGI_base)
388 <0x0 0x0c0c0000 0 0x20 388 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x10 389 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20 390 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>; 391 #interrupt-cells = <3>;
392 #address-cells = <2>; 392 #address-cells = <2>;
393 #size-cells = <2>; 393 #size-cells = <2>;
394 ranges; 394 ranges;
395 interrupt-controller; 395 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TY 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
397 397
398 its: msi-controller@6020000 { 398 its: msi-controller@6020000 {
399 compatible = "arm,gic- 399 compatible = "arm,gic-v3-its";
400 msi-controller; 400 msi-controller;
401 #msi-cells = <1>; <<
402 reg = <0x0 0x6020000 0 401 reg = <0x0 0x6020000 0 0x20000>;
403 }; 402 };
404 }; 403 };
405 404
406 timer { 405 timer {
407 compatible = "arm,armv8-timer" 406 compatible = "arm,armv8-timer";
408 interrupts = <GIC_PPI 13 IRQ_T 407 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 14 IRQ_T 408 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 11 IRQ_T 409 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_PPI 10 IRQ_T 410 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
412 }; 411 };
413 412
414 pmu { 413 pmu {
415 compatible = "arm,cortex-a72-p 414 compatible = "arm,cortex-a72-pmu";
416 interrupts = <GIC_PPI 7 IRQ_TY 415 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
417 }; 416 };
418 417
419 psci { 418 psci {
420 compatible = "arm,psci-0.2"; 419 compatible = "arm,psci-0.2";
421 method = "smc"; 420 method = "smc";
422 }; 421 };
423 422
424 memory@80000000 { 423 memory@80000000 {
425 // DRAM space - 1, size : 2 GB 424 // DRAM space - 1, size : 2 GB DRAM
426 device_type = "memory"; 425 device_type = "memory";
427 reg = <0x00000000 0x80000000 0 426 reg = <0x00000000 0x80000000 0 0x80000000>;
428 }; 427 };
429 428
430 ddr1: memory-controller@1080000 { 429 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory 430 compatible = "fsl,qoriq-memory-controller";
432 reg = <0x0 0x1080000 0x0 0x100 431 reg = <0x0 0x1080000 0x0 0x1000>;
433 interrupts = <GIC_SPI 17 IRQ_T 432 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
434 little-endian; 433 little-endian;
435 }; 434 };
436 435
437 ddr2: memory-controller@1090000 { 436 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory 437 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1090000 0x0 0x100 438 reg = <0x0 0x1090000 0x0 0x1000>;
440 interrupts = <GIC_SPI 18 IRQ_T 439 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
441 little-endian; 440 little-endian;
442 }; 441 };
443 442
444 // One clock unit-sysclk node which bo 443 // One clock unit-sysclk node which bootloader require during DT fix-up
445 sysclk: sysclk { 444 sysclk: sysclk {
446 compatible = "fixed-clock"; 445 compatible = "fixed-clock";
447 #clock-cells = <0>; 446 #clock-cells = <0>;
448 clock-frequency = <100000000>; 447 clock-frequency = <100000000>; // fixed up by bootloader
449 clock-output-names = "sysclk"; 448 clock-output-names = "sysclk";
450 }; 449 };
451 450
452 thermal-zones { 451 thermal-zones {
453 cluster6-7-thermal { !! 452 cluster6-7 {
454 polling-delay-passive 453 polling-delay-passive = <1000>;
455 polling-delay = <5000> 454 polling-delay = <5000>;
456 thermal-sensors = <&tm 455 thermal-sensors = <&tmu 0>;
457 456
458 trips { 457 trips {
459 cluster6_7_ale 458 cluster6_7_alert: cluster6-7-alert {
460 temper 459 temperature = <85000>;
461 hyster 460 hysteresis = <2000>;
462 type = 461 type = "passive";
463 }; 462 };
464 463
465 cluster6_7_cri 464 cluster6_7_crit: cluster6-7-crit {
466 temper 465 temperature = <95000>;
467 hyster 466 hysteresis = <2000>;
468 type = 467 type = "critical";
469 }; 468 };
470 }; 469 };
471 470
472 cooling-maps { 471 cooling-maps {
473 map0 { 472 map0 {
474 trip = 473 trip = <&cluster6_7_alert>;
475 coolin 474 cooling-device =
476 475 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 476 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 477 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 478 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 479 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 480 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 481 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
483 482 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
484 483 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
485 484 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
486 485 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
487 486 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
488 487 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 488 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 489 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 490 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
492 }; 491 };
493 }; 492 };
494 }; 493 };
495 494
496 ddr-ctrl5-thermal { !! 495 ddr-cluster5 {
497 polling-delay-passive 496 polling-delay-passive = <1000>;
498 polling-delay = <5000> 497 polling-delay = <5000>;
499 thermal-sensors = <&tm 498 thermal-sensors = <&tmu 1>;
500 499
501 trips { 500 trips {
502 ddr-cluster5-a 501 ddr-cluster5-alert {
503 temper 502 temperature = <85000>;
504 hyster 503 hysteresis = <2000>;
505 type = 504 type = "passive";
506 }; 505 };
507 506
508 ddr-cluster5-c 507 ddr-cluster5-crit {
509 temper 508 temperature = <95000>;
510 hyster 509 hysteresis = <2000>;
511 type = 510 type = "critical";
512 }; 511 };
513 }; 512 };
514 }; 513 };
515 514
516 wriop-thermal { !! 515 wriop {
517 polling-delay-passive 516 polling-delay-passive = <1000>;
518 polling-delay = <5000> 517 polling-delay = <5000>;
519 thermal-sensors = <&tm 518 thermal-sensors = <&tmu 2>;
520 519
521 trips { 520 trips {
522 wriop-alert { 521 wriop-alert {
523 temper 522 temperature = <85000>;
524 hyster 523 hysteresis = <2000>;
525 type = 524 type = "passive";
526 }; 525 };
527 526
528 wriop-crit { 527 wriop-crit {
529 temper 528 temperature = <95000>;
530 hyster 529 hysteresis = <2000>;
531 type = 530 type = "critical";
532 }; 531 };
533 }; 532 };
534 }; 533 };
535 534
536 dce-thermal { !! 535 dce-qbman-hsio2 {
537 polling-delay-passive 536 polling-delay-passive = <1000>;
538 polling-delay = <5000> 537 polling-delay = <5000>;
539 thermal-sensors = <&tm 538 thermal-sensors = <&tmu 3>;
540 539
541 trips { 540 trips {
542 dce-qbman-aler 541 dce-qbman-alert {
543 temper 542 temperature = <85000>;
544 hyster 543 hysteresis = <2000>;
545 type = 544 type = "passive";
546 }; 545 };
547 546
548 dce-qbman-crit 547 dce-qbman-crit {
549 temper 548 temperature = <95000>;
550 hyster 549 hysteresis = <2000>;
551 type = 550 type = "critical";
552 }; 551 };
553 }; 552 };
554 }; 553 };
555 554
556 ccn-thermal { !! 555 ccn-dpaa-tbu {
557 polling-delay-passive 556 polling-delay-passive = <1000>;
558 polling-delay = <5000> 557 polling-delay = <5000>;
559 thermal-sensors = <&tm 558 thermal-sensors = <&tmu 4>;
560 559
561 trips { 560 trips {
562 ccn-dpaa-alert 561 ccn-dpaa-alert {
563 temper 562 temperature = <85000>;
564 hyster 563 hysteresis = <2000>;
565 type = 564 type = "passive";
566 }; 565 };
567 566
568 ccn-dpaa-crit 567 ccn-dpaa-crit {
569 temper 568 temperature = <95000>;
570 hyster 569 hysteresis = <2000>;
571 type = 570 type = "critical";
572 }; 571 };
573 }; 572 };
574 }; 573 };
575 574
576 cluster4-thermal { !! 575 cluster4-hsio3 {
577 polling-delay-passive 576 polling-delay-passive = <1000>;
578 polling-delay = <5000> 577 polling-delay = <5000>;
579 thermal-sensors = <&tm 578 thermal-sensors = <&tmu 5>;
580 579
581 trips { 580 trips {
582 clust4-hsio3-a 581 clust4-hsio3-alert {
583 temper 582 temperature = <85000>;
584 hyster 583 hysteresis = <2000>;
585 type = 584 type = "passive";
586 }; 585 };
587 586
588 clust4-hsio3-c 587 clust4-hsio3-crit {
589 temper 588 temperature = <95000>;
590 hyster 589 hysteresis = <2000>;
591 type = 590 type = "critical";
592 }; 591 };
593 }; 592 };
594 }; 593 };
595 594
596 cluster2-3-thermal { !! 595 cluster2-3 {
597 polling-delay-passive 596 polling-delay-passive = <1000>;
598 polling-delay = <5000> 597 polling-delay = <5000>;
599 thermal-sensors = <&tm 598 thermal-sensors = <&tmu 6>;
600 599
601 trips { 600 trips {
602 cluster2-3-ale 601 cluster2-3-alert {
603 temper 602 temperature = <85000>;
604 hyster 603 hysteresis = <2000>;
605 type = 604 type = "passive";
606 }; 605 };
607 606
608 cluster2-3-cri 607 cluster2-3-crit {
609 temper 608 temperature = <95000>;
610 hyster 609 hysteresis = <2000>;
611 type = 610 type = "critical";
612 }; 611 };
613 }; 612 };
614 }; 613 };
615 }; 614 };
616 615
617 soc { 616 soc {
618 compatible = "simple-bus"; 617 compatible = "simple-bus";
619 #address-cells = <2>; 618 #address-cells = <2>;
620 #size-cells = <2>; 619 #size-cells = <2>;
621 ranges; 620 ranges;
622 dma-ranges = <0x0 0x0 0x0 0x0 621 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
623 622
624 serdes_1: phy@1ea0000 { 623 serdes_1: phy@1ea0000 {
625 compatible = "fsl,lynx 624 compatible = "fsl,lynx-28g";
626 reg = <0x0 0x1ea0000 0 625 reg = <0x0 0x1ea0000 0x0 0x1e30>;
627 #phy-cells = <1>; 626 #phy-cells = <1>;
628 }; 627 };
629 628
630 serdes_2: phy@1eb0000 { 629 serdes_2: phy@1eb0000 {
631 compatible = "fsl,lynx 630 compatible = "fsl,lynx-28g";
632 reg = <0x0 0x1eb0000 0 631 reg = <0x0 0x1eb0000 0x0 0x1e30>;
633 #phy-cells = <1>; 632 #phy-cells = <1>;
634 status = "disabled"; 633 status = "disabled";
635 }; 634 };
636 635
637 crypto: crypto@8000000 { 636 crypto: crypto@8000000 {
638 compatible = "fsl,sec- 637 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 fsl,sec-era = <10>; 638 fsl,sec-era = <10>;
640 #address-cells = <1>; 639 #address-cells = <1>;
641 #size-cells = <1>; 640 #size-cells = <1>;
642 ranges = <0x0 0x00 0x8 641 ranges = <0x0 0x00 0x8000000 0x100000>;
643 reg = <0x00 0x8000000 642 reg = <0x00 0x8000000 0x0 0x100000>;
644 interrupts = <GIC_SPI 643 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
645 dma-coherent; 644 dma-coherent;
646 status = "disabled"; 645 status = "disabled";
647 646
648 sec_jr0: jr@10000 { 647 sec_jr0: jr@10000 {
649 compatible = " 648 compatible = "fsl,sec-v5.0-job-ring",
650 " 649 "fsl,sec-v4.0-job-ring";
651 reg = <0x10000 650 reg = <0x10000 0x10000>;
652 interrupts = < 651 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
653 }; 652 };
654 653
655 sec_jr1: jr@20000 { 654 sec_jr1: jr@20000 {
656 compatible = " 655 compatible = "fsl,sec-v5.0-job-ring",
657 " 656 "fsl,sec-v4.0-job-ring";
658 reg = <0x20000 657 reg = <0x20000 0x10000>;
659 interrupts = < 658 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
660 }; 659 };
661 660
662 sec_jr2: jr@30000 { 661 sec_jr2: jr@30000 {
663 compatible = " 662 compatible = "fsl,sec-v5.0-job-ring",
664 " 663 "fsl,sec-v4.0-job-ring";
665 reg = <0x30000 664 reg = <0x30000 0x10000>;
666 interrupts = < 665 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
667 }; 666 };
668 667
669 sec_jr3: jr@40000 { 668 sec_jr3: jr@40000 {
670 compatible = " 669 compatible = "fsl,sec-v5.0-job-ring",
671 " 670 "fsl,sec-v4.0-job-ring";
672 reg = <0x40000 671 reg = <0x40000 0x10000>;
673 interrupts = < 672 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
674 }; 673 };
675 }; 674 };
676 675
677 clockgen: clock-controller@130 676 clockgen: clock-controller@1300000 {
678 compatible = "fsl,lx21 677 compatible = "fsl,lx2160a-clockgen";
679 reg = <0 0x1300000 0 0 678 reg = <0 0x1300000 0 0xa0000>;
680 #clock-cells = <2>; 679 #clock-cells = <2>;
681 clocks = <&sysclk>; 680 clocks = <&sysclk>;
682 }; 681 };
683 682
684 dcfg: syscon@1e00000 { 683 dcfg: syscon@1e00000 {
685 compatible = "fsl,lx21 684 compatible = "fsl,lx2160a-dcfg", "syscon";
686 reg = <0x0 0x1e00000 0 685 reg = <0x0 0x1e00000 0x0 0x10000>;
687 little-endian; 686 little-endian;
688 }; 687 };
689 688
690 sfp: efuse@1e80000 { 689 sfp: efuse@1e80000 {
691 compatible = "fsl,ls10 690 compatible = "fsl,ls1028a-sfp";
692 reg = <0x0 0x1e80000 0 691 reg = <0x0 0x1e80000 0x0 0x10000>;
693 clocks = <&clockgen QO 692 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
694 QO 693 QORIQ_CLK_PLL_DIV(4)>;
695 clock-names = "sfp"; 694 clock-names = "sfp";
696 }; 695 };
697 696
698 isc: syscon@1f70000 { 697 isc: syscon@1f70000 {
699 compatible = "fsl,lx21 698 compatible = "fsl,lx2160a-isc", "syscon";
700 reg = <0x0 0x1f70000 0 699 reg = <0x0 0x1f70000 0x0 0x10000>;
701 little-endian; 700 little-endian;
702 #address-cells = <1>; 701 #address-cells = <1>;
703 #size-cells = <1>; 702 #size-cells = <1>;
704 ranges = <0x0 0x0 0x1f 703 ranges = <0x0 0x0 0x1f70000 0x10000>;
705 704
706 extirq: interrupt-cont 705 extirq: interrupt-controller@14 {
707 compatible = " 706 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
708 #interrupt-cel 707 #interrupt-cells = <2>;
709 #address-cells 708 #address-cells = <0>;
710 interrupt-cont 709 interrupt-controller;
711 reg = <0x14 4> 710 reg = <0x14 4>;
712 interrupt-map 711 interrupt-map =
713 <0 0 & 712 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
714 <1 0 & 713 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
715 <2 0 & 714 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
716 <3 0 & 715 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
717 <4 0 & 716 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
718 <5 0 & 717 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
719 <6 0 & 718 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
720 <7 0 & 719 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
721 <8 0 & 720 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
722 <9 0 & 721 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
723 <10 0 722 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
724 <11 0 723 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-map- 724 interrupt-map-mask = <0xf 0x0>;
726 }; 725 };
727 }; 726 };
728 727
729 tmu: tmu@1f80000 { 728 tmu: tmu@1f80000 {
730 compatible = "fsl,qori 729 compatible = "fsl,qoriq-tmu";
731 reg = <0x0 0x1f80000 0 730 reg = <0x0 0x1f80000 0x0 0x10000>;
732 interrupts = <GIC_SPI 731 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
733 fsl,tmu-range = <0x800 732 fsl,tmu-range = <0x800000e6 0x8001017d>;
734 fsl,tmu-calibration = 733 fsl,tmu-calibration =
735 /* Calibration 734 /* Calibration data group 1 */
736 <0x00000000 0x !! 735 <0x00000000 0x00000035
737 /* Calibration 736 /* Calibration data group 2 */
738 <0x00000001 0x !! 737 0x00000001 0x00000154>;
739 little-endian; 738 little-endian;
740 #thermal-sensor-cells 739 #thermal-sensor-cells = <1>;
741 }; 740 };
742 741
743 i2c0: i2c@2000000 { 742 i2c0: i2c@2000000 {
744 compatible = "fsl,vf61 743 compatible = "fsl,vf610-i2c";
745 #address-cells = <1>; 744 #address-cells = <1>;
746 #size-cells = <0>; 745 #size-cells = <0>;
747 reg = <0x0 0x2000000 0 746 reg = <0x0 0x2000000 0x0 0x10000>;
748 interrupts = <GIC_SPI 747 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
749 clock-names = "ipg"; !! 748 clock-names = "i2c";
750 clocks = <&clockgen QO 749 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
751 QO 750 QORIQ_CLK_PLL_DIV(16)>;
752 pinctrl-names = "defau !! 751 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
753 pinctrl-0 = <&i2c0_scl <<
754 pinctrl-1 = <&i2c0_scl <<
755 scl-gpios = <&gpio0 3 <<
756 status = "disabled"; 752 status = "disabled";
757 }; 753 };
758 754
759 i2c1: i2c@2010000 { 755 i2c1: i2c@2010000 {
760 compatible = "fsl,vf61 756 compatible = "fsl,vf610-i2c";
761 #address-cells = <1>; 757 #address-cells = <1>;
762 #size-cells = <0>; 758 #size-cells = <0>;
763 reg = <0x0 0x2010000 0 759 reg = <0x0 0x2010000 0x0 0x10000>;
764 interrupts = <GIC_SPI 760 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
765 clock-names = "ipg"; !! 761 clock-names = "i2c";
766 clocks = <&clockgen QO 762 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
767 QO 763 QORIQ_CLK_PLL_DIV(16)>;
768 pinctrl-names = "defau <<
769 pinctrl-0 = <&i2c1_scl <<
770 pinctrl-1 = <&i2c1_scl <<
771 scl-gpios = <&gpio0 31 <<
772 status = "disabled"; 764 status = "disabled";
773 }; 765 };
774 766
775 i2c2: i2c@2020000 { 767 i2c2: i2c@2020000 {
776 compatible = "fsl,vf61 768 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>; 769 #address-cells = <1>;
778 #size-cells = <0>; 770 #size-cells = <0>;
779 reg = <0x0 0x2020000 0 771 reg = <0x0 0x2020000 0x0 0x10000>;
780 interrupts = <GIC_SPI 772 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
781 clock-names = "ipg"; !! 773 clock-names = "i2c";
782 clocks = <&clockgen QO 774 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
783 QO 775 QORIQ_CLK_PLL_DIV(16)>;
784 pinctrl-names = "defau <<
785 pinctrl-0 = <&i2c2_scl <<
786 pinctrl-1 = <&i2c2_scl <<
787 scl-gpios = <&gpio0 29 <<
788 status = "disabled"; 776 status = "disabled";
789 }; 777 };
790 778
791 i2c3: i2c@2030000 { 779 i2c3: i2c@2030000 {
792 compatible = "fsl,vf61 780 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>; 781 #address-cells = <1>;
794 #size-cells = <0>; 782 #size-cells = <0>;
795 reg = <0x0 0x2030000 0 783 reg = <0x0 0x2030000 0x0 0x10000>;
796 interrupts = <GIC_SPI 784 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
797 clock-names = "ipg"; !! 785 clock-names = "i2c";
798 clocks = <&clockgen QO 786 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
799 QO 787 QORIQ_CLK_PLL_DIV(16)>;
800 pinctrl-names = "defau <<
801 pinctrl-0 = <&i2c3_scl <<
802 pinctrl-1 = <&i2c3_scl <<
803 scl-gpios = <&gpio0 27 <<
804 status = "disabled"; 788 status = "disabled";
805 }; 789 };
806 790
807 i2c4: i2c@2040000 { 791 i2c4: i2c@2040000 {
808 compatible = "fsl,vf61 792 compatible = "fsl,vf610-i2c";
809 #address-cells = <1>; 793 #address-cells = <1>;
810 #size-cells = <0>; 794 #size-cells = <0>;
811 reg = <0x0 0x2040000 0 795 reg = <0x0 0x2040000 0x0 0x10000>;
812 interrupts = <GIC_SPI 796 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
813 clock-names = "ipg"; !! 797 clock-names = "i2c";
814 clocks = <&clockgen QO 798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
815 QO 799 QORIQ_CLK_PLL_DIV(16)>;
816 pinctrl-names = "defau !! 800 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
817 pinctrl-0 = <&i2c4_scl <<
818 pinctrl-1 = <&i2c4_scl <<
819 scl-gpios = <&gpio0 25 <<
820 status = "disabled"; 801 status = "disabled";
821 }; 802 };
822 803
823 i2c5: i2c@2050000 { 804 i2c5: i2c@2050000 {
824 compatible = "fsl,vf61 805 compatible = "fsl,vf610-i2c";
825 #address-cells = <1>; 806 #address-cells = <1>;
826 #size-cells = <0>; 807 #size-cells = <0>;
827 reg = <0x0 0x2050000 0 808 reg = <0x0 0x2050000 0x0 0x10000>;
828 interrupts = <GIC_SPI 809 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
829 clock-names = "ipg"; !! 810 clock-names = "i2c";
830 clocks = <&clockgen QO 811 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
831 QO 812 QORIQ_CLK_PLL_DIV(16)>;
832 pinctrl-names = "defau <<
833 pinctrl-0 = <&i2c5_scl <<
834 pinctrl-1 = <&i2c5_scl <<
835 scl-gpios = <&gpio0 23 <<
836 status = "disabled"; 813 status = "disabled";
837 }; 814 };
838 815
839 i2c6: i2c@2060000 { 816 i2c6: i2c@2060000 {
840 compatible = "fsl,vf61 817 compatible = "fsl,vf610-i2c";
841 #address-cells = <1>; 818 #address-cells = <1>;
842 #size-cells = <0>; 819 #size-cells = <0>;
843 reg = <0x0 0x2060000 0 820 reg = <0x0 0x2060000 0x0 0x10000>;
844 interrupts = <GIC_SPI 821 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "ipg"; !! 822 clock-names = "i2c";
846 clocks = <&clockgen QO 823 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
847 QO 824 QORIQ_CLK_PLL_DIV(16)>;
848 pinctrl-names = "defau <<
849 pinctrl-0 = <&i2c6_scl <<
850 pinctrl-1 = <&i2c6_scl <<
851 scl-gpios = <&gpio1 16 <<
852 status = "disabled"; 825 status = "disabled";
853 }; 826 };
854 827
855 i2c7: i2c@2070000 { 828 i2c7: i2c@2070000 {
856 compatible = "fsl,vf61 829 compatible = "fsl,vf610-i2c";
857 #address-cells = <1>; 830 #address-cells = <1>;
858 #size-cells = <0>; 831 #size-cells = <0>;
859 reg = <0x0 0x2070000 0 832 reg = <0x0 0x2070000 0x0 0x10000>;
860 interrupts = <GIC_SPI 833 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
861 clock-names = "ipg"; !! 834 clock-names = "i2c";
862 clocks = <&clockgen QO 835 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
863 QO 836 QORIQ_CLK_PLL_DIV(16)>;
864 pinctrl-names = "defau <<
865 pinctrl-0 = <&i2c7_scl <<
866 pinctrl-1 = <&i2c7_scl <<
867 scl-gpios = <&gpio1 18 <<
868 status = "disabled"; 837 status = "disabled";
869 }; 838 };
870 839
871 fspi: spi@20c0000 { 840 fspi: spi@20c0000 {
872 compatible = "nxp,lx21 841 compatible = "nxp,lx2160a-fspi";
873 #address-cells = <1>; 842 #address-cells = <1>;
874 #size-cells = <0>; 843 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0 844 reg = <0x0 0x20c0000 0x0 0x10000>,
876 <0x0 0x20000000 845 <0x0 0x20000000 0x0 0x10000000>;
877 reg-names = "fspi_base 846 reg-names = "fspi_base", "fspi_mmap";
878 interrupts = <GIC_SPI 847 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clockgen QO 848 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
880 QO 849 QORIQ_CLK_PLL_DIV(4)>,
881 <&clockgen QO 850 <&clockgen QORIQ_CLK_PLATFORM_PLL
882 QO 851 QORIQ_CLK_PLL_DIV(4)>;
883 clock-names = "fspi_en 852 clock-names = "fspi_en", "fspi";
884 status = "disabled"; 853 status = "disabled";
885 }; 854 };
886 855
887 dspi0: spi@2100000 { 856 dspi0: spi@2100000 {
888 compatible = "fsl,lx21 857 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
889 #address-cells = <1>; 858 #address-cells = <1>;
890 #size-cells = <0>; 859 #size-cells = <0>;
891 reg = <0x0 0x2100000 0 860 reg = <0x0 0x2100000 0x0 0x10000>;
892 interrupts = <GIC_SPI 861 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clockgen QO 862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
894 QO 863 QORIQ_CLK_PLL_DIV(8)>;
895 clock-names = "dspi"; 864 clock-names = "dspi";
896 spi-num-chipselects = 865 spi-num-chipselects = <5>;
897 bus-num = <0>; 866 bus-num = <0>;
898 status = "disabled"; 867 status = "disabled";
899 }; 868 };
900 869
901 dspi1: spi@2110000 { 870 dspi1: spi@2110000 {
902 compatible = "fsl,lx21 871 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
903 #address-cells = <1>; 872 #address-cells = <1>;
904 #size-cells = <0>; 873 #size-cells = <0>;
905 reg = <0x0 0x2110000 0 874 reg = <0x0 0x2110000 0x0 0x10000>;
906 interrupts = <GIC_SPI 875 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clockgen QO 876 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
908 QO 877 QORIQ_CLK_PLL_DIV(8)>;
909 clock-names = "dspi"; 878 clock-names = "dspi";
910 spi-num-chipselects = 879 spi-num-chipselects = <5>;
911 bus-num = <1>; 880 bus-num = <1>;
912 status = "disabled"; 881 status = "disabled";
913 }; 882 };
914 883
915 dspi2: spi@2120000 { 884 dspi2: spi@2120000 {
916 compatible = "fsl,lx21 885 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
917 #address-cells = <1>; 886 #address-cells = <1>;
918 #size-cells = <0>; 887 #size-cells = <0>;
919 reg = <0x0 0x2120000 0 888 reg = <0x0 0x2120000 0x0 0x10000>;
920 interrupts = <GIC_SPI 889 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clockgen QO 890 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
922 QO 891 QORIQ_CLK_PLL_DIV(8)>;
923 clock-names = "dspi"; 892 clock-names = "dspi";
924 spi-num-chipselects = 893 spi-num-chipselects = <5>;
925 bus-num = <2>; 894 bus-num = <2>;
926 status = "disabled"; 895 status = "disabled";
927 }; 896 };
928 897
929 esdhc0: mmc@2140000 { !! 898 esdhc0: esdhc@2140000 {
930 compatible = "fsl,ls20 !! 899 compatible = "fsl,esdhc";
931 reg = <0x0 0x2140000 0 900 reg = <0x0 0x2140000 0x0 0x10000>;
932 interrupts = <GIC_SPI !! 901 interrupts = <0 28 0x4>; /* Level high type */
933 clocks = <&clockgen QO 902 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
934 QO 903 QORIQ_CLK_PLL_DIV(2)>;
935 dma-coherent; 904 dma-coherent;
936 voltage-ranges = <1800 905 voltage-ranges = <1800 1800 3300 3300>;
937 sdhci,auto-cmd12; 906 sdhci,auto-cmd12;
938 little-endian; 907 little-endian;
939 bus-width = <4>; 908 bus-width = <4>;
940 status = "disabled"; 909 status = "disabled";
941 }; 910 };
942 911
943 esdhc1: mmc@2150000 { !! 912 esdhc1: esdhc@2150000 {
944 compatible = "fsl,ls20 !! 913 compatible = "fsl,esdhc";
945 reg = <0x0 0x2150000 0 914 reg = <0x0 0x2150000 0x0 0x10000>;
946 interrupts = <GIC_SPI !! 915 interrupts = <0 63 0x4>; /* Level high type */
947 clocks = <&clockgen QO 916 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
948 QO 917 QORIQ_CLK_PLL_DIV(2)>;
949 dma-coherent; 918 dma-coherent;
950 voltage-ranges = <1800 919 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12; 920 sdhci,auto-cmd12;
952 broken-cd; 921 broken-cd;
953 little-endian; 922 little-endian;
954 bus-width = <4>; 923 bus-width = <4>;
955 status = "disabled"; 924 status = "disabled";
956 }; 925 };
957 926
958 can0: can@2180000 { 927 can0: can@2180000 {
959 compatible = "fsl,lx21 928 compatible = "fsl,lx2160ar1-flexcan";
960 reg = <0x0 0x2180000 0 929 reg = <0x0 0x2180000 0x0 0x10000>;
961 interrupts = <GIC_SPI 930 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&clockgen QO 931 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
963 QO 932 QORIQ_CLK_PLL_DIV(8)>,
964 <&clockgen QO 933 <&clockgen QORIQ_CLK_SYSCLK 0>;
965 clock-names = "ipg", " 934 clock-names = "ipg", "per";
966 fsl,clk-source = /bits 935 fsl,clk-source = /bits/ 8 <0>;
967 status = "disabled"; 936 status = "disabled";
968 }; 937 };
969 938
970 can1: can@2190000 { 939 can1: can@2190000 {
971 compatible = "fsl,lx21 940 compatible = "fsl,lx2160ar1-flexcan";
972 reg = <0x0 0x2190000 0 941 reg = <0x0 0x2190000 0x0 0x10000>;
973 interrupts = <GIC_SPI 942 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clockgen QO 943 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
975 QO 944 QORIQ_CLK_PLL_DIV(8)>,
976 <&clockgen QO 945 <&clockgen QORIQ_CLK_SYSCLK 0>;
977 clock-names = "ipg", " 946 clock-names = "ipg", "per";
978 fsl,clk-source = /bits 947 fsl,clk-source = /bits/ 8 <0>;
979 status = "disabled"; 948 status = "disabled";
980 }; 949 };
981 950
982 uart0: serial@21c0000 { 951 uart0: serial@21c0000 {
983 compatible = "arm,pl01 !! 952 compatible = "arm,sbsa-uart","arm,pl011";
984 clocks = <&clockgen QO <<
985 QO <<
986 <&clockgen QO <<
987 QO <<
988 clock-names = "uartclk <<
989 reg = <0x0 0x21c0000 0 953 reg = <0x0 0x21c0000 0x0 0x1000>;
990 interrupts = <GIC_SPI 954 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> 955 current-speed = <115200>;
991 status = "disabled"; 956 status = "disabled";
992 }; 957 };
993 958
994 uart1: serial@21d0000 { 959 uart1: serial@21d0000 {
995 compatible = "arm,pl01 !! 960 compatible = "arm,sbsa-uart","arm,pl011";
996 clocks = <&clockgen QO <<
997 QO <<
998 <&clockgen QO <<
999 QO <<
1000 clock-names = "uartcl <<
1001 reg = <0x0 0x21d0000 961 reg = <0x0 0x21d0000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 962 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> 963 current-speed = <115200>;
1003 status = "disabled"; 964 status = "disabled";
1004 }; 965 };
1005 966
1006 uart2: serial@21e0000 { 967 uart2: serial@21e0000 {
1007 compatible = "arm,pl0 !! 968 compatible = "arm,sbsa-uart","arm,pl011";
1008 clocks = <&clockgen Q <<
1009 Q <<
1010 <&clockgen Q <<
1011 Q <<
1012 clock-names = "uartcl <<
1013 reg = <0x0 0x21e0000 969 reg = <0x0 0x21e0000 0x0 0x1000>;
1014 interrupts = <GIC_SPI 970 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
>> 971 current-speed = <115200>;
1015 status = "disabled"; 972 status = "disabled";
1016 }; 973 };
1017 974
1018 uart3: serial@21f0000 { 975 uart3: serial@21f0000 {
1019 compatible = "arm,pl0 !! 976 compatible = "arm,sbsa-uart","arm,pl011";
1020 clocks = <&clockgen Q <<
1021 Q <<
1022 <&clockgen Q <<
1023 Q <<
1024 clock-names = "uartcl <<
1025 reg = <0x0 0x21f0000 977 reg = <0x0 0x21f0000 0x0 0x1000>;
1026 interrupts = <GIC_SPI 978 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
>> 979 current-speed = <115200>;
1027 status = "disabled"; 980 status = "disabled";
1028 }; 981 };
1029 982
1030 gpio0: gpio@2300000 { 983 gpio0: gpio@2300000 {
1031 compatible = "fsl,ls2 !! 984 compatible = "fsl,qoriq-gpio";
1032 reg = <0x0 0x2300000 985 reg = <0x0 0x2300000 0x0 0x10000>;
1033 interrupts = <GIC_SPI 986 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1034 gpio-controller; 987 gpio-controller;
1035 little-endian; 988 little-endian;
1036 #gpio-cells = <2>; 989 #gpio-cells = <2>;
1037 interrupt-controller; 990 interrupt-controller;
1038 #interrupt-cells = <2 991 #interrupt-cells = <2>;
1039 }; 992 };
1040 993
1041 gpio1: gpio@2310000 { 994 gpio1: gpio@2310000 {
1042 compatible = "fsl,ls2 !! 995 compatible = "fsl,qoriq-gpio";
1043 reg = <0x0 0x2310000 996 reg = <0x0 0x2310000 0x0 0x10000>;
1044 interrupts = <GIC_SPI 997 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1045 gpio-controller; 998 gpio-controller;
1046 little-endian; 999 little-endian;
1047 #gpio-cells = <2>; 1000 #gpio-cells = <2>;
1048 interrupt-controller; 1001 interrupt-controller;
1049 #interrupt-cells = <2 1002 #interrupt-cells = <2>;
1050 }; 1003 };
1051 1004
1052 gpio2: gpio@2320000 { 1005 gpio2: gpio@2320000 {
1053 compatible = "fsl,ls2 !! 1006 compatible = "fsl,qoriq-gpio";
1054 reg = <0x0 0x2320000 1007 reg = <0x0 0x2320000 0x0 0x10000>;
1055 interrupts = <GIC_SPI 1008 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1056 gpio-controller; 1009 gpio-controller;
1057 little-endian; 1010 little-endian;
1058 #gpio-cells = <2>; 1011 #gpio-cells = <2>;
1059 interrupt-controller; 1012 interrupt-controller;
1060 #interrupt-cells = <2 1013 #interrupt-cells = <2>;
1061 }; 1014 };
1062 1015
1063 gpio3: gpio@2330000 { 1016 gpio3: gpio@2330000 {
1064 compatible = "fsl,ls2 !! 1017 compatible = "fsl,qoriq-gpio";
1065 reg = <0x0 0x2330000 1018 reg = <0x0 0x2330000 0x0 0x10000>;
1066 interrupts = <GIC_SPI 1019 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1067 gpio-controller; 1020 gpio-controller;
1068 little-endian; 1021 little-endian;
1069 #gpio-cells = <2>; 1022 #gpio-cells = <2>;
1070 interrupt-controller; 1023 interrupt-controller;
1071 #interrupt-cells = <2 1024 #interrupt-cells = <2>;
1072 }; 1025 };
1073 1026
1074 watchdog@23a0000 { 1027 watchdog@23a0000 {
1075 compatible = "arm,sbs 1028 compatible = "arm,sbsa-gwdt";
1076 reg = <0x0 0x23a0000 1029 reg = <0x0 0x23a0000 0 0x1000>,
1077 <0x0 0x2390000 1030 <0x0 0x2390000 0 0x1000>;
1078 interrupts = <GIC_SPI 1031 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1079 timeout-sec = <30>; 1032 timeout-sec = <30>;
1080 }; 1033 };
1081 1034
1082 rcpm: wakeup-controller@1e340 !! 1035 rcpm: power-controller@1e34040 {
1083 compatible = "fsl,lx2 1036 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1084 reg = <0x0 0x1e34040 1037 reg = <0x0 0x1e34040 0x0 0x1c>;
1085 #fsl,rcpm-wakeup-cell 1038 #fsl,rcpm-wakeup-cells = <7>;
1086 little-endian; 1039 little-endian;
1087 }; 1040 };
1088 1041
1089 ftm_alarm0: rtc@2800000 { !! 1042 ftm_alarm0: timer@2800000 {
1090 compatible = "fsl,lx2 1043 compatible = "fsl,lx2160a-ftm-alarm";
1091 reg = <0x0 0x2800000 1044 reg = <0x0 0x2800000 0x0 0x10000>;
1092 fsl,rcpm-wakeup = <&r 1045 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1093 interrupts = <GIC_SPI 1046 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1094 }; 1047 };
1095 1048
1096 usb0: usb@3100000 { 1049 usb0: usb@3100000 {
1097 compatible = "snps,dw 1050 compatible = "snps,dwc3";
1098 reg = <0x0 0x3100000 1051 reg = <0x0 0x3100000 0x0 0x10000>;
1099 interrupts = <GIC_SPI 1052 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1100 dr_mode = "host"; 1053 dr_mode = "host";
1101 snps,quirk-frame-leng 1054 snps,quirk-frame-length-adjustment = <0x20>;
1102 usb3-lpm-capable; 1055 usb3-lpm-capable;
1103 snps,dis_rxdet_inp3_q 1056 snps,dis_rxdet_inp3_quirk;
1104 snps,incr-burst-type- 1057 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1105 status = "disabled"; 1058 status = "disabled";
1106 }; 1059 };
1107 1060
1108 usb1: usb@3110000 { 1061 usb1: usb@3110000 {
1109 compatible = "snps,dw 1062 compatible = "snps,dwc3";
1110 reg = <0x0 0x3110000 1063 reg = <0x0 0x3110000 0x0 0x10000>;
1111 interrupts = <GIC_SPI 1064 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1112 dr_mode = "host"; 1065 dr_mode = "host";
1113 snps,quirk-frame-leng 1066 snps,quirk-frame-length-adjustment = <0x20>;
1114 usb3-lpm-capable; 1067 usb3-lpm-capable;
1115 snps,dis_rxdet_inp3_q 1068 snps,dis_rxdet_inp3_quirk;
1116 snps,incr-burst-type- 1069 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1117 status = "disabled"; 1070 status = "disabled";
1118 }; 1071 };
1119 1072
1120 sata0: sata@3200000 { 1073 sata0: sata@3200000 {
1121 compatible = "fsl,lx2 1074 compatible = "fsl,lx2160a-ahci";
1122 reg = <0x0 0x3200000 1075 reg = <0x0 0x3200000 0x0 0x10000>,
1123 <0x7 0x100520 0 1076 <0x7 0x100520 0x0 0x4>;
1124 reg-names = "ahci", " 1077 reg-names = "ahci", "sata-ecc";
1125 interrupts = <GIC_SPI 1078 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clockgen Q 1079 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1127 Q 1080 QORIQ_CLK_PLL_DIV(4)>;
1128 dma-coherent; 1081 dma-coherent;
1129 status = "disabled"; 1082 status = "disabled";
1130 }; 1083 };
1131 1084
1132 sata1: sata@3210000 { 1085 sata1: sata@3210000 {
1133 compatible = "fsl,lx2 1086 compatible = "fsl,lx2160a-ahci";
1134 reg = <0x0 0x3210000 1087 reg = <0x0 0x3210000 0x0 0x10000>,
1135 <0x7 0x100520 0 1088 <0x7 0x100520 0x0 0x4>;
1136 reg-names = "ahci", " 1089 reg-names = "ahci", "sata-ecc";
1137 interrupts = <GIC_SPI 1090 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1138 clocks = <&clockgen Q 1091 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1139 Q 1092 QORIQ_CLK_PLL_DIV(4)>;
1140 dma-coherent; 1093 dma-coherent;
1141 status = "disabled"; 1094 status = "disabled";
1142 }; 1095 };
1143 1096
1144 sata2: sata@3220000 { 1097 sata2: sata@3220000 {
1145 compatible = "fsl,lx2 1098 compatible = "fsl,lx2160a-ahci";
1146 reg = <0x0 0x3220000 1099 reg = <0x0 0x3220000 0x0 0x10000>,
1147 <0x7 0x100520 0 1100 <0x7 0x100520 0x0 0x4>;
1148 reg-names = "ahci", " 1101 reg-names = "ahci", "sata-ecc";
1149 interrupts = <GIC_SPI 1102 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clockgen Q 1103 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1151 Q 1104 QORIQ_CLK_PLL_DIV(4)>;
1152 dma-coherent; 1105 dma-coherent;
1153 status = "disabled"; 1106 status = "disabled";
1154 }; 1107 };
1155 1108
1156 sata3: sata@3230000 { 1109 sata3: sata@3230000 {
1157 compatible = "fsl,lx2 1110 compatible = "fsl,lx2160a-ahci";
1158 reg = <0x0 0x3230000 1111 reg = <0x0 0x3230000 0x0 0x10000>,
1159 <0x7 0x100520 0 1112 <0x7 0x100520 0x0 0x4>;
1160 reg-names = "ahci", " 1113 reg-names = "ahci", "sata-ecc";
1161 interrupts = <GIC_SPI 1114 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clockgen Q 1115 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1163 Q 1116 QORIQ_CLK_PLL_DIV(4)>;
1164 dma-coherent; 1117 dma-coherent;
1165 status = "disabled"; 1118 status = "disabled";
1166 }; 1119 };
1167 1120
1168 pcie1: pcie@3400000 { 1121 pcie1: pcie@3400000 {
1169 compatible = "fsl,lx2 1122 compatible = "fsl,lx2160a-pcie";
1170 reg = <0x00 0x0340000 1123 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1171 <0x80 0x0000000 1124 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1172 reg-names = "csr_axi_ 1125 reg-names = "csr_axi_slave", "config_axi_slave";
1173 interrupts = <GIC_SPI 1126 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1174 <GIC_SPI 1127 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1175 <GIC_SPI 1128 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1176 interrupt-names = "ae 1129 interrupt-names = "aer", "pme", "intr";
1177 #address-cells = <3>; 1130 #address-cells = <3>;
1178 #size-cells = <2>; 1131 #size-cells = <2>;
1179 device_type = "pci"; 1132 device_type = "pci";
1180 dma-coherent; 1133 dma-coherent;
1181 apio-wins = <8>; 1134 apio-wins = <8>;
1182 ppio-wins = <8>; 1135 ppio-wins = <8>;
1183 bus-range = <0x0 0xff 1136 bus-range = <0x0 0xff>;
1184 ranges = <0x82000000 1137 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1185 msi-parent = <&its 0> !! 1138 msi-parent = <&its>;
1186 #interrupt-cells = <1 1139 #interrupt-cells = <1>;
1187 interrupt-map-mask = 1140 interrupt-map-mask = <0 0 0 7>;
1188 interrupt-map = <0000 1141 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1189 <0000 1142 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1190 <0000 1143 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1191 <0000 1144 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1192 iommu-map = <0 &smmu 1145 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1193 status = "disabled"; 1146 status = "disabled";
1194 }; 1147 };
1195 1148
1196 pcie2: pcie@3500000 { 1149 pcie2: pcie@3500000 {
1197 compatible = "fsl,lx2 1150 compatible = "fsl,lx2160a-pcie";
1198 reg = <0x00 0x0350000 1151 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1199 <0x88 0x0000000 1152 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1200 reg-names = "csr_axi_ 1153 reg-names = "csr_axi_slave", "config_axi_slave";
1201 interrupts = <GIC_SPI 1154 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1202 <GIC_SPI 1155 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1203 <GIC_SPI 1156 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1204 interrupt-names = "ae 1157 interrupt-names = "aer", "pme", "intr";
1205 #address-cells = <3>; 1158 #address-cells = <3>;
1206 #size-cells = <2>; 1159 #size-cells = <2>;
1207 device_type = "pci"; 1160 device_type = "pci";
1208 dma-coherent; 1161 dma-coherent;
1209 apio-wins = <8>; 1162 apio-wins = <8>;
1210 ppio-wins = <8>; 1163 ppio-wins = <8>;
1211 bus-range = <0x0 0xff 1164 bus-range = <0x0 0xff>;
1212 ranges = <0x82000000 1165 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1213 msi-parent = <&its 0> !! 1166 msi-parent = <&its>;
1214 #interrupt-cells = <1 1167 #interrupt-cells = <1>;
1215 interrupt-map-mask = 1168 interrupt-map-mask = <0 0 0 7>;
1216 interrupt-map = <0000 1169 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1217 <0000 1170 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1218 <0000 1171 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1219 <0000 1172 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1220 iommu-map = <0 &smmu 1173 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1221 status = "disabled"; 1174 status = "disabled";
1222 }; 1175 };
1223 1176
1224 pcie3: pcie@3600000 { 1177 pcie3: pcie@3600000 {
1225 compatible = "fsl,lx2 1178 compatible = "fsl,lx2160a-pcie";
1226 reg = <0x00 0x0360000 1179 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1227 <0x90 0x0000000 1180 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1228 reg-names = "csr_axi_ 1181 reg-names = "csr_axi_slave", "config_axi_slave";
1229 interrupts = <GIC_SPI 1182 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1230 <GIC_SPI 1183 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1231 <GIC_SPI 1184 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1232 interrupt-names = "ae 1185 interrupt-names = "aer", "pme", "intr";
1233 #address-cells = <3>; 1186 #address-cells = <3>;
1234 #size-cells = <2>; 1187 #size-cells = <2>;
1235 device_type = "pci"; 1188 device_type = "pci";
1236 dma-coherent; 1189 dma-coherent;
1237 apio-wins = <256>; 1190 apio-wins = <256>;
1238 ppio-wins = <24>; 1191 ppio-wins = <24>;
1239 bus-range = <0x0 0xff 1192 bus-range = <0x0 0xff>;
1240 ranges = <0x82000000 1193 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1241 msi-parent = <&its 0> !! 1194 msi-parent = <&its>;
1242 #interrupt-cells = <1 1195 #interrupt-cells = <1>;
1243 interrupt-map-mask = 1196 interrupt-map-mask = <0 0 0 7>;
1244 interrupt-map = <0000 1197 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245 <0000 1198 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1246 <0000 1199 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1247 <0000 1200 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1248 iommu-map = <0 &smmu 1201 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1249 status = "disabled"; 1202 status = "disabled";
1250 }; 1203 };
1251 1204
1252 pcie4: pcie@3700000 { 1205 pcie4: pcie@3700000 {
1253 compatible = "fsl,lx2 1206 compatible = "fsl,lx2160a-pcie";
1254 reg = <0x00 0x0370000 1207 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1255 <0x98 0x0000000 1208 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1256 reg-names = "csr_axi_ 1209 reg-names = "csr_axi_slave", "config_axi_slave";
1257 interrupts = <GIC_SPI 1210 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1258 <GIC_SPI 1211 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1259 <GIC_SPI 1212 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1260 interrupt-names = "ae 1213 interrupt-names = "aer", "pme", "intr";
1261 #address-cells = <3>; 1214 #address-cells = <3>;
1262 #size-cells = <2>; 1215 #size-cells = <2>;
1263 device_type = "pci"; 1216 device_type = "pci";
1264 dma-coherent; 1217 dma-coherent;
1265 apio-wins = <8>; 1218 apio-wins = <8>;
1266 ppio-wins = <8>; 1219 ppio-wins = <8>;
1267 bus-range = <0x0 0xff 1220 bus-range = <0x0 0xff>;
1268 ranges = <0x82000000 1221 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1269 msi-parent = <&its 0> !! 1222 msi-parent = <&its>;
1270 #interrupt-cells = <1 1223 #interrupt-cells = <1>;
1271 interrupt-map-mask = 1224 interrupt-map-mask = <0 0 0 7>;
1272 interrupt-map = <0000 1225 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1273 <0000 1226 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1274 <0000 1227 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1275 <0000 1228 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1276 iommu-map = <0 &smmu 1229 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1277 status = "disabled"; 1230 status = "disabled";
1278 }; 1231 };
1279 1232
1280 pcie5: pcie@3800000 { 1233 pcie5: pcie@3800000 {
1281 compatible = "fsl,lx2 1234 compatible = "fsl,lx2160a-pcie";
1282 reg = <0x00 0x0380000 1235 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1283 <0xa0 0x0000000 1236 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1284 reg-names = "csr_axi_ 1237 reg-names = "csr_axi_slave", "config_axi_slave";
1285 interrupts = <GIC_SPI 1238 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1286 <GIC_SPI 1239 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1287 <GIC_SPI 1240 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1288 interrupt-names = "ae 1241 interrupt-names = "aer", "pme", "intr";
1289 #address-cells = <3>; 1242 #address-cells = <3>;
1290 #size-cells = <2>; 1243 #size-cells = <2>;
1291 device_type = "pci"; 1244 device_type = "pci";
1292 dma-coherent; 1245 dma-coherent;
1293 apio-wins = <256>; 1246 apio-wins = <256>;
1294 ppio-wins = <24>; 1247 ppio-wins = <24>;
1295 bus-range = <0x0 0xff 1248 bus-range = <0x0 0xff>;
1296 ranges = <0x82000000 1249 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1297 msi-parent = <&its 0> !! 1250 msi-parent = <&its>;
1298 #interrupt-cells = <1 1251 #interrupt-cells = <1>;
1299 interrupt-map-mask = 1252 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0000 1253 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1301 <0000 1254 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1302 <0000 1255 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1303 <0000 1256 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1304 iommu-map = <0 &smmu 1257 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1305 status = "disabled"; 1258 status = "disabled";
1306 }; 1259 };
1307 1260
1308 pcie6: pcie@3900000 { 1261 pcie6: pcie@3900000 {
1309 compatible = "fsl,lx2 1262 compatible = "fsl,lx2160a-pcie";
1310 reg = <0x00 0x0390000 1263 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1311 <0xa8 0x0000000 1264 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1312 reg-names = "csr_axi_ 1265 reg-names = "csr_axi_slave", "config_axi_slave";
1313 interrupts = <GIC_SPI 1266 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1314 <GIC_SPI 1267 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1315 <GIC_SPI 1268 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1316 interrupt-names = "ae 1269 interrupt-names = "aer", "pme", "intr";
1317 #address-cells = <3>; 1270 #address-cells = <3>;
1318 #size-cells = <2>; 1271 #size-cells = <2>;
1319 device_type = "pci"; 1272 device_type = "pci";
1320 dma-coherent; 1273 dma-coherent;
1321 apio-wins = <8>; 1274 apio-wins = <8>;
1322 ppio-wins = <8>; 1275 ppio-wins = <8>;
1323 bus-range = <0x0 0xff 1276 bus-range = <0x0 0xff>;
1324 ranges = <0x82000000 1277 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1325 msi-parent = <&its 0> !! 1278 msi-parent = <&its>;
1326 #interrupt-cells = <1 1279 #interrupt-cells = <1>;
1327 interrupt-map-mask = 1280 interrupt-map-mask = <0 0 0 7>;
1328 interrupt-map = <0000 1281 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1329 <0000 1282 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1330 <0000 1283 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1331 <0000 1284 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1332 iommu-map = <0 &smmu 1285 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1333 status = "disabled"; 1286 status = "disabled";
1334 }; 1287 };
1335 1288
1336 smmu: iommu@5000000 { 1289 smmu: iommu@5000000 {
1337 compatible = "arm,mmu 1290 compatible = "arm,mmu-500";
1338 reg = <0 0x5000000 0 1291 reg = <0 0x5000000 0 0x800000>;
1339 #iommu-cells = <1>; 1292 #iommu-cells = <1>;
1340 #global-interrupts = 1293 #global-interrupts = <14>;
1341 // globa 1294 // global secure fault
1342 interrupts = <GIC_SPI 1295 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1343 // combi 1296 // combined secure
1344 <GIC_SPI 1297 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1345 // globa 1298 // global non-secure fault
1346 <GIC_SPI 1299 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1347 // combi 1300 // combined non-secure
1348 <GIC_SPI 1301 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1349 // perfo 1302 // performance counter interrupts 0-9
1350 <GIC_SPI 1303 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 1304 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 1305 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 1306 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 1307 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 1308 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 1309 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 1310 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 1311 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 1312 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1360 // per c 1313 // per context interrupt, 64 interrupts
1361 <GIC_SPI 1314 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 1315 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 1316 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1317 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1318 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1319 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1320 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1321 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1322 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1323 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1324 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1325 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1326 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1327 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1328 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1329 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1330 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1331 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1332 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1333 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1334 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1335 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1336 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1337 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1338 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1339 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1340 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1341 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1342 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1343 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1344 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1345 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1346 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1347 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1348 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1349 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1350 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1351 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1352 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1353 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1354 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1355 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1356 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1357 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1358 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1359 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1360 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1361 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1362 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1363 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1364 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1365 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1366 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1367 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 1368 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 1369 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 1370 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 1371 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 1372 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 1373 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 1374 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 1375 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 1376 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 1377 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1425 dma-coherent; 1378 dma-coherent;
1426 }; 1379 };
1427 1380
1428 console@8340020 { 1381 console@8340020 {
1429 compatible = "fsl,dpa 1382 compatible = "fsl,dpaa2-console";
1430 reg = <0x00000000 0x0 1383 reg = <0x00000000 0x08340020 0 0x2>;
1431 }; 1384 };
1432 1385
1433 ptp-timer@8b95000 { 1386 ptp-timer@8b95000 {
1434 compatible = "fsl,dpa 1387 compatible = "fsl,dpaa2-ptp";
1435 reg = <0x0 0x8b95000 1388 reg = <0x0 0x8b95000 0x0 0x100>;
1436 clocks = <&clockgen Q 1389 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1437 Q 1390 QORIQ_CLK_PLL_DIV(2)>;
1438 little-endian; 1391 little-endian;
1439 fsl,extts-fifo; 1392 fsl,extts-fifo;
1440 }; 1393 };
1441 1394
1442 /* WRIOP0: 0x8b8_0000, E-MDIO 1395 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1443 emdio1: mdio@8b96000 { 1396 emdio1: mdio@8b96000 {
1444 compatible = "fsl,fma 1397 compatible = "fsl,fman-memac-mdio";
1445 reg = <0x0 0x8b96000 1398 reg = <0x0 0x8b96000 0x0 0x1000>;
1446 interrupts = <GIC_SPI 1399 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1447 #address-cells = <1>; 1400 #address-cells = <1>;
1448 #size-cells = <0>; 1401 #size-cells = <0>;
1449 little-endian; 1402 little-endian;
1450 clock-frequency = <25 1403 clock-frequency = <2500000>;
1451 clocks = <&clockgen Q 1404 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1452 Q 1405 QORIQ_CLK_PLL_DIV(2)>;
1453 status = "disabled"; 1406 status = "disabled";
1454 }; 1407 };
1455 1408
1456 emdio2: mdio@8b97000 { 1409 emdio2: mdio@8b97000 {
1457 compatible = "fsl,fma 1410 compatible = "fsl,fman-memac-mdio";
1458 reg = <0x0 0x8b97000 1411 reg = <0x0 0x8b97000 0x0 0x1000>;
1459 interrupts = <GIC_SPI 1412 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1460 little-endian; 1413 little-endian;
1461 #address-cells = <1>; 1414 #address-cells = <1>;
1462 #size-cells = <0>; 1415 #size-cells = <0>;
1463 clock-frequency = <25 1416 clock-frequency = <2500000>;
1464 clocks = <&clockgen Q 1417 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1465 Q 1418 QORIQ_CLK_PLL_DIV(2)>;
1466 status = "disabled"; 1419 status = "disabled";
1467 }; 1420 };
1468 1421
1469 pcs_mdio1: mdio@8c07000 { 1422 pcs_mdio1: mdio@8c07000 {
1470 compatible = "fsl,fma 1423 compatible = "fsl,fman-memac-mdio";
1471 reg = <0x0 0x8c07000 1424 reg = <0x0 0x8c07000 0x0 0x1000>;
1472 little-endian; 1425 little-endian;
1473 #address-cells = <1>; 1426 #address-cells = <1>;
1474 #size-cells = <0>; 1427 #size-cells = <0>;
1475 status = "disabled"; 1428 status = "disabled";
1476 1429
1477 pcs1: ethernet-phy@0 1430 pcs1: ethernet-phy@0 {
1478 reg = <0>; 1431 reg = <0>;
1479 }; 1432 };
1480 }; 1433 };
1481 1434
1482 pcs_mdio2: mdio@8c0b000 { 1435 pcs_mdio2: mdio@8c0b000 {
1483 compatible = "fsl,fma 1436 compatible = "fsl,fman-memac-mdio";
1484 reg = <0x0 0x8c0b000 1437 reg = <0x0 0x8c0b000 0x0 0x1000>;
1485 little-endian; 1438 little-endian;
1486 #address-cells = <1>; 1439 #address-cells = <1>;
1487 #size-cells = <0>; 1440 #size-cells = <0>;
1488 status = "disabled"; 1441 status = "disabled";
1489 1442
1490 pcs2: ethernet-phy@0 1443 pcs2: ethernet-phy@0 {
1491 reg = <0>; 1444 reg = <0>;
1492 }; 1445 };
1493 }; 1446 };
1494 1447
1495 pcs_mdio3: mdio@8c0f000 { 1448 pcs_mdio3: mdio@8c0f000 {
1496 compatible = "fsl,fma 1449 compatible = "fsl,fman-memac-mdio";
1497 reg = <0x0 0x8c0f000 1450 reg = <0x0 0x8c0f000 0x0 0x1000>;
1498 little-endian; 1451 little-endian;
1499 #address-cells = <1>; 1452 #address-cells = <1>;
1500 #size-cells = <0>; 1453 #size-cells = <0>;
1501 status = "disabled"; 1454 status = "disabled";
1502 1455
1503 pcs3: ethernet-phy@0 1456 pcs3: ethernet-phy@0 {
1504 reg = <0>; 1457 reg = <0>;
1505 }; 1458 };
1506 }; 1459 };
1507 1460
1508 pcs_mdio4: mdio@8c13000 { 1461 pcs_mdio4: mdio@8c13000 {
1509 compatible = "fsl,fma 1462 compatible = "fsl,fman-memac-mdio";
1510 reg = <0x0 0x8c13000 1463 reg = <0x0 0x8c13000 0x0 0x1000>;
1511 little-endian; 1464 little-endian;
1512 #address-cells = <1>; 1465 #address-cells = <1>;
1513 #size-cells = <0>; 1466 #size-cells = <0>;
1514 status = "disabled"; 1467 status = "disabled";
1515 1468
1516 pcs4: ethernet-phy@0 1469 pcs4: ethernet-phy@0 {
1517 reg = <0>; 1470 reg = <0>;
1518 }; 1471 };
1519 }; 1472 };
1520 1473
1521 pcs_mdio5: mdio@8c17000 { 1474 pcs_mdio5: mdio@8c17000 {
1522 compatible = "fsl,fma 1475 compatible = "fsl,fman-memac-mdio";
1523 reg = <0x0 0x8c17000 1476 reg = <0x0 0x8c17000 0x0 0x1000>;
1524 little-endian; 1477 little-endian;
1525 #address-cells = <1>; 1478 #address-cells = <1>;
1526 #size-cells = <0>; 1479 #size-cells = <0>;
1527 status = "disabled"; 1480 status = "disabled";
1528 1481
1529 pcs5: ethernet-phy@0 1482 pcs5: ethernet-phy@0 {
1530 reg = <0>; 1483 reg = <0>;
1531 }; 1484 };
1532 }; 1485 };
1533 1486
1534 pcs_mdio6: mdio@8c1b000 { 1487 pcs_mdio6: mdio@8c1b000 {
1535 compatible = "fsl,fma 1488 compatible = "fsl,fman-memac-mdio";
1536 reg = <0x0 0x8c1b000 1489 reg = <0x0 0x8c1b000 0x0 0x1000>;
1537 little-endian; 1490 little-endian;
1538 #address-cells = <1>; 1491 #address-cells = <1>;
1539 #size-cells = <0>; 1492 #size-cells = <0>;
1540 status = "disabled"; 1493 status = "disabled";
1541 1494
1542 pcs6: ethernet-phy@0 1495 pcs6: ethernet-phy@0 {
1543 reg = <0>; 1496 reg = <0>;
1544 }; 1497 };
1545 }; 1498 };
1546 1499
1547 pcs_mdio7: mdio@8c1f000 { 1500 pcs_mdio7: mdio@8c1f000 {
1548 compatible = "fsl,fma 1501 compatible = "fsl,fman-memac-mdio";
1549 reg = <0x0 0x8c1f000 1502 reg = <0x0 0x8c1f000 0x0 0x1000>;
1550 little-endian; 1503 little-endian;
1551 #address-cells = <1>; 1504 #address-cells = <1>;
1552 #size-cells = <0>; 1505 #size-cells = <0>;
1553 status = "disabled"; 1506 status = "disabled";
1554 1507
1555 pcs7: ethernet-phy@0 1508 pcs7: ethernet-phy@0 {
1556 reg = <0>; 1509 reg = <0>;
1557 }; 1510 };
1558 }; 1511 };
1559 1512
1560 pcs_mdio8: mdio@8c23000 { 1513 pcs_mdio8: mdio@8c23000 {
1561 compatible = "fsl,fma 1514 compatible = "fsl,fman-memac-mdio";
1562 reg = <0x0 0x8c23000 1515 reg = <0x0 0x8c23000 0x0 0x1000>;
1563 little-endian; 1516 little-endian;
1564 #address-cells = <1>; 1517 #address-cells = <1>;
1565 #size-cells = <0>; 1518 #size-cells = <0>;
1566 status = "disabled"; 1519 status = "disabled";
1567 1520
1568 pcs8: ethernet-phy@0 1521 pcs8: ethernet-phy@0 {
1569 reg = <0>; 1522 reg = <0>;
1570 }; 1523 };
1571 }; 1524 };
1572 1525
1573 pcs_mdio9: mdio@8c27000 { 1526 pcs_mdio9: mdio@8c27000 {
1574 compatible = "fsl,fma 1527 compatible = "fsl,fman-memac-mdio";
1575 reg = <0x0 0x8c27000 1528 reg = <0x0 0x8c27000 0x0 0x1000>;
1576 little-endian; 1529 little-endian;
1577 #address-cells = <1>; 1530 #address-cells = <1>;
1578 #size-cells = <0>; 1531 #size-cells = <0>;
1579 status = "disabled"; 1532 status = "disabled";
1580 1533
1581 pcs9: ethernet-phy@0 1534 pcs9: ethernet-phy@0 {
1582 reg = <0>; 1535 reg = <0>;
1583 }; 1536 };
1584 }; 1537 };
1585 1538
1586 pcs_mdio10: mdio@8c2b000 { 1539 pcs_mdio10: mdio@8c2b000 {
1587 compatible = "fsl,fma 1540 compatible = "fsl,fman-memac-mdio";
1588 reg = <0x0 0x8c2b000 1541 reg = <0x0 0x8c2b000 0x0 0x1000>;
1589 little-endian; 1542 little-endian;
1590 #address-cells = <1>; 1543 #address-cells = <1>;
1591 #size-cells = <0>; 1544 #size-cells = <0>;
1592 status = "disabled"; 1545 status = "disabled";
1593 1546
1594 pcs10: ethernet-phy@0 1547 pcs10: ethernet-phy@0 {
1595 reg = <0>; 1548 reg = <0>;
1596 }; 1549 };
1597 }; 1550 };
1598 1551
1599 pcs_mdio11: mdio@8c2f000 { 1552 pcs_mdio11: mdio@8c2f000 {
1600 compatible = "fsl,fma 1553 compatible = "fsl,fman-memac-mdio";
1601 reg = <0x0 0x8c2f000 1554 reg = <0x0 0x8c2f000 0x0 0x1000>;
1602 little-endian; 1555 little-endian;
1603 #address-cells = <1>; 1556 #address-cells = <1>;
1604 #size-cells = <0>; 1557 #size-cells = <0>;
1605 status = "disabled"; 1558 status = "disabled";
1606 1559
1607 pcs11: ethernet-phy@0 1560 pcs11: ethernet-phy@0 {
1608 reg = <0>; 1561 reg = <0>;
1609 }; 1562 };
1610 }; 1563 };
1611 1564
1612 pcs_mdio12: mdio@8c33000 { 1565 pcs_mdio12: mdio@8c33000 {
1613 compatible = "fsl,fma 1566 compatible = "fsl,fman-memac-mdio";
1614 reg = <0x0 0x8c33000 1567 reg = <0x0 0x8c33000 0x0 0x1000>;
1615 little-endian; 1568 little-endian;
1616 #address-cells = <1>; 1569 #address-cells = <1>;
1617 #size-cells = <0>; 1570 #size-cells = <0>;
1618 status = "disabled"; 1571 status = "disabled";
1619 1572
1620 pcs12: ethernet-phy@0 1573 pcs12: ethernet-phy@0 {
1621 reg = <0>; 1574 reg = <0>;
1622 }; 1575 };
1623 }; 1576 };
1624 1577
1625 pcs_mdio13: mdio@8c37000 { 1578 pcs_mdio13: mdio@8c37000 {
1626 compatible = "fsl,fma 1579 compatible = "fsl,fman-memac-mdio";
1627 reg = <0x0 0x8c37000 1580 reg = <0x0 0x8c37000 0x0 0x1000>;
1628 little-endian; 1581 little-endian;
1629 #address-cells = <1>; 1582 #address-cells = <1>;
1630 #size-cells = <0>; 1583 #size-cells = <0>;
1631 status = "disabled"; 1584 status = "disabled";
1632 1585
1633 pcs13: ethernet-phy@0 1586 pcs13: ethernet-phy@0 {
1634 reg = <0>; 1587 reg = <0>;
1635 }; 1588 };
1636 }; 1589 };
1637 1590
1638 pcs_mdio14: mdio@8c3b000 { 1591 pcs_mdio14: mdio@8c3b000 {
1639 compatible = "fsl,fma 1592 compatible = "fsl,fman-memac-mdio";
1640 reg = <0x0 0x8c3b000 1593 reg = <0x0 0x8c3b000 0x0 0x1000>;
1641 little-endian; 1594 little-endian;
1642 #address-cells = <1>; 1595 #address-cells = <1>;
1643 #size-cells = <0>; 1596 #size-cells = <0>;
1644 status = "disabled"; 1597 status = "disabled";
1645 1598
1646 pcs14: ethernet-phy@0 1599 pcs14: ethernet-phy@0 {
1647 reg = <0>; 1600 reg = <0>;
1648 }; 1601 };
1649 }; 1602 };
1650 1603
1651 pcs_mdio15: mdio@8c3f000 { 1604 pcs_mdio15: mdio@8c3f000 {
1652 compatible = "fsl,fma 1605 compatible = "fsl,fman-memac-mdio";
1653 reg = <0x0 0x8c3f000 1606 reg = <0x0 0x8c3f000 0x0 0x1000>;
1654 little-endian; 1607 little-endian;
1655 #address-cells = <1>; 1608 #address-cells = <1>;
1656 #size-cells = <0>; 1609 #size-cells = <0>;
1657 status = "disabled"; 1610 status = "disabled";
1658 1611
1659 pcs15: ethernet-phy@0 1612 pcs15: ethernet-phy@0 {
1660 reg = <0>; 1613 reg = <0>;
1661 }; 1614 };
1662 }; 1615 };
1663 1616
1664 pcs_mdio16: mdio@8c43000 { 1617 pcs_mdio16: mdio@8c43000 {
1665 compatible = "fsl,fma 1618 compatible = "fsl,fman-memac-mdio";
1666 reg = <0x0 0x8c43000 1619 reg = <0x0 0x8c43000 0x0 0x1000>;
1667 little-endian; 1620 little-endian;
1668 #address-cells = <1>; 1621 #address-cells = <1>;
1669 #size-cells = <0>; 1622 #size-cells = <0>;
1670 status = "disabled"; 1623 status = "disabled";
1671 1624
1672 pcs16: ethernet-phy@0 1625 pcs16: ethernet-phy@0 {
1673 reg = <0>; 1626 reg = <0>;
1674 }; 1627 };
1675 }; 1628 };
1676 1629
1677 pcs_mdio17: mdio@8c47000 { 1630 pcs_mdio17: mdio@8c47000 {
1678 compatible = "fsl,fma 1631 compatible = "fsl,fman-memac-mdio";
1679 reg = <0x0 0x8c47000 1632 reg = <0x0 0x8c47000 0x0 0x1000>;
1680 little-endian; 1633 little-endian;
1681 #address-cells = <1>; 1634 #address-cells = <1>;
1682 #size-cells = <0>; 1635 #size-cells = <0>;
1683 status = "disabled"; 1636 status = "disabled";
1684 1637
1685 pcs17: ethernet-phy@0 1638 pcs17: ethernet-phy@0 {
1686 reg = <0>; 1639 reg = <0>;
1687 }; 1640 };
1688 }; 1641 };
1689 1642
1690 pcs_mdio18: mdio@8c4b000 { 1643 pcs_mdio18: mdio@8c4b000 {
1691 compatible = "fsl,fma 1644 compatible = "fsl,fman-memac-mdio";
1692 reg = <0x0 0x8c4b000 1645 reg = <0x0 0x8c4b000 0x0 0x1000>;
1693 little-endian; 1646 little-endian;
1694 #address-cells = <1>; 1647 #address-cells = <1>;
1695 #size-cells = <0>; 1648 #size-cells = <0>;
1696 status = "disabled"; 1649 status = "disabled";
1697 1650
1698 pcs18: ethernet-phy@0 1651 pcs18: ethernet-phy@0 {
1699 reg = <0>; 1652 reg = <0>;
1700 }; 1653 };
1701 }; 1654 };
1702 1655
1703 pinmux_i2crv: pinmux@70010012 <<
1704 compatible = "pinctrl <<
1705 reg = <0x00000007 0x0 <<
1706 #address-cells = <1>; <<
1707 #size-cells = <0>; <<
1708 pinctrl-single,bit-pe <<
1709 pinctrl-single,regist <<
1710 pinctrl-single,functi <<
1711 <<
1712 i2c1_scl: i2c1-scl-pi <<
1713 pinctrl-singl <<
1714 }; <<
1715 <<
1716 i2c1_scl_gpio: i2c1-s <<
1717 pinctrl-singl <<
1718 }; <<
1719 <<
1720 i2c2_scl: i2c2-scl-pi <<
1721 pinctrl-singl <<
1722 }; <<
1723 <<
1724 i2c2_scl_gpio: i2c2-s <<
1725 pinctrl-singl <<
1726 }; <<
1727 <<
1728 i2c3_scl: i2c3-scl-pi <<
1729 pinctrl-singl <<
1730 }; <<
1731 <<
1732 i2c3_scl_gpio: i2c3-s <<
1733 pinctrl-singl <<
1734 }; <<
1735 <<
1736 i2c4_scl: i2c4-scl-pi <<
1737 pinctrl-singl <<
1738 }; <<
1739 <<
1740 i2c4_scl_gpio: i2c4-s <<
1741 pinctrl-singl <<
1742 }; <<
1743 <<
1744 i2c5_scl: i2c5-scl-pi <<
1745 pinctrl-singl <<
1746 }; <<
1747 <<
1748 i2c5_scl_gpio: i2c5-s <<
1749 pinctrl-singl <<
1750 }; <<
1751 <<
1752 i2c6_scl: i2c6-scl-pi <<
1753 pinctrl-singl <<
1754 }; <<
1755 <<
1756 i2c6_scl_gpio: i2c6-s <<
1757 pinctrl-singl <<
1758 }; <<
1759 <<
1760 i2c7_scl: i2c7-scl-pi <<
1761 pinctrl-singl <<
1762 }; <<
1763 <<
1764 i2c7_scl_gpio: i2c7-s <<
1765 pinctrl-singl <<
1766 }; <<
1767 <<
1768 i2c0_scl: i2c0-scl-pi <<
1769 pinctrl-singl <<
1770 }; <<
1771 <<
1772 i2c0_scl_gpio: i2c0-s <<
1773 pinctrl-singl <<
1774 }; <<
1775 }; <<
1776 <<
1777 fsl_mc: fsl-mc@80c000000 { 1656 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qor 1657 compatible = "fsl,qoriq-mc";
1779 reg = <0x00000008 0x0 1658 reg = <0x00000008 0x0c000000 0 0x40>,
1780 <0x00000000 0x0 1659 <0x00000000 0x08340000 0 0x40000>;
1781 msi-parent = <&its 0> !! 1660 msi-parent = <&its>;
1782 /* iommu-map property 1661 /* iommu-map property is fixed up by u-boot */
1783 iommu-map = <0 &smmu 1662 iommu-map = <0 &smmu 0 0>;
1784 dma-coherent; 1663 dma-coherent;
1785 #address-cells = <3>; 1664 #address-cells = <3>;
1786 #size-cells = <1>; 1665 #size-cells = <1>;
1787 1666
1788 /* 1667 /*
1789 * Region type 0x0 - 1668 * Region type 0x0 - MC portals
1790 * Region type 0x1 - 1669 * Region type 0x1 - QBMAN portals
1791 */ 1670 */
1792 ranges = <0x0 0x0 0x0 1671 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1793 0x1 0x0 0x0 1672 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1794 1673
1795 /* 1674 /*
1796 * Define the maximum 1675 * Define the maximum number of MACs present on the SoC.
1797 */ 1676 */
1798 dpmacs { 1677 dpmacs {
1799 #address-cell 1678 #address-cells = <1>;
1800 #size-cells = 1679 #size-cells = <0>;
1801 1680
1802 dpmac1: ether 1681 dpmac1: ethernet@1 {
1803 compa 1682 compatible = "fsl,qoriq-mc-dpmac";
1804 reg = 1683 reg = <0x1>;
1805 pcs-h 1684 pcs-handle = <&pcs1>;
1806 }; 1685 };
1807 1686
1808 dpmac2: ether 1687 dpmac2: ethernet@2 {
1809 compa 1688 compatible = "fsl,qoriq-mc-dpmac";
1810 reg = 1689 reg = <0x2>;
1811 pcs-h 1690 pcs-handle = <&pcs2>;
1812 }; 1691 };
1813 1692
1814 dpmac3: ether 1693 dpmac3: ethernet@3 {
1815 compa 1694 compatible = "fsl,qoriq-mc-dpmac";
1816 reg = 1695 reg = <0x3>;
1817 pcs-h 1696 pcs-handle = <&pcs3>;
1818 }; 1697 };
1819 1698
1820 dpmac4: ether 1699 dpmac4: ethernet@4 {
1821 compa 1700 compatible = "fsl,qoriq-mc-dpmac";
1822 reg = 1701 reg = <0x4>;
1823 pcs-h 1702 pcs-handle = <&pcs4>;
1824 }; 1703 };
1825 1704
1826 dpmac5: ether 1705 dpmac5: ethernet@5 {
1827 compa 1706 compatible = "fsl,qoriq-mc-dpmac";
1828 reg = 1707 reg = <0x5>;
1829 pcs-h 1708 pcs-handle = <&pcs5>;
1830 }; 1709 };
1831 1710
1832 dpmac6: ether 1711 dpmac6: ethernet@6 {
1833 compa 1712 compatible = "fsl,qoriq-mc-dpmac";
1834 reg = 1713 reg = <0x6>;
1835 pcs-h 1714 pcs-handle = <&pcs6>;
1836 }; 1715 };
1837 1716
1838 dpmac7: ether 1717 dpmac7: ethernet@7 {
1839 compa 1718 compatible = "fsl,qoriq-mc-dpmac";
1840 reg = 1719 reg = <0x7>;
1841 pcs-h 1720 pcs-handle = <&pcs7>;
1842 }; 1721 };
1843 1722
1844 dpmac8: ether 1723 dpmac8: ethernet@8 {
1845 compa 1724 compatible = "fsl,qoriq-mc-dpmac";
1846 reg = 1725 reg = <0x8>;
1847 pcs-h 1726 pcs-handle = <&pcs8>;
1848 }; 1727 };
1849 1728
1850 dpmac9: ether 1729 dpmac9: ethernet@9 {
1851 compa 1730 compatible = "fsl,qoriq-mc-dpmac";
1852 reg = 1731 reg = <0x9>;
1853 pcs-h 1732 pcs-handle = <&pcs9>;
1854 }; 1733 };
1855 1734
1856 dpmac10: ethe 1735 dpmac10: ethernet@a {
1857 compa 1736 compatible = "fsl,qoriq-mc-dpmac";
1858 reg = 1737 reg = <0xa>;
1859 pcs-h 1738 pcs-handle = <&pcs10>;
1860 }; 1739 };
1861 1740
1862 dpmac11: ethe 1741 dpmac11: ethernet@b {
1863 compa 1742 compatible = "fsl,qoriq-mc-dpmac";
1864 reg = 1743 reg = <0xb>;
1865 pcs-h 1744 pcs-handle = <&pcs11>;
1866 }; 1745 };
1867 1746
1868 dpmac12: ethe 1747 dpmac12: ethernet@c {
1869 compa 1748 compatible = "fsl,qoriq-mc-dpmac";
1870 reg = 1749 reg = <0xc>;
1871 pcs-h 1750 pcs-handle = <&pcs12>;
1872 }; 1751 };
1873 1752
1874 dpmac13: ethe 1753 dpmac13: ethernet@d {
1875 compa 1754 compatible = "fsl,qoriq-mc-dpmac";
1876 reg = 1755 reg = <0xd>;
1877 pcs-h 1756 pcs-handle = <&pcs13>;
1878 }; 1757 };
1879 1758
1880 dpmac14: ethe 1759 dpmac14: ethernet@e {
1881 compa 1760 compatible = "fsl,qoriq-mc-dpmac";
1882 reg = 1761 reg = <0xe>;
1883 pcs-h 1762 pcs-handle = <&pcs14>;
1884 }; 1763 };
1885 1764
1886 dpmac15: ethe 1765 dpmac15: ethernet@f {
1887 compa 1766 compatible = "fsl,qoriq-mc-dpmac";
1888 reg = 1767 reg = <0xf>;
1889 pcs-h 1768 pcs-handle = <&pcs15>;
1890 }; 1769 };
1891 1770
1892 dpmac16: ethe 1771 dpmac16: ethernet@10 {
1893 compa 1772 compatible = "fsl,qoriq-mc-dpmac";
1894 reg = 1773 reg = <0x10>;
1895 pcs-h 1774 pcs-handle = <&pcs16>;
1896 }; 1775 };
1897 1776
1898 dpmac17: ethe 1777 dpmac17: ethernet@11 {
1899 compa 1778 compatible = "fsl,qoriq-mc-dpmac";
1900 reg = 1779 reg = <0x11>;
1901 pcs-h 1780 pcs-handle = <&pcs17>;
1902 }; 1781 };
1903 1782
1904 dpmac18: ethe 1783 dpmac18: ethernet@12 {
1905 compa 1784 compatible = "fsl,qoriq-mc-dpmac";
1906 reg = 1785 reg = <0x12>;
1907 pcs-h 1786 pcs-handle = <&pcs18>;
1908 }; 1787 };
1909 }; 1788 };
1910 }; 1789 };
1911 }; 1790 };
1912 1791
1913 firmware { 1792 firmware {
1914 optee: optee { 1793 optee: optee {
1915 compatible = "linaro, 1794 compatible = "linaro,optee-tz";
1916 method = "smc"; 1795 method = "smc";
1917 status = "disabled"; 1796 status = "disabled";
1918 }; 1797 };
1919 }; 1798 };
1920 }; 1799 };
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