1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree Include file for Layerscape-LX2 3 // Device Tree Include file for Layerscape-LX2160A family SoC.
4 // 4 //
5 // Copyright 2018-2020 NXP 5 // Copyright 2018-2020 NXP
6 6
7 #include <dt-bindings/clock/fsl,qoriq-clockgen 7 #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
11 11
12 /memreserve/ 0x80000000 0x00010000; 12 /memreserve/ 0x80000000 0x00010000;
13 13
14 / { 14 / {
15 compatible = "fsl,lx2160a"; 15 compatible = "fsl,lx2160a";
16 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
17 #address-cells = <2>; 17 #address-cells = <2>;
18 #size-cells = <2>; 18 #size-cells = <2>;
19 19
20 aliases { 20 aliases {
21 rtc1 = &ftm_alarm0; 21 rtc1 = &ftm_alarm0;
22 }; 22 };
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>; 25 #address-cells = <1>;
26 #size-cells = <0>; 26 #size-cells = <0>;
27 27
28 // 8 clusters having 2 Cortex- 28 // 8 clusters having 2 Cortex-A72 cores each
29 cpu0: cpu@0 { 29 cpu0: cpu@0 {
30 device_type = "cpu"; 30 device_type = "cpu";
31 compatible = "arm,cort 31 compatible = "arm,cortex-a72";
32 enable-method = "psci" 32 enable-method = "psci";
33 reg = <0x0>; 33 reg = <0x0>;
34 clocks = <&clockgen QO 34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000 35 d-cache-size = <0x8000>;
36 d-cache-line-size = <6 36 d-cache-line-size = <64>;
37 d-cache-sets = <128>; 37 d-cache-sets = <128>;
38 i-cache-size = <0xC000 38 i-cache-size = <0xC000>;
39 i-cache-line-size = <6 39 i-cache-line-size = <64>;
40 i-cache-sets = <192>; 40 i-cache-sets = <192>;
41 next-level-cache = <&c 41 next-level-cache = <&cluster0_l2>;
42 cpu-idle-states = <&cp 42 cpu-idle-states = <&cpu_pw15>;
43 #cooling-cells = <2>; 43 #cooling-cells = <2>;
44 }; 44 };
45 45
46 cpu1: cpu@1 { 46 cpu1: cpu@1 {
47 device_type = "cpu"; 47 device_type = "cpu";
48 compatible = "arm,cort 48 compatible = "arm,cortex-a72";
49 enable-method = "psci" 49 enable-method = "psci";
50 reg = <0x1>; 50 reg = <0x1>;
51 clocks = <&clockgen QO 51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000 52 d-cache-size = <0x8000>;
53 d-cache-line-size = <6 53 d-cache-line-size = <64>;
54 d-cache-sets = <128>; 54 d-cache-sets = <128>;
55 i-cache-size = <0xC000 55 i-cache-size = <0xC000>;
56 i-cache-line-size = <6 56 i-cache-line-size = <64>;
57 i-cache-sets = <192>; 57 i-cache-sets = <192>;
58 next-level-cache = <&c 58 next-level-cache = <&cluster0_l2>;
59 cpu-idle-states = <&cp 59 cpu-idle-states = <&cpu_pw15>;
60 #cooling-cells = <2>; 60 #cooling-cells = <2>;
61 }; 61 };
62 62
63 cpu100: cpu@100 { 63 cpu100: cpu@100 {
64 device_type = "cpu"; 64 device_type = "cpu";
65 compatible = "arm,cort 65 compatible = "arm,cortex-a72";
66 enable-method = "psci" 66 enable-method = "psci";
67 reg = <0x100>; 67 reg = <0x100>;
68 clocks = <&clockgen QO 68 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
69 d-cache-size = <0x8000 69 d-cache-size = <0x8000>;
70 d-cache-line-size = <6 70 d-cache-line-size = <64>;
71 d-cache-sets = <128>; 71 d-cache-sets = <128>;
72 i-cache-size = <0xC000 72 i-cache-size = <0xC000>;
73 i-cache-line-size = <6 73 i-cache-line-size = <64>;
74 i-cache-sets = <192>; 74 i-cache-sets = <192>;
75 next-level-cache = <&c 75 next-level-cache = <&cluster1_l2>;
76 cpu-idle-states = <&cp 76 cpu-idle-states = <&cpu_pw15>;
77 #cooling-cells = <2>; 77 #cooling-cells = <2>;
78 }; 78 };
79 79
80 cpu101: cpu@101 { 80 cpu101: cpu@101 {
81 device_type = "cpu"; 81 device_type = "cpu";
82 compatible = "arm,cort 82 compatible = "arm,cortex-a72";
83 enable-method = "psci" 83 enable-method = "psci";
84 reg = <0x101>; 84 reg = <0x101>;
85 clocks = <&clockgen QO 85 clocks = <&clockgen QORIQ_CLK_CMUX 1>;
86 d-cache-size = <0x8000 86 d-cache-size = <0x8000>;
87 d-cache-line-size = <6 87 d-cache-line-size = <64>;
88 d-cache-sets = <128>; 88 d-cache-sets = <128>;
89 i-cache-size = <0xC000 89 i-cache-size = <0xC000>;
90 i-cache-line-size = <6 90 i-cache-line-size = <64>;
91 i-cache-sets = <192>; 91 i-cache-sets = <192>;
92 next-level-cache = <&c 92 next-level-cache = <&cluster1_l2>;
93 cpu-idle-states = <&cp 93 cpu-idle-states = <&cpu_pw15>;
94 #cooling-cells = <2>; 94 #cooling-cells = <2>;
95 }; 95 };
96 96
97 cpu200: cpu@200 { 97 cpu200: cpu@200 {
98 device_type = "cpu"; 98 device_type = "cpu";
99 compatible = "arm,cort 99 compatible = "arm,cortex-a72";
100 enable-method = "psci" 100 enable-method = "psci";
101 reg = <0x200>; 101 reg = <0x200>;
102 clocks = <&clockgen QO 102 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
103 d-cache-size = <0x8000 103 d-cache-size = <0x8000>;
104 d-cache-line-size = <6 104 d-cache-line-size = <64>;
105 d-cache-sets = <128>; 105 d-cache-sets = <128>;
106 i-cache-size = <0xC000 106 i-cache-size = <0xC000>;
107 i-cache-line-size = <6 107 i-cache-line-size = <64>;
108 i-cache-sets = <192>; 108 i-cache-sets = <192>;
109 next-level-cache = <&c 109 next-level-cache = <&cluster2_l2>;
110 cpu-idle-states = <&cp 110 cpu-idle-states = <&cpu_pw15>;
111 #cooling-cells = <2>; 111 #cooling-cells = <2>;
112 }; 112 };
113 113
114 cpu201: cpu@201 { 114 cpu201: cpu@201 {
115 device_type = "cpu"; 115 device_type = "cpu";
116 compatible = "arm,cort 116 compatible = "arm,cortex-a72";
117 enable-method = "psci" 117 enable-method = "psci";
118 reg = <0x201>; 118 reg = <0x201>;
119 clocks = <&clockgen QO 119 clocks = <&clockgen QORIQ_CLK_CMUX 2>;
120 d-cache-size = <0x8000 120 d-cache-size = <0x8000>;
121 d-cache-line-size = <6 121 d-cache-line-size = <64>;
122 d-cache-sets = <128>; 122 d-cache-sets = <128>;
123 i-cache-size = <0xC000 123 i-cache-size = <0xC000>;
124 i-cache-line-size = <6 124 i-cache-line-size = <64>;
125 i-cache-sets = <192>; 125 i-cache-sets = <192>;
126 next-level-cache = <&c 126 next-level-cache = <&cluster2_l2>;
127 cpu-idle-states = <&cp 127 cpu-idle-states = <&cpu_pw15>;
128 #cooling-cells = <2>; 128 #cooling-cells = <2>;
129 }; 129 };
130 130
131 cpu300: cpu@300 { 131 cpu300: cpu@300 {
132 device_type = "cpu"; 132 device_type = "cpu";
133 compatible = "arm,cort 133 compatible = "arm,cortex-a72";
134 enable-method = "psci" 134 enable-method = "psci";
135 reg = <0x300>; 135 reg = <0x300>;
136 clocks = <&clockgen QO 136 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
137 d-cache-size = <0x8000 137 d-cache-size = <0x8000>;
138 d-cache-line-size = <6 138 d-cache-line-size = <64>;
139 d-cache-sets = <128>; 139 d-cache-sets = <128>;
140 i-cache-size = <0xC000 140 i-cache-size = <0xC000>;
141 i-cache-line-size = <6 141 i-cache-line-size = <64>;
142 i-cache-sets = <192>; 142 i-cache-sets = <192>;
143 next-level-cache = <&c 143 next-level-cache = <&cluster3_l2>;
144 cpu-idle-states = <&cp 144 cpu-idle-states = <&cpu_pw15>;
145 #cooling-cells = <2>; 145 #cooling-cells = <2>;
146 }; 146 };
147 147
148 cpu301: cpu@301 { 148 cpu301: cpu@301 {
149 device_type = "cpu"; 149 device_type = "cpu";
150 compatible = "arm,cort 150 compatible = "arm,cortex-a72";
151 enable-method = "psci" 151 enable-method = "psci";
152 reg = <0x301>; 152 reg = <0x301>;
153 clocks = <&clockgen QO 153 clocks = <&clockgen QORIQ_CLK_CMUX 3>;
154 d-cache-size = <0x8000 154 d-cache-size = <0x8000>;
155 d-cache-line-size = <6 155 d-cache-line-size = <64>;
156 d-cache-sets = <128>; 156 d-cache-sets = <128>;
157 i-cache-size = <0xC000 157 i-cache-size = <0xC000>;
158 i-cache-line-size = <6 158 i-cache-line-size = <64>;
159 i-cache-sets = <192>; 159 i-cache-sets = <192>;
160 next-level-cache = <&c 160 next-level-cache = <&cluster3_l2>;
161 cpu-idle-states = <&cp 161 cpu-idle-states = <&cpu_pw15>;
162 #cooling-cells = <2>; 162 #cooling-cells = <2>;
163 }; 163 };
164 164
165 cpu400: cpu@400 { 165 cpu400: cpu@400 {
166 device_type = "cpu"; 166 device_type = "cpu";
167 compatible = "arm,cort 167 compatible = "arm,cortex-a72";
168 enable-method = "psci" 168 enable-method = "psci";
169 reg = <0x400>; 169 reg = <0x400>;
170 clocks = <&clockgen QO 170 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
171 d-cache-size = <0x8000 171 d-cache-size = <0x8000>;
172 d-cache-line-size = <6 172 d-cache-line-size = <64>;
173 d-cache-sets = <128>; 173 d-cache-sets = <128>;
174 i-cache-size = <0xC000 174 i-cache-size = <0xC000>;
175 i-cache-line-size = <6 175 i-cache-line-size = <64>;
176 i-cache-sets = <192>; 176 i-cache-sets = <192>;
177 next-level-cache = <&c 177 next-level-cache = <&cluster4_l2>;
178 cpu-idle-states = <&cp 178 cpu-idle-states = <&cpu_pw15>;
179 #cooling-cells = <2>; 179 #cooling-cells = <2>;
180 }; 180 };
181 181
182 cpu401: cpu@401 { 182 cpu401: cpu@401 {
183 device_type = "cpu"; 183 device_type = "cpu";
184 compatible = "arm,cort 184 compatible = "arm,cortex-a72";
185 enable-method = "psci" 185 enable-method = "psci";
186 reg = <0x401>; 186 reg = <0x401>;
187 clocks = <&clockgen QO 187 clocks = <&clockgen QORIQ_CLK_CMUX 4>;
188 d-cache-size = <0x8000 188 d-cache-size = <0x8000>;
189 d-cache-line-size = <6 189 d-cache-line-size = <64>;
190 d-cache-sets = <128>; 190 d-cache-sets = <128>;
191 i-cache-size = <0xC000 191 i-cache-size = <0xC000>;
192 i-cache-line-size = <6 192 i-cache-line-size = <64>;
193 i-cache-sets = <192>; 193 i-cache-sets = <192>;
194 next-level-cache = <&c 194 next-level-cache = <&cluster4_l2>;
195 cpu-idle-states = <&cp 195 cpu-idle-states = <&cpu_pw15>;
196 #cooling-cells = <2>; 196 #cooling-cells = <2>;
197 }; 197 };
198 198
199 cpu500: cpu@500 { 199 cpu500: cpu@500 {
200 device_type = "cpu"; 200 device_type = "cpu";
201 compatible = "arm,cort 201 compatible = "arm,cortex-a72";
202 enable-method = "psci" 202 enable-method = "psci";
203 reg = <0x500>; 203 reg = <0x500>;
204 clocks = <&clockgen QO 204 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
205 d-cache-size = <0x8000 205 d-cache-size = <0x8000>;
206 d-cache-line-size = <6 206 d-cache-line-size = <64>;
207 d-cache-sets = <128>; 207 d-cache-sets = <128>;
208 i-cache-size = <0xC000 208 i-cache-size = <0xC000>;
209 i-cache-line-size = <6 209 i-cache-line-size = <64>;
210 i-cache-sets = <192>; 210 i-cache-sets = <192>;
211 next-level-cache = <&c 211 next-level-cache = <&cluster5_l2>;
212 cpu-idle-states = <&cp 212 cpu-idle-states = <&cpu_pw15>;
213 #cooling-cells = <2>; 213 #cooling-cells = <2>;
214 }; 214 };
215 215
216 cpu501: cpu@501 { 216 cpu501: cpu@501 {
217 device_type = "cpu"; 217 device_type = "cpu";
218 compatible = "arm,cort 218 compatible = "arm,cortex-a72";
219 enable-method = "psci" 219 enable-method = "psci";
220 reg = <0x501>; 220 reg = <0x501>;
221 clocks = <&clockgen QO 221 clocks = <&clockgen QORIQ_CLK_CMUX 5>;
222 d-cache-size = <0x8000 222 d-cache-size = <0x8000>;
223 d-cache-line-size = <6 223 d-cache-line-size = <64>;
224 d-cache-sets = <128>; 224 d-cache-sets = <128>;
225 i-cache-size = <0xC000 225 i-cache-size = <0xC000>;
226 i-cache-line-size = <6 226 i-cache-line-size = <64>;
227 i-cache-sets = <192>; 227 i-cache-sets = <192>;
228 next-level-cache = <&c 228 next-level-cache = <&cluster5_l2>;
229 cpu-idle-states = <&cp 229 cpu-idle-states = <&cpu_pw15>;
230 #cooling-cells = <2>; 230 #cooling-cells = <2>;
231 }; 231 };
232 232
233 cpu600: cpu@600 { 233 cpu600: cpu@600 {
234 device_type = "cpu"; 234 device_type = "cpu";
235 compatible = "arm,cort 235 compatible = "arm,cortex-a72";
236 enable-method = "psci" 236 enable-method = "psci";
237 reg = <0x600>; 237 reg = <0x600>;
238 clocks = <&clockgen QO 238 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
239 d-cache-size = <0x8000 239 d-cache-size = <0x8000>;
240 d-cache-line-size = <6 240 d-cache-line-size = <64>;
241 d-cache-sets = <128>; 241 d-cache-sets = <128>;
242 i-cache-size = <0xC000 242 i-cache-size = <0xC000>;
243 i-cache-line-size = <6 243 i-cache-line-size = <64>;
244 i-cache-sets = <192>; 244 i-cache-sets = <192>;
245 next-level-cache = <&c 245 next-level-cache = <&cluster6_l2>;
246 cpu-idle-states = <&cp 246 cpu-idle-states = <&cpu_pw15>;
247 #cooling-cells = <2>; 247 #cooling-cells = <2>;
248 }; 248 };
249 249
250 cpu601: cpu@601 { 250 cpu601: cpu@601 {
251 device_type = "cpu"; 251 device_type = "cpu";
252 compatible = "arm,cort 252 compatible = "arm,cortex-a72";
253 enable-method = "psci" 253 enable-method = "psci";
254 reg = <0x601>; 254 reg = <0x601>;
255 clocks = <&clockgen QO 255 clocks = <&clockgen QORIQ_CLK_CMUX 6>;
256 d-cache-size = <0x8000 256 d-cache-size = <0x8000>;
257 d-cache-line-size = <6 257 d-cache-line-size = <64>;
258 d-cache-sets = <128>; 258 d-cache-sets = <128>;
259 i-cache-size = <0xC000 259 i-cache-size = <0xC000>;
260 i-cache-line-size = <6 260 i-cache-line-size = <64>;
261 i-cache-sets = <192>; 261 i-cache-sets = <192>;
262 next-level-cache = <&c 262 next-level-cache = <&cluster6_l2>;
263 cpu-idle-states = <&cp 263 cpu-idle-states = <&cpu_pw15>;
264 #cooling-cells = <2>; 264 #cooling-cells = <2>;
265 }; 265 };
266 266
267 cpu700: cpu@700 { 267 cpu700: cpu@700 {
268 device_type = "cpu"; 268 device_type = "cpu";
269 compatible = "arm,cort 269 compatible = "arm,cortex-a72";
270 enable-method = "psci" 270 enable-method = "psci";
271 reg = <0x700>; 271 reg = <0x700>;
272 clocks = <&clockgen QO 272 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
273 d-cache-size = <0x8000 273 d-cache-size = <0x8000>;
274 d-cache-line-size = <6 274 d-cache-line-size = <64>;
275 d-cache-sets = <128>; 275 d-cache-sets = <128>;
276 i-cache-size = <0xC000 276 i-cache-size = <0xC000>;
277 i-cache-line-size = <6 277 i-cache-line-size = <64>;
278 i-cache-sets = <192>; 278 i-cache-sets = <192>;
279 next-level-cache = <&c 279 next-level-cache = <&cluster7_l2>;
280 cpu-idle-states = <&cp 280 cpu-idle-states = <&cpu_pw15>;
281 #cooling-cells = <2>; 281 #cooling-cells = <2>;
282 }; 282 };
283 283
284 cpu701: cpu@701 { 284 cpu701: cpu@701 {
285 device_type = "cpu"; 285 device_type = "cpu";
286 compatible = "arm,cort 286 compatible = "arm,cortex-a72";
287 enable-method = "psci" 287 enable-method = "psci";
288 reg = <0x701>; 288 reg = <0x701>;
289 clocks = <&clockgen QO 289 clocks = <&clockgen QORIQ_CLK_CMUX 7>;
290 d-cache-size = <0x8000 290 d-cache-size = <0x8000>;
291 d-cache-line-size = <6 291 d-cache-line-size = <64>;
292 d-cache-sets = <128>; 292 d-cache-sets = <128>;
293 i-cache-size = <0xC000 293 i-cache-size = <0xC000>;
294 i-cache-line-size = <6 294 i-cache-line-size = <64>;
295 i-cache-sets = <192>; 295 i-cache-sets = <192>;
296 next-level-cache = <&c 296 next-level-cache = <&cluster7_l2>;
297 cpu-idle-states = <&cp 297 cpu-idle-states = <&cpu_pw15>;
298 #cooling-cells = <2>; 298 #cooling-cells = <2>;
299 }; 299 };
300 300
301 cluster0_l2: l2-cache0 { 301 cluster0_l2: l2-cache0 {
302 compatible = "cache"; 302 compatible = "cache";
303 cache-unified; 303 cache-unified;
304 cache-size = <0x100000 304 cache-size = <0x100000>;
305 cache-line-size = <64> 305 cache-line-size = <64>;
306 cache-sets = <1024>; 306 cache-sets = <1024>;
307 cache-level = <2>; 307 cache-level = <2>;
308 }; 308 };
309 309
310 cluster1_l2: l2-cache1 { 310 cluster1_l2: l2-cache1 {
311 compatible = "cache"; 311 compatible = "cache";
312 cache-unified; 312 cache-unified;
313 cache-size = <0x100000 313 cache-size = <0x100000>;
314 cache-line-size = <64> 314 cache-line-size = <64>;
315 cache-sets = <1024>; 315 cache-sets = <1024>;
316 cache-level = <2>; 316 cache-level = <2>;
317 }; 317 };
318 318
319 cluster2_l2: l2-cache2 { 319 cluster2_l2: l2-cache2 {
320 compatible = "cache"; 320 compatible = "cache";
321 cache-unified; 321 cache-unified;
322 cache-size = <0x100000 322 cache-size = <0x100000>;
323 cache-line-size = <64> 323 cache-line-size = <64>;
324 cache-sets = <1024>; 324 cache-sets = <1024>;
325 cache-level = <2>; 325 cache-level = <2>;
326 }; 326 };
327 327
328 cluster3_l2: l2-cache3 { 328 cluster3_l2: l2-cache3 {
329 compatible = "cache"; 329 compatible = "cache";
330 cache-unified; 330 cache-unified;
331 cache-size = <0x100000 331 cache-size = <0x100000>;
332 cache-line-size = <64> 332 cache-line-size = <64>;
333 cache-sets = <1024>; 333 cache-sets = <1024>;
334 cache-level = <2>; 334 cache-level = <2>;
335 }; 335 };
336 336
337 cluster4_l2: l2-cache4 { 337 cluster4_l2: l2-cache4 {
338 compatible = "cache"; 338 compatible = "cache";
339 cache-unified; 339 cache-unified;
340 cache-size = <0x100000 340 cache-size = <0x100000>;
341 cache-line-size = <64> 341 cache-line-size = <64>;
342 cache-sets = <1024>; 342 cache-sets = <1024>;
343 cache-level = <2>; 343 cache-level = <2>;
344 }; 344 };
345 345
346 cluster5_l2: l2-cache5 { 346 cluster5_l2: l2-cache5 {
347 compatible = "cache"; 347 compatible = "cache";
348 cache-unified; 348 cache-unified;
349 cache-size = <0x100000 349 cache-size = <0x100000>;
350 cache-line-size = <64> 350 cache-line-size = <64>;
351 cache-sets = <1024>; 351 cache-sets = <1024>;
352 cache-level = <2>; 352 cache-level = <2>;
353 }; 353 };
354 354
355 cluster6_l2: l2-cache6 { 355 cluster6_l2: l2-cache6 {
356 compatible = "cache"; 356 compatible = "cache";
357 cache-unified; 357 cache-unified;
358 cache-size = <0x100000 358 cache-size = <0x100000>;
359 cache-line-size = <64> 359 cache-line-size = <64>;
360 cache-sets = <1024>; 360 cache-sets = <1024>;
361 cache-level = <2>; 361 cache-level = <2>;
362 }; 362 };
363 363
364 cluster7_l2: l2-cache7 { 364 cluster7_l2: l2-cache7 {
365 compatible = "cache"; 365 compatible = "cache";
366 cache-unified; 366 cache-unified;
367 cache-size = <0x100000 367 cache-size = <0x100000>;
368 cache-line-size = <64> 368 cache-line-size = <64>;
369 cache-sets = <1024>; 369 cache-sets = <1024>;
370 cache-level = <2>; 370 cache-level = <2>;
371 }; 371 };
372 372
373 cpu_pw15: cpu-pw15 { 373 cpu_pw15: cpu-pw15 {
374 compatible = "arm,idle 374 compatible = "arm,idle-state";
375 idle-state-name = "PW1 375 idle-state-name = "PW15";
376 arm,psci-suspend-param 376 arm,psci-suspend-param = <0x0>;
377 entry-latency-us = <20 377 entry-latency-us = <2000>;
378 exit-latency-us = <200 378 exit-latency-us = <2000>;
379 min-residency-us = <60 379 min-residency-us = <6000>;
380 }; 380 };
381 }; 381 };
382 382
383 gic: interrupt-controller@6000000 { 383 gic: interrupt-controller@6000000 {
384 compatible = "arm,gic-v3"; 384 compatible = "arm,gic-v3";
385 reg = <0x0 0x06000000 0 0x1000 385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x20 386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
387 387 // SGI_base)
388 <0x0 0x0c0c0000 0 0x20 388 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x10 389 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20 390 <0x0 0x0c0e0000 0 0x20000>; // GICV
391 #interrupt-cells = <3>; 391 #interrupt-cells = <3>;
392 #address-cells = <2>; 392 #address-cells = <2>;
393 #size-cells = <2>; 393 #size-cells = <2>;
394 ranges; 394 ranges;
395 interrupt-controller; 395 interrupt-controller;
396 interrupts = <GIC_PPI 9 IRQ_TY 396 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
397 397
398 its: msi-controller@6020000 { 398 its: msi-controller@6020000 {
399 compatible = "arm,gic- 399 compatible = "arm,gic-v3-its";
400 msi-controller; 400 msi-controller;
401 #msi-cells = <1>; 401 #msi-cells = <1>;
402 reg = <0x0 0x6020000 0 402 reg = <0x0 0x6020000 0 0x20000>;
403 }; 403 };
404 }; 404 };
405 405
406 timer { 406 timer {
407 compatible = "arm,armv8-timer" 407 compatible = "arm,armv8-timer";
408 interrupts = <GIC_PPI 13 IRQ_T 408 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_PPI 14 IRQ_T 409 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_PPI 11 IRQ_T 410 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
411 <GIC_PPI 10 IRQ_T 411 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
412 }; 412 };
413 413
414 pmu { 414 pmu {
415 compatible = "arm,cortex-a72-p 415 compatible = "arm,cortex-a72-pmu";
416 interrupts = <GIC_PPI 7 IRQ_TY 416 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
417 }; 417 };
418 418
419 psci { 419 psci {
420 compatible = "arm,psci-0.2"; 420 compatible = "arm,psci-0.2";
421 method = "smc"; 421 method = "smc";
422 }; 422 };
423 423
424 memory@80000000 { 424 memory@80000000 {
425 // DRAM space - 1, size : 2 GB 425 // DRAM space - 1, size : 2 GB DRAM
426 device_type = "memory"; 426 device_type = "memory";
427 reg = <0x00000000 0x80000000 0 427 reg = <0x00000000 0x80000000 0 0x80000000>;
428 }; 428 };
429 429
430 ddr1: memory-controller@1080000 { 430 ddr1: memory-controller@1080000 {
431 compatible = "fsl,qoriq-memory 431 compatible = "fsl,qoriq-memory-controller";
432 reg = <0x0 0x1080000 0x0 0x100 432 reg = <0x0 0x1080000 0x0 0x1000>;
433 interrupts = <GIC_SPI 17 IRQ_T 433 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
434 little-endian; 434 little-endian;
435 }; 435 };
436 436
437 ddr2: memory-controller@1090000 { 437 ddr2: memory-controller@1090000 {
438 compatible = "fsl,qoriq-memory 438 compatible = "fsl,qoriq-memory-controller";
439 reg = <0x0 0x1090000 0x0 0x100 439 reg = <0x0 0x1090000 0x0 0x1000>;
440 interrupts = <GIC_SPI 18 IRQ_T 440 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
441 little-endian; 441 little-endian;
442 }; 442 };
443 443
444 // One clock unit-sysclk node which bo 444 // One clock unit-sysclk node which bootloader require during DT fix-up
445 sysclk: sysclk { 445 sysclk: sysclk {
446 compatible = "fixed-clock"; 446 compatible = "fixed-clock";
447 #clock-cells = <0>; 447 #clock-cells = <0>;
448 clock-frequency = <100000000>; 448 clock-frequency = <100000000>; // fixed up by bootloader
449 clock-output-names = "sysclk"; 449 clock-output-names = "sysclk";
450 }; 450 };
451 451
452 thermal-zones { 452 thermal-zones {
453 cluster6-7-thermal { 453 cluster6-7-thermal {
454 polling-delay-passive 454 polling-delay-passive = <1000>;
455 polling-delay = <5000> 455 polling-delay = <5000>;
456 thermal-sensors = <&tm 456 thermal-sensors = <&tmu 0>;
457 457
458 trips { 458 trips {
459 cluster6_7_ale 459 cluster6_7_alert: cluster6-7-alert {
460 temper 460 temperature = <85000>;
461 hyster 461 hysteresis = <2000>;
462 type = 462 type = "passive";
463 }; 463 };
464 464
465 cluster6_7_cri 465 cluster6_7_crit: cluster6-7-crit {
466 temper 466 temperature = <95000>;
467 hyster 467 hysteresis = <2000>;
468 type = 468 type = "critical";
469 }; 469 };
470 }; 470 };
471 471
472 cooling-maps { 472 cooling-maps {
473 map0 { 473 map0 {
474 trip = 474 trip = <&cluster6_7_alert>;
475 coolin 475 cooling-device =
476 476 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
477 477 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
478 478 <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
479 479 <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
480 480 <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
481 481 <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
482 482 <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
483 483 <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
484 484 <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
485 485 <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
486 486 <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
487 487 <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
488 488 <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 489 <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 490 <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 491 <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
492 }; 492 };
493 }; 493 };
494 }; 494 };
495 495
496 ddr-ctrl5-thermal { 496 ddr-ctrl5-thermal {
497 polling-delay-passive 497 polling-delay-passive = <1000>;
498 polling-delay = <5000> 498 polling-delay = <5000>;
499 thermal-sensors = <&tm 499 thermal-sensors = <&tmu 1>;
500 500
501 trips { 501 trips {
502 ddr-cluster5-a 502 ddr-cluster5-alert {
503 temper 503 temperature = <85000>;
504 hyster 504 hysteresis = <2000>;
505 type = 505 type = "passive";
506 }; 506 };
507 507
508 ddr-cluster5-c 508 ddr-cluster5-crit {
509 temper 509 temperature = <95000>;
510 hyster 510 hysteresis = <2000>;
511 type = 511 type = "critical";
512 }; 512 };
513 }; 513 };
514 }; 514 };
515 515
516 wriop-thermal { 516 wriop-thermal {
517 polling-delay-passive 517 polling-delay-passive = <1000>;
518 polling-delay = <5000> 518 polling-delay = <5000>;
519 thermal-sensors = <&tm 519 thermal-sensors = <&tmu 2>;
520 520
521 trips { 521 trips {
522 wriop-alert { 522 wriop-alert {
523 temper 523 temperature = <85000>;
524 hyster 524 hysteresis = <2000>;
525 type = 525 type = "passive";
526 }; 526 };
527 527
528 wriop-crit { 528 wriop-crit {
529 temper 529 temperature = <95000>;
530 hyster 530 hysteresis = <2000>;
531 type = 531 type = "critical";
532 }; 532 };
533 }; 533 };
534 }; 534 };
535 535
536 dce-thermal { 536 dce-thermal {
537 polling-delay-passive 537 polling-delay-passive = <1000>;
538 polling-delay = <5000> 538 polling-delay = <5000>;
539 thermal-sensors = <&tm 539 thermal-sensors = <&tmu 3>;
540 540
541 trips { 541 trips {
542 dce-qbman-aler 542 dce-qbman-alert {
543 temper 543 temperature = <85000>;
544 hyster 544 hysteresis = <2000>;
545 type = 545 type = "passive";
546 }; 546 };
547 547
548 dce-qbman-crit 548 dce-qbman-crit {
549 temper 549 temperature = <95000>;
550 hyster 550 hysteresis = <2000>;
551 type = 551 type = "critical";
552 }; 552 };
553 }; 553 };
554 }; 554 };
555 555
556 ccn-thermal { 556 ccn-thermal {
557 polling-delay-passive 557 polling-delay-passive = <1000>;
558 polling-delay = <5000> 558 polling-delay = <5000>;
559 thermal-sensors = <&tm 559 thermal-sensors = <&tmu 4>;
560 560
561 trips { 561 trips {
562 ccn-dpaa-alert 562 ccn-dpaa-alert {
563 temper 563 temperature = <85000>;
564 hyster 564 hysteresis = <2000>;
565 type = 565 type = "passive";
566 }; 566 };
567 567
568 ccn-dpaa-crit 568 ccn-dpaa-crit {
569 temper 569 temperature = <95000>;
570 hyster 570 hysteresis = <2000>;
571 type = 571 type = "critical";
572 }; 572 };
573 }; 573 };
574 }; 574 };
575 575
576 cluster4-thermal { 576 cluster4-thermal {
577 polling-delay-passive 577 polling-delay-passive = <1000>;
578 polling-delay = <5000> 578 polling-delay = <5000>;
579 thermal-sensors = <&tm 579 thermal-sensors = <&tmu 5>;
580 580
581 trips { 581 trips {
582 clust4-hsio3-a 582 clust4-hsio3-alert {
583 temper 583 temperature = <85000>;
584 hyster 584 hysteresis = <2000>;
585 type = 585 type = "passive";
586 }; 586 };
587 587
588 clust4-hsio3-c 588 clust4-hsio3-crit {
589 temper 589 temperature = <95000>;
590 hyster 590 hysteresis = <2000>;
591 type = 591 type = "critical";
592 }; 592 };
593 }; 593 };
594 }; 594 };
595 595
596 cluster2-3-thermal { 596 cluster2-3-thermal {
597 polling-delay-passive 597 polling-delay-passive = <1000>;
598 polling-delay = <5000> 598 polling-delay = <5000>;
599 thermal-sensors = <&tm 599 thermal-sensors = <&tmu 6>;
600 600
601 trips { 601 trips {
602 cluster2-3-ale 602 cluster2-3-alert {
603 temper 603 temperature = <85000>;
604 hyster 604 hysteresis = <2000>;
605 type = 605 type = "passive";
606 }; 606 };
607 607
608 cluster2-3-cri 608 cluster2-3-crit {
609 temper 609 temperature = <95000>;
610 hyster 610 hysteresis = <2000>;
611 type = 611 type = "critical";
612 }; 612 };
613 }; 613 };
614 }; 614 };
615 }; 615 };
616 616
617 soc { 617 soc {
618 compatible = "simple-bus"; 618 compatible = "simple-bus";
619 #address-cells = <2>; 619 #address-cells = <2>;
620 #size-cells = <2>; 620 #size-cells = <2>;
621 ranges; 621 ranges;
622 dma-ranges = <0x0 0x0 0x0 0x0 622 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
623 623
624 serdes_1: phy@1ea0000 { 624 serdes_1: phy@1ea0000 {
625 compatible = "fsl,lynx 625 compatible = "fsl,lynx-28g";
626 reg = <0x0 0x1ea0000 0 626 reg = <0x0 0x1ea0000 0x0 0x1e30>;
627 #phy-cells = <1>; 627 #phy-cells = <1>;
628 }; 628 };
629 629
630 serdes_2: phy@1eb0000 { 630 serdes_2: phy@1eb0000 {
631 compatible = "fsl,lynx 631 compatible = "fsl,lynx-28g";
632 reg = <0x0 0x1eb0000 0 632 reg = <0x0 0x1eb0000 0x0 0x1e30>;
633 #phy-cells = <1>; 633 #phy-cells = <1>;
634 status = "disabled"; 634 status = "disabled";
635 }; 635 };
636 636
637 crypto: crypto@8000000 { 637 crypto: crypto@8000000 {
638 compatible = "fsl,sec- 638 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
639 fsl,sec-era = <10>; 639 fsl,sec-era = <10>;
640 #address-cells = <1>; 640 #address-cells = <1>;
641 #size-cells = <1>; 641 #size-cells = <1>;
642 ranges = <0x0 0x00 0x8 642 ranges = <0x0 0x00 0x8000000 0x100000>;
643 reg = <0x00 0x8000000 643 reg = <0x00 0x8000000 0x0 0x100000>;
644 interrupts = <GIC_SPI 644 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
645 dma-coherent; 645 dma-coherent;
646 status = "disabled"; 646 status = "disabled";
647 647
648 sec_jr0: jr@10000 { 648 sec_jr0: jr@10000 {
649 compatible = " 649 compatible = "fsl,sec-v5.0-job-ring",
650 " 650 "fsl,sec-v4.0-job-ring";
651 reg = <0x10000 651 reg = <0x10000 0x10000>;
652 interrupts = < 652 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
653 }; 653 };
654 654
655 sec_jr1: jr@20000 { 655 sec_jr1: jr@20000 {
656 compatible = " 656 compatible = "fsl,sec-v5.0-job-ring",
657 " 657 "fsl,sec-v4.0-job-ring";
658 reg = <0x20000 658 reg = <0x20000 0x10000>;
659 interrupts = < 659 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
660 }; 660 };
661 661
662 sec_jr2: jr@30000 { 662 sec_jr2: jr@30000 {
663 compatible = " 663 compatible = "fsl,sec-v5.0-job-ring",
664 " 664 "fsl,sec-v4.0-job-ring";
665 reg = <0x30000 665 reg = <0x30000 0x10000>;
666 interrupts = < 666 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
667 }; 667 };
668 668
669 sec_jr3: jr@40000 { 669 sec_jr3: jr@40000 {
670 compatible = " 670 compatible = "fsl,sec-v5.0-job-ring",
671 " 671 "fsl,sec-v4.0-job-ring";
672 reg = <0x40000 672 reg = <0x40000 0x10000>;
673 interrupts = < 673 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
674 }; 674 };
675 }; 675 };
676 676
677 clockgen: clock-controller@130 677 clockgen: clock-controller@1300000 {
678 compatible = "fsl,lx21 678 compatible = "fsl,lx2160a-clockgen";
679 reg = <0 0x1300000 0 0 679 reg = <0 0x1300000 0 0xa0000>;
680 #clock-cells = <2>; 680 #clock-cells = <2>;
681 clocks = <&sysclk>; 681 clocks = <&sysclk>;
682 }; 682 };
683 683
684 dcfg: syscon@1e00000 { 684 dcfg: syscon@1e00000 {
685 compatible = "fsl,lx21 685 compatible = "fsl,lx2160a-dcfg", "syscon";
686 reg = <0x0 0x1e00000 0 686 reg = <0x0 0x1e00000 0x0 0x10000>;
687 little-endian; 687 little-endian;
688 }; 688 };
689 689
690 sfp: efuse@1e80000 { 690 sfp: efuse@1e80000 {
691 compatible = "fsl,ls10 691 compatible = "fsl,ls1028a-sfp";
692 reg = <0x0 0x1e80000 0 692 reg = <0x0 0x1e80000 0x0 0x10000>;
693 clocks = <&clockgen QO 693 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
694 QO 694 QORIQ_CLK_PLL_DIV(4)>;
695 clock-names = "sfp"; 695 clock-names = "sfp";
696 }; 696 };
697 697
698 isc: syscon@1f70000 { 698 isc: syscon@1f70000 {
699 compatible = "fsl,lx21 699 compatible = "fsl,lx2160a-isc", "syscon";
700 reg = <0x0 0x1f70000 0 700 reg = <0x0 0x1f70000 0x0 0x10000>;
701 little-endian; 701 little-endian;
702 #address-cells = <1>; 702 #address-cells = <1>;
703 #size-cells = <1>; 703 #size-cells = <1>;
704 ranges = <0x0 0x0 0x1f 704 ranges = <0x0 0x0 0x1f70000 0x10000>;
705 705
706 extirq: interrupt-cont 706 extirq: interrupt-controller@14 {
707 compatible = " 707 compatible = "fsl,lx2160a-extirq", "fsl,ls1088a-extirq";
708 #interrupt-cel 708 #interrupt-cells = <2>;
709 #address-cells 709 #address-cells = <0>;
710 interrupt-cont 710 interrupt-controller;
711 reg = <0x14 4> 711 reg = <0x14 4>;
712 interrupt-map 712 interrupt-map =
713 <0 0 & 713 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
714 <1 0 & 714 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
715 <2 0 & 715 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
716 <3 0 & 716 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
717 <4 0 & 717 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
718 <5 0 & 718 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
719 <6 0 & 719 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
720 <7 0 & 720 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
721 <8 0 & 721 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
722 <9 0 & 722 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
723 <10 0 723 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
724 <11 0 724 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-map- 725 interrupt-map-mask = <0xf 0x0>;
726 }; 726 };
727 }; 727 };
728 728
729 tmu: tmu@1f80000 { 729 tmu: tmu@1f80000 {
730 compatible = "fsl,qori 730 compatible = "fsl,qoriq-tmu";
731 reg = <0x0 0x1f80000 0 731 reg = <0x0 0x1f80000 0x0 0x10000>;
732 interrupts = <GIC_SPI 732 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
733 fsl,tmu-range = <0x800 733 fsl,tmu-range = <0x800000e6 0x8001017d>;
734 fsl,tmu-calibration = 734 fsl,tmu-calibration =
735 /* Calibration 735 /* Calibration data group 1 */
736 <0x00000000 0x 736 <0x00000000 0x00000035>,
737 /* Calibration 737 /* Calibration data group 2 */
738 <0x00000001 0x 738 <0x00000001 0x00000154>;
739 little-endian; 739 little-endian;
740 #thermal-sensor-cells 740 #thermal-sensor-cells = <1>;
741 }; 741 };
742 742
743 i2c0: i2c@2000000 { 743 i2c0: i2c@2000000 {
744 compatible = "fsl,vf61 744 compatible = "fsl,vf610-i2c";
745 #address-cells = <1>; 745 #address-cells = <1>;
746 #size-cells = <0>; 746 #size-cells = <0>;
747 reg = <0x0 0x2000000 0 747 reg = <0x0 0x2000000 0x0 0x10000>;
748 interrupts = <GIC_SPI 748 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
749 clock-names = "ipg"; 749 clock-names = "ipg";
750 clocks = <&clockgen QO 750 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
751 QO 751 QORIQ_CLK_PLL_DIV(16)>;
752 pinctrl-names = "defau 752 pinctrl-names = "default", "gpio";
753 pinctrl-0 = <&i2c0_scl 753 pinctrl-0 = <&i2c0_scl>;
754 pinctrl-1 = <&i2c0_scl 754 pinctrl-1 = <&i2c0_scl_gpio>;
755 scl-gpios = <&gpio0 3 755 scl-gpios = <&gpio0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
756 status = "disabled"; 756 status = "disabled";
757 }; 757 };
758 758
759 i2c1: i2c@2010000 { 759 i2c1: i2c@2010000 {
760 compatible = "fsl,vf61 760 compatible = "fsl,vf610-i2c";
761 #address-cells = <1>; 761 #address-cells = <1>;
762 #size-cells = <0>; 762 #size-cells = <0>;
763 reg = <0x0 0x2010000 0 763 reg = <0x0 0x2010000 0x0 0x10000>;
764 interrupts = <GIC_SPI 764 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
765 clock-names = "ipg"; 765 clock-names = "ipg";
766 clocks = <&clockgen QO 766 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
767 QO 767 QORIQ_CLK_PLL_DIV(16)>;
768 pinctrl-names = "defau 768 pinctrl-names = "default", "gpio";
769 pinctrl-0 = <&i2c1_scl 769 pinctrl-0 = <&i2c1_scl>;
770 pinctrl-1 = <&i2c1_scl 770 pinctrl-1 = <&i2c1_scl_gpio>;
771 scl-gpios = <&gpio0 31 771 scl-gpios = <&gpio0 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
772 status = "disabled"; 772 status = "disabled";
773 }; 773 };
774 774
775 i2c2: i2c@2020000 { 775 i2c2: i2c@2020000 {
776 compatible = "fsl,vf61 776 compatible = "fsl,vf610-i2c";
777 #address-cells = <1>; 777 #address-cells = <1>;
778 #size-cells = <0>; 778 #size-cells = <0>;
779 reg = <0x0 0x2020000 0 779 reg = <0x0 0x2020000 0x0 0x10000>;
780 interrupts = <GIC_SPI 780 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
781 clock-names = "ipg"; 781 clock-names = "ipg";
782 clocks = <&clockgen QO 782 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
783 QO 783 QORIQ_CLK_PLL_DIV(16)>;
784 pinctrl-names = "defau 784 pinctrl-names = "default", "gpio";
785 pinctrl-0 = <&i2c2_scl 785 pinctrl-0 = <&i2c2_scl>;
786 pinctrl-1 = <&i2c2_scl 786 pinctrl-1 = <&i2c2_scl_gpio>;
787 scl-gpios = <&gpio0 29 787 scl-gpios = <&gpio0 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
788 status = "disabled"; 788 status = "disabled";
789 }; 789 };
790 790
791 i2c3: i2c@2030000 { 791 i2c3: i2c@2030000 {
792 compatible = "fsl,vf61 792 compatible = "fsl,vf610-i2c";
793 #address-cells = <1>; 793 #address-cells = <1>;
794 #size-cells = <0>; 794 #size-cells = <0>;
795 reg = <0x0 0x2030000 0 795 reg = <0x0 0x2030000 0x0 0x10000>;
796 interrupts = <GIC_SPI 796 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
797 clock-names = "ipg"; 797 clock-names = "ipg";
798 clocks = <&clockgen QO 798 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
799 QO 799 QORIQ_CLK_PLL_DIV(16)>;
800 pinctrl-names = "defau 800 pinctrl-names = "default", "gpio";
801 pinctrl-0 = <&i2c3_scl 801 pinctrl-0 = <&i2c3_scl>;
802 pinctrl-1 = <&i2c3_scl 802 pinctrl-1 = <&i2c3_scl_gpio>;
803 scl-gpios = <&gpio0 27 803 scl-gpios = <&gpio0 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
804 status = "disabled"; 804 status = "disabled";
805 }; 805 };
806 806
807 i2c4: i2c@2040000 { 807 i2c4: i2c@2040000 {
808 compatible = "fsl,vf61 808 compatible = "fsl,vf610-i2c";
809 #address-cells = <1>; 809 #address-cells = <1>;
810 #size-cells = <0>; 810 #size-cells = <0>;
811 reg = <0x0 0x2040000 0 811 reg = <0x0 0x2040000 0x0 0x10000>;
812 interrupts = <GIC_SPI 812 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
813 clock-names = "ipg"; 813 clock-names = "ipg";
814 clocks = <&clockgen QO 814 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
815 QO 815 QORIQ_CLK_PLL_DIV(16)>;
816 pinctrl-names = "defau 816 pinctrl-names = "default", "gpio";
817 pinctrl-0 = <&i2c4_scl 817 pinctrl-0 = <&i2c4_scl>;
818 pinctrl-1 = <&i2c4_scl 818 pinctrl-1 = <&i2c4_scl_gpio>;
819 scl-gpios = <&gpio0 25 819 scl-gpios = <&gpio0 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
820 status = "disabled"; 820 status = "disabled";
821 }; 821 };
822 822
823 i2c5: i2c@2050000 { 823 i2c5: i2c@2050000 {
824 compatible = "fsl,vf61 824 compatible = "fsl,vf610-i2c";
825 #address-cells = <1>; 825 #address-cells = <1>;
826 #size-cells = <0>; 826 #size-cells = <0>;
827 reg = <0x0 0x2050000 0 827 reg = <0x0 0x2050000 0x0 0x10000>;
828 interrupts = <GIC_SPI 828 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
829 clock-names = "ipg"; 829 clock-names = "ipg";
830 clocks = <&clockgen QO 830 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
831 QO 831 QORIQ_CLK_PLL_DIV(16)>;
832 pinctrl-names = "defau 832 pinctrl-names = "default", "gpio";
833 pinctrl-0 = <&i2c5_scl 833 pinctrl-0 = <&i2c5_scl>;
834 pinctrl-1 = <&i2c5_scl 834 pinctrl-1 = <&i2c5_scl_gpio>;
835 scl-gpios = <&gpio0 23 835 scl-gpios = <&gpio0 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
836 status = "disabled"; 836 status = "disabled";
837 }; 837 };
838 838
839 i2c6: i2c@2060000 { 839 i2c6: i2c@2060000 {
840 compatible = "fsl,vf61 840 compatible = "fsl,vf610-i2c";
841 #address-cells = <1>; 841 #address-cells = <1>;
842 #size-cells = <0>; 842 #size-cells = <0>;
843 reg = <0x0 0x2060000 0 843 reg = <0x0 0x2060000 0x0 0x10000>;
844 interrupts = <GIC_SPI 844 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
845 clock-names = "ipg"; 845 clock-names = "ipg";
846 clocks = <&clockgen QO 846 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
847 QO 847 QORIQ_CLK_PLL_DIV(16)>;
848 pinctrl-names = "defau 848 pinctrl-names = "default", "gpio";
849 pinctrl-0 = <&i2c6_scl 849 pinctrl-0 = <&i2c6_scl>;
850 pinctrl-1 = <&i2c6_scl 850 pinctrl-1 = <&i2c6_scl_gpio>;
851 scl-gpios = <&gpio1 16 851 scl-gpios = <&gpio1 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
852 status = "disabled"; 852 status = "disabled";
853 }; 853 };
854 854
855 i2c7: i2c@2070000 { 855 i2c7: i2c@2070000 {
856 compatible = "fsl,vf61 856 compatible = "fsl,vf610-i2c";
857 #address-cells = <1>; 857 #address-cells = <1>;
858 #size-cells = <0>; 858 #size-cells = <0>;
859 reg = <0x0 0x2070000 0 859 reg = <0x0 0x2070000 0x0 0x10000>;
860 interrupts = <GIC_SPI 860 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
861 clock-names = "ipg"; 861 clock-names = "ipg";
862 clocks = <&clockgen QO 862 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
863 QO 863 QORIQ_CLK_PLL_DIV(16)>;
864 pinctrl-names = "defau 864 pinctrl-names = "default", "gpio";
865 pinctrl-0 = <&i2c7_scl 865 pinctrl-0 = <&i2c7_scl>;
866 pinctrl-1 = <&i2c7_scl 866 pinctrl-1 = <&i2c7_scl_gpio>;
867 scl-gpios = <&gpio1 18 867 scl-gpios = <&gpio1 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
868 status = "disabled"; 868 status = "disabled";
869 }; 869 };
870 870
871 fspi: spi@20c0000 { 871 fspi: spi@20c0000 {
872 compatible = "nxp,lx21 872 compatible = "nxp,lx2160a-fspi";
873 #address-cells = <1>; 873 #address-cells = <1>;
874 #size-cells = <0>; 874 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0 875 reg = <0x0 0x20c0000 0x0 0x10000>,
876 <0x0 0x20000000 876 <0x0 0x20000000 0x0 0x10000000>;
877 reg-names = "fspi_base 877 reg-names = "fspi_base", "fspi_mmap";
878 interrupts = <GIC_SPI 878 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
879 clocks = <&clockgen QO 879 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
880 QO 880 QORIQ_CLK_PLL_DIV(4)>,
881 <&clockgen QO 881 <&clockgen QORIQ_CLK_PLATFORM_PLL
882 QO 882 QORIQ_CLK_PLL_DIV(4)>;
883 clock-names = "fspi_en 883 clock-names = "fspi_en", "fspi";
884 status = "disabled"; 884 status = "disabled";
885 }; 885 };
886 886
887 dspi0: spi@2100000 { 887 dspi0: spi@2100000 {
888 compatible = "fsl,lx21 888 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
889 #address-cells = <1>; 889 #address-cells = <1>;
890 #size-cells = <0>; 890 #size-cells = <0>;
891 reg = <0x0 0x2100000 0 891 reg = <0x0 0x2100000 0x0 0x10000>;
892 interrupts = <GIC_SPI 892 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
893 clocks = <&clockgen QO 893 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
894 QO 894 QORIQ_CLK_PLL_DIV(8)>;
895 clock-names = "dspi"; 895 clock-names = "dspi";
896 spi-num-chipselects = 896 spi-num-chipselects = <5>;
897 bus-num = <0>; 897 bus-num = <0>;
898 status = "disabled"; 898 status = "disabled";
899 }; 899 };
900 900
901 dspi1: spi@2110000 { 901 dspi1: spi@2110000 {
902 compatible = "fsl,lx21 902 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
903 #address-cells = <1>; 903 #address-cells = <1>;
904 #size-cells = <0>; 904 #size-cells = <0>;
905 reg = <0x0 0x2110000 0 905 reg = <0x0 0x2110000 0x0 0x10000>;
906 interrupts = <GIC_SPI 906 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
907 clocks = <&clockgen QO 907 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
908 QO 908 QORIQ_CLK_PLL_DIV(8)>;
909 clock-names = "dspi"; 909 clock-names = "dspi";
910 spi-num-chipselects = 910 spi-num-chipselects = <5>;
911 bus-num = <1>; 911 bus-num = <1>;
912 status = "disabled"; 912 status = "disabled";
913 }; 913 };
914 914
915 dspi2: spi@2120000 { 915 dspi2: spi@2120000 {
916 compatible = "fsl,lx21 916 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi";
917 #address-cells = <1>; 917 #address-cells = <1>;
918 #size-cells = <0>; 918 #size-cells = <0>;
919 reg = <0x0 0x2120000 0 919 reg = <0x0 0x2120000 0x0 0x10000>;
920 interrupts = <GIC_SPI 920 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&clockgen QO 921 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
922 QO 922 QORIQ_CLK_PLL_DIV(8)>;
923 clock-names = "dspi"; 923 clock-names = "dspi";
924 spi-num-chipselects = 924 spi-num-chipselects = <5>;
925 bus-num = <2>; 925 bus-num = <2>;
926 status = "disabled"; 926 status = "disabled";
927 }; 927 };
928 928
929 esdhc0: mmc@2140000 { 929 esdhc0: mmc@2140000 {
930 compatible = "fsl,ls20 930 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
931 reg = <0x0 0x2140000 0 931 reg = <0x0 0x2140000 0x0 0x10000>;
932 interrupts = <GIC_SPI 932 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&clockgen QO 933 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
934 QO 934 QORIQ_CLK_PLL_DIV(2)>;
935 dma-coherent; 935 dma-coherent;
936 voltage-ranges = <1800 936 voltage-ranges = <1800 1800 3300 3300>;
937 sdhci,auto-cmd12; 937 sdhci,auto-cmd12;
938 little-endian; 938 little-endian;
939 bus-width = <4>; 939 bus-width = <4>;
940 status = "disabled"; 940 status = "disabled";
941 }; 941 };
942 942
943 esdhc1: mmc@2150000 { 943 esdhc1: mmc@2150000 {
944 compatible = "fsl,ls20 944 compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
945 reg = <0x0 0x2150000 0 945 reg = <0x0 0x2150000 0x0 0x10000>;
946 interrupts = <GIC_SPI 946 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clockgen QO 947 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
948 QO 948 QORIQ_CLK_PLL_DIV(2)>;
949 dma-coherent; 949 dma-coherent;
950 voltage-ranges = <1800 950 voltage-ranges = <1800 1800 3300 3300>;
951 sdhci,auto-cmd12; 951 sdhci,auto-cmd12;
952 broken-cd; 952 broken-cd;
953 little-endian; 953 little-endian;
954 bus-width = <4>; 954 bus-width = <4>;
955 status = "disabled"; 955 status = "disabled";
956 }; 956 };
957 957
958 can0: can@2180000 { 958 can0: can@2180000 {
959 compatible = "fsl,lx21 959 compatible = "fsl,lx2160ar1-flexcan";
960 reg = <0x0 0x2180000 0 960 reg = <0x0 0x2180000 0x0 0x10000>;
961 interrupts = <GIC_SPI 961 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
962 clocks = <&clockgen QO 962 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
963 QO 963 QORIQ_CLK_PLL_DIV(8)>,
964 <&clockgen QO 964 <&clockgen QORIQ_CLK_SYSCLK 0>;
965 clock-names = "ipg", " 965 clock-names = "ipg", "per";
966 fsl,clk-source = /bits 966 fsl,clk-source = /bits/ 8 <0>;
967 status = "disabled"; 967 status = "disabled";
968 }; 968 };
969 969
970 can1: can@2190000 { 970 can1: can@2190000 {
971 compatible = "fsl,lx21 971 compatible = "fsl,lx2160ar1-flexcan";
972 reg = <0x0 0x2190000 0 972 reg = <0x0 0x2190000 0x0 0x10000>;
973 interrupts = <GIC_SPI 973 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
974 clocks = <&clockgen QO 974 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
975 QO 975 QORIQ_CLK_PLL_DIV(8)>,
976 <&clockgen QO 976 <&clockgen QORIQ_CLK_SYSCLK 0>;
977 clock-names = "ipg", " 977 clock-names = "ipg", "per";
978 fsl,clk-source = /bits 978 fsl,clk-source = /bits/ 8 <0>;
979 status = "disabled"; 979 status = "disabled";
980 }; 980 };
981 981
982 uart0: serial@21c0000 { 982 uart0: serial@21c0000 {
983 compatible = "arm,pl01 983 compatible = "arm,pl011", "arm,primecell";
984 clocks = <&clockgen QO 984 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
985 QO 985 QORIQ_CLK_PLL_DIV(8)>,
986 <&clockgen QO 986 <&clockgen QORIQ_CLK_PLATFORM_PLL
987 QO 987 QORIQ_CLK_PLL_DIV(8)>;
988 clock-names = "uartclk 988 clock-names = "uartclk", "apb_pclk";
989 reg = <0x0 0x21c0000 0 989 reg = <0x0 0x21c0000 0x0 0x1000>;
990 interrupts = <GIC_SPI 990 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
991 status = "disabled"; 991 status = "disabled";
992 }; 992 };
993 993
994 uart1: serial@21d0000 { 994 uart1: serial@21d0000 {
995 compatible = "arm,pl01 995 compatible = "arm,pl011", "arm,primecell";
996 clocks = <&clockgen QO 996 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
997 QO 997 QORIQ_CLK_PLL_DIV(8)>,
998 <&clockgen QO 998 <&clockgen QORIQ_CLK_PLATFORM_PLL
999 QO 999 QORIQ_CLK_PLL_DIV(8)>;
1000 clock-names = "uartcl 1000 clock-names = "uartclk", "apb_pclk";
1001 reg = <0x0 0x21d0000 1001 reg = <0x0 0x21d0000 0x0 0x1000>;
1002 interrupts = <GIC_SPI 1002 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1003 status = "disabled"; 1003 status = "disabled";
1004 }; 1004 };
1005 1005
1006 uart2: serial@21e0000 { 1006 uart2: serial@21e0000 {
1007 compatible = "arm,pl0 1007 compatible = "arm,pl011", "arm,primecell";
1008 clocks = <&clockgen Q 1008 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1009 Q 1009 QORIQ_CLK_PLL_DIV(8)>,
1010 <&clockgen Q 1010 <&clockgen QORIQ_CLK_PLATFORM_PLL
1011 Q 1011 QORIQ_CLK_PLL_DIV(8)>;
1012 clock-names = "uartcl 1012 clock-names = "uartclk", "apb_pclk";
1013 reg = <0x0 0x21e0000 1013 reg = <0x0 0x21e0000 0x0 0x1000>;
1014 interrupts = <GIC_SPI 1014 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
1015 status = "disabled"; 1015 status = "disabled";
1016 }; 1016 };
1017 1017
1018 uart3: serial@21f0000 { 1018 uart3: serial@21f0000 {
1019 compatible = "arm,pl0 1019 compatible = "arm,pl011", "arm,primecell";
1020 clocks = <&clockgen Q 1020 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1021 Q 1021 QORIQ_CLK_PLL_DIV(8)>,
1022 <&clockgen Q 1022 <&clockgen QORIQ_CLK_PLATFORM_PLL
1023 Q 1023 QORIQ_CLK_PLL_DIV(8)>;
1024 clock-names = "uartcl 1024 clock-names = "uartclk", "apb_pclk";
1025 reg = <0x0 0x21f0000 1025 reg = <0x0 0x21f0000 0x0 0x1000>;
1026 interrupts = <GIC_SPI 1026 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1027 status = "disabled"; 1027 status = "disabled";
1028 }; 1028 };
1029 1029
1030 gpio0: gpio@2300000 { 1030 gpio0: gpio@2300000 {
1031 compatible = "fsl,ls2 1031 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1032 reg = <0x0 0x2300000 1032 reg = <0x0 0x2300000 0x0 0x10000>;
1033 interrupts = <GIC_SPI 1033 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1034 gpio-controller; 1034 gpio-controller;
1035 little-endian; 1035 little-endian;
1036 #gpio-cells = <2>; 1036 #gpio-cells = <2>;
1037 interrupt-controller; 1037 interrupt-controller;
1038 #interrupt-cells = <2 1038 #interrupt-cells = <2>;
1039 }; 1039 };
1040 1040
1041 gpio1: gpio@2310000 { 1041 gpio1: gpio@2310000 {
1042 compatible = "fsl,ls2 1042 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1043 reg = <0x0 0x2310000 1043 reg = <0x0 0x2310000 0x0 0x10000>;
1044 interrupts = <GIC_SPI 1044 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1045 gpio-controller; 1045 gpio-controller;
1046 little-endian; 1046 little-endian;
1047 #gpio-cells = <2>; 1047 #gpio-cells = <2>;
1048 interrupt-controller; 1048 interrupt-controller;
1049 #interrupt-cells = <2 1049 #interrupt-cells = <2>;
1050 }; 1050 };
1051 1051
1052 gpio2: gpio@2320000 { 1052 gpio2: gpio@2320000 {
1053 compatible = "fsl,ls2 1053 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1054 reg = <0x0 0x2320000 1054 reg = <0x0 0x2320000 0x0 0x10000>;
1055 interrupts = <GIC_SPI 1055 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1056 gpio-controller; 1056 gpio-controller;
1057 little-endian; 1057 little-endian;
1058 #gpio-cells = <2>; 1058 #gpio-cells = <2>;
1059 interrupt-controller; 1059 interrupt-controller;
1060 #interrupt-cells = <2 1060 #interrupt-cells = <2>;
1061 }; 1061 };
1062 1062
1063 gpio3: gpio@2330000 { 1063 gpio3: gpio@2330000 {
1064 compatible = "fsl,ls2 1064 compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
1065 reg = <0x0 0x2330000 1065 reg = <0x0 0x2330000 0x0 0x10000>;
1066 interrupts = <GIC_SPI 1066 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1067 gpio-controller; 1067 gpio-controller;
1068 little-endian; 1068 little-endian;
1069 #gpio-cells = <2>; 1069 #gpio-cells = <2>;
1070 interrupt-controller; 1070 interrupt-controller;
1071 #interrupt-cells = <2 1071 #interrupt-cells = <2>;
1072 }; 1072 };
1073 1073
1074 watchdog@23a0000 { 1074 watchdog@23a0000 {
1075 compatible = "arm,sbs 1075 compatible = "arm,sbsa-gwdt";
1076 reg = <0x0 0x23a0000 1076 reg = <0x0 0x23a0000 0 0x1000>,
1077 <0x0 0x2390000 1077 <0x0 0x2390000 0 0x1000>;
1078 interrupts = <GIC_SPI 1078 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1079 timeout-sec = <30>; 1079 timeout-sec = <30>;
1080 }; 1080 };
1081 1081
1082 rcpm: wakeup-controller@1e340 1082 rcpm: wakeup-controller@1e34040 {
1083 compatible = "fsl,lx2 1083 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+";
1084 reg = <0x0 0x1e34040 1084 reg = <0x0 0x1e34040 0x0 0x1c>;
1085 #fsl,rcpm-wakeup-cell 1085 #fsl,rcpm-wakeup-cells = <7>;
1086 little-endian; 1086 little-endian;
1087 }; 1087 };
1088 1088
1089 ftm_alarm0: rtc@2800000 { 1089 ftm_alarm0: rtc@2800000 {
1090 compatible = "fsl,lx2 1090 compatible = "fsl,lx2160a-ftm-alarm";
1091 reg = <0x0 0x2800000 1091 reg = <0x0 0x2800000 0x0 0x10000>;
1092 fsl,rcpm-wakeup = <&r 1092 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1093 interrupts = <GIC_SPI 1093 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
1094 }; 1094 };
1095 1095
1096 usb0: usb@3100000 { 1096 usb0: usb@3100000 {
1097 compatible = "snps,dw 1097 compatible = "snps,dwc3";
1098 reg = <0x0 0x3100000 1098 reg = <0x0 0x3100000 0x0 0x10000>;
1099 interrupts = <GIC_SPI 1099 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1100 dr_mode = "host"; 1100 dr_mode = "host";
1101 snps,quirk-frame-leng 1101 snps,quirk-frame-length-adjustment = <0x20>;
1102 usb3-lpm-capable; 1102 usb3-lpm-capable;
1103 snps,dis_rxdet_inp3_q 1103 snps,dis_rxdet_inp3_quirk;
1104 snps,incr-burst-type- 1104 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1105 status = "disabled"; 1105 status = "disabled";
1106 }; 1106 };
1107 1107
1108 usb1: usb@3110000 { 1108 usb1: usb@3110000 {
1109 compatible = "snps,dw 1109 compatible = "snps,dwc3";
1110 reg = <0x0 0x3110000 1110 reg = <0x0 0x3110000 0x0 0x10000>;
1111 interrupts = <GIC_SPI 1111 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1112 dr_mode = "host"; 1112 dr_mode = "host";
1113 snps,quirk-frame-leng 1113 snps,quirk-frame-length-adjustment = <0x20>;
1114 usb3-lpm-capable; 1114 usb3-lpm-capable;
1115 snps,dis_rxdet_inp3_q 1115 snps,dis_rxdet_inp3_quirk;
1116 snps,incr-burst-type- 1116 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
1117 status = "disabled"; 1117 status = "disabled";
1118 }; 1118 };
1119 1119
1120 sata0: sata@3200000 { 1120 sata0: sata@3200000 {
1121 compatible = "fsl,lx2 1121 compatible = "fsl,lx2160a-ahci";
1122 reg = <0x0 0x3200000 1122 reg = <0x0 0x3200000 0x0 0x10000>,
1123 <0x7 0x100520 0 1123 <0x7 0x100520 0x0 0x4>;
1124 reg-names = "ahci", " 1124 reg-names = "ahci", "sata-ecc";
1125 interrupts = <GIC_SPI 1125 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1126 clocks = <&clockgen Q 1126 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1127 Q 1127 QORIQ_CLK_PLL_DIV(4)>;
1128 dma-coherent; 1128 dma-coherent;
1129 status = "disabled"; 1129 status = "disabled";
1130 }; 1130 };
1131 1131
1132 sata1: sata@3210000 { 1132 sata1: sata@3210000 {
1133 compatible = "fsl,lx2 1133 compatible = "fsl,lx2160a-ahci";
1134 reg = <0x0 0x3210000 1134 reg = <0x0 0x3210000 0x0 0x10000>,
1135 <0x7 0x100520 0 1135 <0x7 0x100520 0x0 0x4>;
1136 reg-names = "ahci", " 1136 reg-names = "ahci", "sata-ecc";
1137 interrupts = <GIC_SPI 1137 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1138 clocks = <&clockgen Q 1138 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1139 Q 1139 QORIQ_CLK_PLL_DIV(4)>;
1140 dma-coherent; 1140 dma-coherent;
1141 status = "disabled"; 1141 status = "disabled";
1142 }; 1142 };
1143 1143
1144 sata2: sata@3220000 { 1144 sata2: sata@3220000 {
1145 compatible = "fsl,lx2 1145 compatible = "fsl,lx2160a-ahci";
1146 reg = <0x0 0x3220000 1146 reg = <0x0 0x3220000 0x0 0x10000>,
1147 <0x7 0x100520 0 1147 <0x7 0x100520 0x0 0x4>;
1148 reg-names = "ahci", " 1148 reg-names = "ahci", "sata-ecc";
1149 interrupts = <GIC_SPI 1149 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&clockgen Q 1150 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1151 Q 1151 QORIQ_CLK_PLL_DIV(4)>;
1152 dma-coherent; 1152 dma-coherent;
1153 status = "disabled"; 1153 status = "disabled";
1154 }; 1154 };
1155 1155
1156 sata3: sata@3230000 { 1156 sata3: sata@3230000 {
1157 compatible = "fsl,lx2 1157 compatible = "fsl,lx2160a-ahci";
1158 reg = <0x0 0x3230000 1158 reg = <0x0 0x3230000 0x0 0x10000>,
1159 <0x7 0x100520 0 1159 <0x7 0x100520 0x0 0x4>;
1160 reg-names = "ahci", " 1160 reg-names = "ahci", "sata-ecc";
1161 interrupts = <GIC_SPI 1161 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1162 clocks = <&clockgen Q 1162 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1163 Q 1163 QORIQ_CLK_PLL_DIV(4)>;
1164 dma-coherent; 1164 dma-coherent;
1165 status = "disabled"; 1165 status = "disabled";
1166 }; 1166 };
1167 1167
1168 pcie1: pcie@3400000 { 1168 pcie1: pcie@3400000 {
1169 compatible = "fsl,lx2 1169 compatible = "fsl,lx2160a-pcie";
1170 reg = <0x00 0x0340000 1170 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1171 <0x80 0x0000000 1171 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1172 reg-names = "csr_axi_ 1172 reg-names = "csr_axi_slave", "config_axi_slave";
1173 interrupts = <GIC_SPI 1173 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1174 <GIC_SPI 1174 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1175 <GIC_SPI 1175 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1176 interrupt-names = "ae 1176 interrupt-names = "aer", "pme", "intr";
1177 #address-cells = <3>; 1177 #address-cells = <3>;
1178 #size-cells = <2>; 1178 #size-cells = <2>;
1179 device_type = "pci"; 1179 device_type = "pci";
1180 dma-coherent; 1180 dma-coherent;
1181 apio-wins = <8>; 1181 apio-wins = <8>;
1182 ppio-wins = <8>; 1182 ppio-wins = <8>;
1183 bus-range = <0x0 0xff 1183 bus-range = <0x0 0xff>;
1184 ranges = <0x82000000 1184 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1185 msi-parent = <&its 0> 1185 msi-parent = <&its 0>;
1186 #interrupt-cells = <1 1186 #interrupt-cells = <1>;
1187 interrupt-map-mask = 1187 interrupt-map-mask = <0 0 0 7>;
1188 interrupt-map = <0000 1188 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1189 <0000 1189 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1190 <0000 1190 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1191 <0000 1191 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1192 iommu-map = <0 &smmu 1192 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1193 status = "disabled"; 1193 status = "disabled";
1194 }; 1194 };
1195 1195
1196 pcie2: pcie@3500000 { 1196 pcie2: pcie@3500000 {
1197 compatible = "fsl,lx2 1197 compatible = "fsl,lx2160a-pcie";
1198 reg = <0x00 0x0350000 1198 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1199 <0x88 0x0000000 1199 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1200 reg-names = "csr_axi_ 1200 reg-names = "csr_axi_slave", "config_axi_slave";
1201 interrupts = <GIC_SPI 1201 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1202 <GIC_SPI 1202 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1203 <GIC_SPI 1203 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1204 interrupt-names = "ae 1204 interrupt-names = "aer", "pme", "intr";
1205 #address-cells = <3>; 1205 #address-cells = <3>;
1206 #size-cells = <2>; 1206 #size-cells = <2>;
1207 device_type = "pci"; 1207 device_type = "pci";
1208 dma-coherent; 1208 dma-coherent;
1209 apio-wins = <8>; 1209 apio-wins = <8>;
1210 ppio-wins = <8>; 1210 ppio-wins = <8>;
1211 bus-range = <0x0 0xff 1211 bus-range = <0x0 0xff>;
1212 ranges = <0x82000000 1212 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1213 msi-parent = <&its 0> 1213 msi-parent = <&its 0>;
1214 #interrupt-cells = <1 1214 #interrupt-cells = <1>;
1215 interrupt-map-mask = 1215 interrupt-map-mask = <0 0 0 7>;
1216 interrupt-map = <0000 1216 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1217 <0000 1217 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1218 <0000 1218 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1219 <0000 1219 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1220 iommu-map = <0 &smmu 1220 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1221 status = "disabled"; 1221 status = "disabled";
1222 }; 1222 };
1223 1223
1224 pcie3: pcie@3600000 { 1224 pcie3: pcie@3600000 {
1225 compatible = "fsl,lx2 1225 compatible = "fsl,lx2160a-pcie";
1226 reg = <0x00 0x0360000 1226 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1227 <0x90 0x0000000 1227 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1228 reg-names = "csr_axi_ 1228 reg-names = "csr_axi_slave", "config_axi_slave";
1229 interrupts = <GIC_SPI 1229 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1230 <GIC_SPI 1230 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1231 <GIC_SPI 1231 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1232 interrupt-names = "ae 1232 interrupt-names = "aer", "pme", "intr";
1233 #address-cells = <3>; 1233 #address-cells = <3>;
1234 #size-cells = <2>; 1234 #size-cells = <2>;
1235 device_type = "pci"; 1235 device_type = "pci";
1236 dma-coherent; 1236 dma-coherent;
1237 apio-wins = <256>; 1237 apio-wins = <256>;
1238 ppio-wins = <24>; 1238 ppio-wins = <24>;
1239 bus-range = <0x0 0xff 1239 bus-range = <0x0 0xff>;
1240 ranges = <0x82000000 1240 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1241 msi-parent = <&its 0> 1241 msi-parent = <&its 0>;
1242 #interrupt-cells = <1 1242 #interrupt-cells = <1>;
1243 interrupt-map-mask = 1243 interrupt-map-mask = <0 0 0 7>;
1244 interrupt-map = <0000 1244 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245 <0000 1245 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1246 <0000 1246 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1247 <0000 1247 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1248 iommu-map = <0 &smmu 1248 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1249 status = "disabled"; 1249 status = "disabled";
1250 }; 1250 };
1251 1251
1252 pcie4: pcie@3700000 { 1252 pcie4: pcie@3700000 {
1253 compatible = "fsl,lx2 1253 compatible = "fsl,lx2160a-pcie";
1254 reg = <0x00 0x0370000 1254 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1255 <0x98 0x0000000 1255 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1256 reg-names = "csr_axi_ 1256 reg-names = "csr_axi_slave", "config_axi_slave";
1257 interrupts = <GIC_SPI 1257 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1258 <GIC_SPI 1258 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1259 <GIC_SPI 1259 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1260 interrupt-names = "ae 1260 interrupt-names = "aer", "pme", "intr";
1261 #address-cells = <3>; 1261 #address-cells = <3>;
1262 #size-cells = <2>; 1262 #size-cells = <2>;
1263 device_type = "pci"; 1263 device_type = "pci";
1264 dma-coherent; 1264 dma-coherent;
1265 apio-wins = <8>; 1265 apio-wins = <8>;
1266 ppio-wins = <8>; 1266 ppio-wins = <8>;
1267 bus-range = <0x0 0xff 1267 bus-range = <0x0 0xff>;
1268 ranges = <0x82000000 1268 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1269 msi-parent = <&its 0> 1269 msi-parent = <&its 0>;
1270 #interrupt-cells = <1 1270 #interrupt-cells = <1>;
1271 interrupt-map-mask = 1271 interrupt-map-mask = <0 0 0 7>;
1272 interrupt-map = <0000 1272 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1273 <0000 1273 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1274 <0000 1274 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1275 <0000 1275 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1276 iommu-map = <0 &smmu 1276 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1277 status = "disabled"; 1277 status = "disabled";
1278 }; 1278 };
1279 1279
1280 pcie5: pcie@3800000 { 1280 pcie5: pcie@3800000 {
1281 compatible = "fsl,lx2 1281 compatible = "fsl,lx2160a-pcie";
1282 reg = <0x00 0x0380000 1282 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1283 <0xa0 0x0000000 1283 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1284 reg-names = "csr_axi_ 1284 reg-names = "csr_axi_slave", "config_axi_slave";
1285 interrupts = <GIC_SPI 1285 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1286 <GIC_SPI 1286 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1287 <GIC_SPI 1287 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1288 interrupt-names = "ae 1288 interrupt-names = "aer", "pme", "intr";
1289 #address-cells = <3>; 1289 #address-cells = <3>;
1290 #size-cells = <2>; 1290 #size-cells = <2>;
1291 device_type = "pci"; 1291 device_type = "pci";
1292 dma-coherent; 1292 dma-coherent;
1293 apio-wins = <256>; 1293 apio-wins = <256>;
1294 ppio-wins = <24>; 1294 ppio-wins = <24>;
1295 bus-range = <0x0 0xff 1295 bus-range = <0x0 0xff>;
1296 ranges = <0x82000000 1296 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1297 msi-parent = <&its 0> 1297 msi-parent = <&its 0>;
1298 #interrupt-cells = <1 1298 #interrupt-cells = <1>;
1299 interrupt-map-mask = 1299 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0000 1300 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1301 <0000 1301 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1302 <0000 1302 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1303 <0000 1303 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1304 iommu-map = <0 &smmu 1304 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1305 status = "disabled"; 1305 status = "disabled";
1306 }; 1306 };
1307 1307
1308 pcie6: pcie@3900000 { 1308 pcie6: pcie@3900000 {
1309 compatible = "fsl,lx2 1309 compatible = "fsl,lx2160a-pcie";
1310 reg = <0x00 0x0390000 1310 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1311 <0xa8 0x0000000 1311 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1312 reg-names = "csr_axi_ 1312 reg-names = "csr_axi_slave", "config_axi_slave";
1313 interrupts = <GIC_SPI 1313 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
1314 <GIC_SPI 1314 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
1315 <GIC_SPI 1315 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
1316 interrupt-names = "ae 1316 interrupt-names = "aer", "pme", "intr";
1317 #address-cells = <3>; 1317 #address-cells = <3>;
1318 #size-cells = <2>; 1318 #size-cells = <2>;
1319 device_type = "pci"; 1319 device_type = "pci";
1320 dma-coherent; 1320 dma-coherent;
1321 apio-wins = <8>; 1321 apio-wins = <8>;
1322 ppio-wins = <8>; 1322 ppio-wins = <8>;
1323 bus-range = <0x0 0xff 1323 bus-range = <0x0 0xff>;
1324 ranges = <0x82000000 1324 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1325 msi-parent = <&its 0> 1325 msi-parent = <&its 0>;
1326 #interrupt-cells = <1 1326 #interrupt-cells = <1>;
1327 interrupt-map-mask = 1327 interrupt-map-mask = <0 0 0 7>;
1328 interrupt-map = <0000 1328 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1329 <0000 1329 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1330 <0000 1330 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1331 <0000 1331 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1332 iommu-map = <0 &smmu 1332 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1333 status = "disabled"; 1333 status = "disabled";
1334 }; 1334 };
1335 1335
1336 smmu: iommu@5000000 { 1336 smmu: iommu@5000000 {
1337 compatible = "arm,mmu 1337 compatible = "arm,mmu-500";
1338 reg = <0 0x5000000 0 1338 reg = <0 0x5000000 0 0x800000>;
1339 #iommu-cells = <1>; 1339 #iommu-cells = <1>;
1340 #global-interrupts = 1340 #global-interrupts = <14>;
1341 // globa 1341 // global secure fault
1342 interrupts = <GIC_SPI 1342 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
1343 // combi 1343 // combined secure
1344 <GIC_SPI 1344 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1345 // globa 1345 // global non-secure fault
1346 <GIC_SPI 1346 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
1347 // combi 1347 // combined non-secure
1348 <GIC_SPI 1348 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1349 // perfo 1349 // performance counter interrupts 0-9
1350 <GIC_SPI 1350 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
1351 <GIC_SPI 1351 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
1352 <GIC_SPI 1352 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
1353 <GIC_SPI 1353 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
1354 <GIC_SPI 1354 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
1355 <GIC_SPI 1355 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 1356 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 1357 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
1358 <GIC_SPI 1358 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
1359 <GIC_SPI 1359 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
1360 // per c 1360 // per context interrupt, 64 interrupts
1361 <GIC_SPI 1361 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1362 <GIC_SPI 1362 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
1363 <GIC_SPI 1363 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
1364 <GIC_SPI 1364 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
1365 <GIC_SPI 1365 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
1366 <GIC_SPI 1366 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
1367 <GIC_SPI 1367 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
1368 <GIC_SPI 1368 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
1369 <GIC_SPI 1369 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
1370 <GIC_SPI 1370 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
1371 <GIC_SPI 1371 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 1372 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
1373 <GIC_SPI 1373 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
1374 <GIC_SPI 1374 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
1375 <GIC_SPI 1375 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
1376 <GIC_SPI 1376 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
1377 <GIC_SPI 1377 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
1378 <GIC_SPI 1378 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1379 <GIC_SPI 1379 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
1380 <GIC_SPI 1380 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
1381 <GIC_SPI 1381 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
1382 <GIC_SPI 1382 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1383 <GIC_SPI 1383 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1384 <GIC_SPI 1384 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1385 <GIC_SPI 1385 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1386 <GIC_SPI 1386 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1387 <GIC_SPI 1387 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1388 <GIC_SPI 1388 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1389 <GIC_SPI 1389 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1390 <GIC_SPI 1390 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
1391 <GIC_SPI 1391 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1392 <GIC_SPI 1392 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
1393 <GIC_SPI 1393 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
1394 <GIC_SPI 1394 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
1395 <GIC_SPI 1395 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
1396 <GIC_SPI 1396 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1397 <GIC_SPI 1397 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1398 <GIC_SPI 1398 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1399 <GIC_SPI 1399 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1400 <GIC_SPI 1400 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1401 <GIC_SPI 1401 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1402 <GIC_SPI 1402 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1403 <GIC_SPI 1403 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1404 <GIC_SPI 1404 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1405 <GIC_SPI 1405 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1406 <GIC_SPI 1406 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1407 <GIC_SPI 1407 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1408 <GIC_SPI 1408 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
1409 <GIC_SPI 1409 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
1410 <GIC_SPI 1410 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
1411 <GIC_SPI 1411 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 1412 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 1413 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1414 <GIC_SPI 1414 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
1415 <GIC_SPI 1415 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
1416 <GIC_SPI 1416 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
1417 <GIC_SPI 1417 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
1418 <GIC_SPI 1418 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1419 <GIC_SPI 1419 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
1420 <GIC_SPI 1420 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
1421 <GIC_SPI 1421 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
1422 <GIC_SPI 1422 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
1423 <GIC_SPI 1423 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
1424 <GIC_SPI 1424 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1425 dma-coherent; 1425 dma-coherent;
1426 }; 1426 };
1427 1427
1428 console@8340020 { 1428 console@8340020 {
1429 compatible = "fsl,dpa 1429 compatible = "fsl,dpaa2-console";
1430 reg = <0x00000000 0x0 1430 reg = <0x00000000 0x08340020 0 0x2>;
1431 }; 1431 };
1432 1432
1433 ptp-timer@8b95000 { 1433 ptp-timer@8b95000 {
1434 compatible = "fsl,dpa 1434 compatible = "fsl,dpaa2-ptp";
1435 reg = <0x0 0x8b95000 1435 reg = <0x0 0x8b95000 0x0 0x100>;
1436 clocks = <&clockgen Q 1436 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1437 Q 1437 QORIQ_CLK_PLL_DIV(2)>;
1438 little-endian; 1438 little-endian;
1439 fsl,extts-fifo; 1439 fsl,extts-fifo;
1440 }; 1440 };
1441 1441
1442 /* WRIOP0: 0x8b8_0000, E-MDIO 1442 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1443 emdio1: mdio@8b96000 { 1443 emdio1: mdio@8b96000 {
1444 compatible = "fsl,fma 1444 compatible = "fsl,fman-memac-mdio";
1445 reg = <0x0 0x8b96000 1445 reg = <0x0 0x8b96000 0x0 0x1000>;
1446 interrupts = <GIC_SPI 1446 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1447 #address-cells = <1>; 1447 #address-cells = <1>;
1448 #size-cells = <0>; 1448 #size-cells = <0>;
1449 little-endian; 1449 little-endian;
1450 clock-frequency = <25 1450 clock-frequency = <2500000>;
1451 clocks = <&clockgen Q 1451 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1452 Q 1452 QORIQ_CLK_PLL_DIV(2)>;
1453 status = "disabled"; 1453 status = "disabled";
1454 }; 1454 };
1455 1455
1456 emdio2: mdio@8b97000 { 1456 emdio2: mdio@8b97000 {
1457 compatible = "fsl,fma 1457 compatible = "fsl,fman-memac-mdio";
1458 reg = <0x0 0x8b97000 1458 reg = <0x0 0x8b97000 0x0 0x1000>;
1459 interrupts = <GIC_SPI 1459 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1460 little-endian; 1460 little-endian;
1461 #address-cells = <1>; 1461 #address-cells = <1>;
1462 #size-cells = <0>; 1462 #size-cells = <0>;
1463 clock-frequency = <25 1463 clock-frequency = <2500000>;
1464 clocks = <&clockgen Q 1464 clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
1465 Q 1465 QORIQ_CLK_PLL_DIV(2)>;
1466 status = "disabled"; 1466 status = "disabled";
1467 }; 1467 };
1468 1468
1469 pcs_mdio1: mdio@8c07000 { 1469 pcs_mdio1: mdio@8c07000 {
1470 compatible = "fsl,fma 1470 compatible = "fsl,fman-memac-mdio";
1471 reg = <0x0 0x8c07000 1471 reg = <0x0 0x8c07000 0x0 0x1000>;
1472 little-endian; 1472 little-endian;
1473 #address-cells = <1>; 1473 #address-cells = <1>;
1474 #size-cells = <0>; 1474 #size-cells = <0>;
1475 status = "disabled"; 1475 status = "disabled";
1476 1476
1477 pcs1: ethernet-phy@0 1477 pcs1: ethernet-phy@0 {
1478 reg = <0>; 1478 reg = <0>;
1479 }; 1479 };
1480 }; 1480 };
1481 1481
1482 pcs_mdio2: mdio@8c0b000 { 1482 pcs_mdio2: mdio@8c0b000 {
1483 compatible = "fsl,fma 1483 compatible = "fsl,fman-memac-mdio";
1484 reg = <0x0 0x8c0b000 1484 reg = <0x0 0x8c0b000 0x0 0x1000>;
1485 little-endian; 1485 little-endian;
1486 #address-cells = <1>; 1486 #address-cells = <1>;
1487 #size-cells = <0>; 1487 #size-cells = <0>;
1488 status = "disabled"; 1488 status = "disabled";
1489 1489
1490 pcs2: ethernet-phy@0 1490 pcs2: ethernet-phy@0 {
1491 reg = <0>; 1491 reg = <0>;
1492 }; 1492 };
1493 }; 1493 };
1494 1494
1495 pcs_mdio3: mdio@8c0f000 { 1495 pcs_mdio3: mdio@8c0f000 {
1496 compatible = "fsl,fma 1496 compatible = "fsl,fman-memac-mdio";
1497 reg = <0x0 0x8c0f000 1497 reg = <0x0 0x8c0f000 0x0 0x1000>;
1498 little-endian; 1498 little-endian;
1499 #address-cells = <1>; 1499 #address-cells = <1>;
1500 #size-cells = <0>; 1500 #size-cells = <0>;
1501 status = "disabled"; 1501 status = "disabled";
1502 1502
1503 pcs3: ethernet-phy@0 1503 pcs3: ethernet-phy@0 {
1504 reg = <0>; 1504 reg = <0>;
1505 }; 1505 };
1506 }; 1506 };
1507 1507
1508 pcs_mdio4: mdio@8c13000 { 1508 pcs_mdio4: mdio@8c13000 {
1509 compatible = "fsl,fma 1509 compatible = "fsl,fman-memac-mdio";
1510 reg = <0x0 0x8c13000 1510 reg = <0x0 0x8c13000 0x0 0x1000>;
1511 little-endian; 1511 little-endian;
1512 #address-cells = <1>; 1512 #address-cells = <1>;
1513 #size-cells = <0>; 1513 #size-cells = <0>;
1514 status = "disabled"; 1514 status = "disabled";
1515 1515
1516 pcs4: ethernet-phy@0 1516 pcs4: ethernet-phy@0 {
1517 reg = <0>; 1517 reg = <0>;
1518 }; 1518 };
1519 }; 1519 };
1520 1520
1521 pcs_mdio5: mdio@8c17000 { 1521 pcs_mdio5: mdio@8c17000 {
1522 compatible = "fsl,fma 1522 compatible = "fsl,fman-memac-mdio";
1523 reg = <0x0 0x8c17000 1523 reg = <0x0 0x8c17000 0x0 0x1000>;
1524 little-endian; 1524 little-endian;
1525 #address-cells = <1>; 1525 #address-cells = <1>;
1526 #size-cells = <0>; 1526 #size-cells = <0>;
1527 status = "disabled"; 1527 status = "disabled";
1528 1528
1529 pcs5: ethernet-phy@0 1529 pcs5: ethernet-phy@0 {
1530 reg = <0>; 1530 reg = <0>;
1531 }; 1531 };
1532 }; 1532 };
1533 1533
1534 pcs_mdio6: mdio@8c1b000 { 1534 pcs_mdio6: mdio@8c1b000 {
1535 compatible = "fsl,fma 1535 compatible = "fsl,fman-memac-mdio";
1536 reg = <0x0 0x8c1b000 1536 reg = <0x0 0x8c1b000 0x0 0x1000>;
1537 little-endian; 1537 little-endian;
1538 #address-cells = <1>; 1538 #address-cells = <1>;
1539 #size-cells = <0>; 1539 #size-cells = <0>;
1540 status = "disabled"; 1540 status = "disabled";
1541 1541
1542 pcs6: ethernet-phy@0 1542 pcs6: ethernet-phy@0 {
1543 reg = <0>; 1543 reg = <0>;
1544 }; 1544 };
1545 }; 1545 };
1546 1546
1547 pcs_mdio7: mdio@8c1f000 { 1547 pcs_mdio7: mdio@8c1f000 {
1548 compatible = "fsl,fma 1548 compatible = "fsl,fman-memac-mdio";
1549 reg = <0x0 0x8c1f000 1549 reg = <0x0 0x8c1f000 0x0 0x1000>;
1550 little-endian; 1550 little-endian;
1551 #address-cells = <1>; 1551 #address-cells = <1>;
1552 #size-cells = <0>; 1552 #size-cells = <0>;
1553 status = "disabled"; 1553 status = "disabled";
1554 1554
1555 pcs7: ethernet-phy@0 1555 pcs7: ethernet-phy@0 {
1556 reg = <0>; 1556 reg = <0>;
1557 }; 1557 };
1558 }; 1558 };
1559 1559
1560 pcs_mdio8: mdio@8c23000 { 1560 pcs_mdio8: mdio@8c23000 {
1561 compatible = "fsl,fma 1561 compatible = "fsl,fman-memac-mdio";
1562 reg = <0x0 0x8c23000 1562 reg = <0x0 0x8c23000 0x0 0x1000>;
1563 little-endian; 1563 little-endian;
1564 #address-cells = <1>; 1564 #address-cells = <1>;
1565 #size-cells = <0>; 1565 #size-cells = <0>;
1566 status = "disabled"; 1566 status = "disabled";
1567 1567
1568 pcs8: ethernet-phy@0 1568 pcs8: ethernet-phy@0 {
1569 reg = <0>; 1569 reg = <0>;
1570 }; 1570 };
1571 }; 1571 };
1572 1572
1573 pcs_mdio9: mdio@8c27000 { 1573 pcs_mdio9: mdio@8c27000 {
1574 compatible = "fsl,fma 1574 compatible = "fsl,fman-memac-mdio";
1575 reg = <0x0 0x8c27000 1575 reg = <0x0 0x8c27000 0x0 0x1000>;
1576 little-endian; 1576 little-endian;
1577 #address-cells = <1>; 1577 #address-cells = <1>;
1578 #size-cells = <0>; 1578 #size-cells = <0>;
1579 status = "disabled"; 1579 status = "disabled";
1580 1580
1581 pcs9: ethernet-phy@0 1581 pcs9: ethernet-phy@0 {
1582 reg = <0>; 1582 reg = <0>;
1583 }; 1583 };
1584 }; 1584 };
1585 1585
1586 pcs_mdio10: mdio@8c2b000 { 1586 pcs_mdio10: mdio@8c2b000 {
1587 compatible = "fsl,fma 1587 compatible = "fsl,fman-memac-mdio";
1588 reg = <0x0 0x8c2b000 1588 reg = <0x0 0x8c2b000 0x0 0x1000>;
1589 little-endian; 1589 little-endian;
1590 #address-cells = <1>; 1590 #address-cells = <1>;
1591 #size-cells = <0>; 1591 #size-cells = <0>;
1592 status = "disabled"; 1592 status = "disabled";
1593 1593
1594 pcs10: ethernet-phy@0 1594 pcs10: ethernet-phy@0 {
1595 reg = <0>; 1595 reg = <0>;
1596 }; 1596 };
1597 }; 1597 };
1598 1598
1599 pcs_mdio11: mdio@8c2f000 { 1599 pcs_mdio11: mdio@8c2f000 {
1600 compatible = "fsl,fma 1600 compatible = "fsl,fman-memac-mdio";
1601 reg = <0x0 0x8c2f000 1601 reg = <0x0 0x8c2f000 0x0 0x1000>;
1602 little-endian; 1602 little-endian;
1603 #address-cells = <1>; 1603 #address-cells = <1>;
1604 #size-cells = <0>; 1604 #size-cells = <0>;
1605 status = "disabled"; 1605 status = "disabled";
1606 1606
1607 pcs11: ethernet-phy@0 1607 pcs11: ethernet-phy@0 {
1608 reg = <0>; 1608 reg = <0>;
1609 }; 1609 };
1610 }; 1610 };
1611 1611
1612 pcs_mdio12: mdio@8c33000 { 1612 pcs_mdio12: mdio@8c33000 {
1613 compatible = "fsl,fma 1613 compatible = "fsl,fman-memac-mdio";
1614 reg = <0x0 0x8c33000 1614 reg = <0x0 0x8c33000 0x0 0x1000>;
1615 little-endian; 1615 little-endian;
1616 #address-cells = <1>; 1616 #address-cells = <1>;
1617 #size-cells = <0>; 1617 #size-cells = <0>;
1618 status = "disabled"; 1618 status = "disabled";
1619 1619
1620 pcs12: ethernet-phy@0 1620 pcs12: ethernet-phy@0 {
1621 reg = <0>; 1621 reg = <0>;
1622 }; 1622 };
1623 }; 1623 };
1624 1624
1625 pcs_mdio13: mdio@8c37000 { 1625 pcs_mdio13: mdio@8c37000 {
1626 compatible = "fsl,fma 1626 compatible = "fsl,fman-memac-mdio";
1627 reg = <0x0 0x8c37000 1627 reg = <0x0 0x8c37000 0x0 0x1000>;
1628 little-endian; 1628 little-endian;
1629 #address-cells = <1>; 1629 #address-cells = <1>;
1630 #size-cells = <0>; 1630 #size-cells = <0>;
1631 status = "disabled"; 1631 status = "disabled";
1632 1632
1633 pcs13: ethernet-phy@0 1633 pcs13: ethernet-phy@0 {
1634 reg = <0>; 1634 reg = <0>;
1635 }; 1635 };
1636 }; 1636 };
1637 1637
1638 pcs_mdio14: mdio@8c3b000 { 1638 pcs_mdio14: mdio@8c3b000 {
1639 compatible = "fsl,fma 1639 compatible = "fsl,fman-memac-mdio";
1640 reg = <0x0 0x8c3b000 1640 reg = <0x0 0x8c3b000 0x0 0x1000>;
1641 little-endian; 1641 little-endian;
1642 #address-cells = <1>; 1642 #address-cells = <1>;
1643 #size-cells = <0>; 1643 #size-cells = <0>;
1644 status = "disabled"; 1644 status = "disabled";
1645 1645
1646 pcs14: ethernet-phy@0 1646 pcs14: ethernet-phy@0 {
1647 reg = <0>; 1647 reg = <0>;
1648 }; 1648 };
1649 }; 1649 };
1650 1650
1651 pcs_mdio15: mdio@8c3f000 { 1651 pcs_mdio15: mdio@8c3f000 {
1652 compatible = "fsl,fma 1652 compatible = "fsl,fman-memac-mdio";
1653 reg = <0x0 0x8c3f000 1653 reg = <0x0 0x8c3f000 0x0 0x1000>;
1654 little-endian; 1654 little-endian;
1655 #address-cells = <1>; 1655 #address-cells = <1>;
1656 #size-cells = <0>; 1656 #size-cells = <0>;
1657 status = "disabled"; 1657 status = "disabled";
1658 1658
1659 pcs15: ethernet-phy@0 1659 pcs15: ethernet-phy@0 {
1660 reg = <0>; 1660 reg = <0>;
1661 }; 1661 };
1662 }; 1662 };
1663 1663
1664 pcs_mdio16: mdio@8c43000 { 1664 pcs_mdio16: mdio@8c43000 {
1665 compatible = "fsl,fma 1665 compatible = "fsl,fman-memac-mdio";
1666 reg = <0x0 0x8c43000 1666 reg = <0x0 0x8c43000 0x0 0x1000>;
1667 little-endian; 1667 little-endian;
1668 #address-cells = <1>; 1668 #address-cells = <1>;
1669 #size-cells = <0>; 1669 #size-cells = <0>;
1670 status = "disabled"; 1670 status = "disabled";
1671 1671
1672 pcs16: ethernet-phy@0 1672 pcs16: ethernet-phy@0 {
1673 reg = <0>; 1673 reg = <0>;
1674 }; 1674 };
1675 }; 1675 };
1676 1676
1677 pcs_mdio17: mdio@8c47000 { 1677 pcs_mdio17: mdio@8c47000 {
1678 compatible = "fsl,fma 1678 compatible = "fsl,fman-memac-mdio";
1679 reg = <0x0 0x8c47000 1679 reg = <0x0 0x8c47000 0x0 0x1000>;
1680 little-endian; 1680 little-endian;
1681 #address-cells = <1>; 1681 #address-cells = <1>;
1682 #size-cells = <0>; 1682 #size-cells = <0>;
1683 status = "disabled"; 1683 status = "disabled";
1684 1684
1685 pcs17: ethernet-phy@0 1685 pcs17: ethernet-phy@0 {
1686 reg = <0>; 1686 reg = <0>;
1687 }; 1687 };
1688 }; 1688 };
1689 1689
1690 pcs_mdio18: mdio@8c4b000 { 1690 pcs_mdio18: mdio@8c4b000 {
1691 compatible = "fsl,fma 1691 compatible = "fsl,fman-memac-mdio";
1692 reg = <0x0 0x8c4b000 1692 reg = <0x0 0x8c4b000 0x0 0x1000>;
1693 little-endian; 1693 little-endian;
1694 #address-cells = <1>; 1694 #address-cells = <1>;
1695 #size-cells = <0>; 1695 #size-cells = <0>;
1696 status = "disabled"; 1696 status = "disabled";
1697 1697
1698 pcs18: ethernet-phy@0 1698 pcs18: ethernet-phy@0 {
1699 reg = <0>; 1699 reg = <0>;
1700 }; 1700 };
1701 }; 1701 };
1702 1702
1703 pinmux_i2crv: pinmux@70010012 1703 pinmux_i2crv: pinmux@70010012c {
1704 compatible = "pinctrl 1704 compatible = "pinctrl-single";
1705 reg = <0x00000007 0x0 1705 reg = <0x00000007 0x0010012c 0x0 0xc>;
1706 #address-cells = <1>; 1706 #address-cells = <1>;
1707 #size-cells = <0>; 1707 #size-cells = <0>;
1708 pinctrl-single,bit-pe 1708 pinctrl-single,bit-per-mux;
1709 pinctrl-single,regist 1709 pinctrl-single,register-width = <32>;
1710 pinctrl-single,functi 1710 pinctrl-single,function-mask = <0x7>;
1711 1711
1712 i2c1_scl: i2c1-scl-pi 1712 i2c1_scl: i2c1-scl-pins {
1713 pinctrl-singl 1713 pinctrl-single,bits = <0x0 0 0x7>;
1714 }; 1714 };
1715 1715
1716 i2c1_scl_gpio: i2c1-s 1716 i2c1_scl_gpio: i2c1-scl-gpio-pins {
1717 pinctrl-singl 1717 pinctrl-single,bits = <0x0 0x1 0x7>;
1718 }; 1718 };
1719 1719
1720 i2c2_scl: i2c2-scl-pi 1720 i2c2_scl: i2c2-scl-pins {
1721 pinctrl-singl 1721 pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
1722 }; 1722 };
1723 1723
1724 i2c2_scl_gpio: i2c2-s 1724 i2c2_scl_gpio: i2c2-scl-gpio-pins {
1725 pinctrl-singl 1725 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
1726 }; 1726 };
1727 1727
1728 i2c3_scl: i2c3-scl-pi 1728 i2c3_scl: i2c3-scl-pins {
1729 pinctrl-singl 1729 pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
1730 }; 1730 };
1731 1731
1732 i2c3_scl_gpio: i2c3-s 1732 i2c3_scl_gpio: i2c3-scl-gpio-pins {
1733 pinctrl-singl 1733 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
1734 }; 1734 };
1735 1735
1736 i2c4_scl: i2c4-scl-pi 1736 i2c4_scl: i2c4-scl-pins {
1737 pinctrl-singl 1737 pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
1738 }; 1738 };
1739 1739
1740 i2c4_scl_gpio: i2c4-s 1740 i2c4_scl_gpio: i2c4-scl-gpio-pins {
1741 pinctrl-singl 1741 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
1742 }; 1742 };
1743 1743
1744 i2c5_scl: i2c5-scl-pi 1744 i2c5_scl: i2c5-scl-pins {
1745 pinctrl-singl 1745 pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
1746 }; 1746 };
1747 1747
1748 i2c5_scl_gpio: i2c5-s 1748 i2c5_scl_gpio: i2c5-scl-gpio-pins {
1749 pinctrl-singl 1749 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
1750 }; 1750 };
1751 1751
1752 i2c6_scl: i2c6-scl-pi 1752 i2c6_scl: i2c6-scl-pins {
1753 pinctrl-singl 1753 pinctrl-single,bits = <0x4 0x2 0x7>;
1754 }; 1754 };
1755 1755
1756 i2c6_scl_gpio: i2c6-s 1756 i2c6_scl_gpio: i2c6-scl-gpio-pins {
1757 pinctrl-singl 1757 pinctrl-single,bits = <0x4 0x1 0x7>;
1758 }; 1758 };
1759 1759
1760 i2c7_scl: i2c7-scl-pi 1760 i2c7_scl: i2c7-scl-pins {
1761 pinctrl-singl 1761 pinctrl-single,bits = <0x4 0x2 0x7>;
1762 }; 1762 };
1763 1763
1764 i2c7_scl_gpio: i2c7-s 1764 i2c7_scl_gpio: i2c7-scl-gpio-pins {
1765 pinctrl-singl 1765 pinctrl-single,bits = <0x4 0x1 0x7>;
1766 }; 1766 };
1767 1767
1768 i2c0_scl: i2c0-scl-pi 1768 i2c0_scl: i2c0-scl-pins {
1769 pinctrl-singl 1769 pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
1770 }; 1770 };
1771 1771
1772 i2c0_scl_gpio: i2c0-s 1772 i2c0_scl_gpio: i2c0-scl-gpio-pins {
1773 pinctrl-singl 1773 pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
1774 }; 1774 };
1775 }; 1775 };
1776 1776
1777 fsl_mc: fsl-mc@80c000000 { 1777 fsl_mc: fsl-mc@80c000000 {
1778 compatible = "fsl,qor 1778 compatible = "fsl,qoriq-mc";
1779 reg = <0x00000008 0x0 1779 reg = <0x00000008 0x0c000000 0 0x40>,
1780 <0x00000000 0x0 1780 <0x00000000 0x08340000 0 0x40000>;
1781 msi-parent = <&its 0> 1781 msi-parent = <&its 0>;
1782 /* iommu-map property 1782 /* iommu-map property is fixed up by u-boot */
1783 iommu-map = <0 &smmu 1783 iommu-map = <0 &smmu 0 0>;
1784 dma-coherent; 1784 dma-coherent;
1785 #address-cells = <3>; 1785 #address-cells = <3>;
1786 #size-cells = <1>; 1786 #size-cells = <1>;
1787 1787
1788 /* 1788 /*
1789 * Region type 0x0 - 1789 * Region type 0x0 - MC portals
1790 * Region type 0x1 - 1790 * Region type 0x1 - QBMAN portals
1791 */ 1791 */
1792 ranges = <0x0 0x0 0x0 1792 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1793 0x1 0x0 0x0 1793 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1794 1794
1795 /* 1795 /*
1796 * Define the maximum 1796 * Define the maximum number of MACs present on the SoC.
1797 */ 1797 */
1798 dpmacs { 1798 dpmacs {
1799 #address-cell 1799 #address-cells = <1>;
1800 #size-cells = 1800 #size-cells = <0>;
1801 1801
1802 dpmac1: ether 1802 dpmac1: ethernet@1 {
1803 compa 1803 compatible = "fsl,qoriq-mc-dpmac";
1804 reg = 1804 reg = <0x1>;
1805 pcs-h 1805 pcs-handle = <&pcs1>;
1806 }; 1806 };
1807 1807
1808 dpmac2: ether 1808 dpmac2: ethernet@2 {
1809 compa 1809 compatible = "fsl,qoriq-mc-dpmac";
1810 reg = 1810 reg = <0x2>;
1811 pcs-h 1811 pcs-handle = <&pcs2>;
1812 }; 1812 };
1813 1813
1814 dpmac3: ether 1814 dpmac3: ethernet@3 {
1815 compa 1815 compatible = "fsl,qoriq-mc-dpmac";
1816 reg = 1816 reg = <0x3>;
1817 pcs-h 1817 pcs-handle = <&pcs3>;
1818 }; 1818 };
1819 1819
1820 dpmac4: ether 1820 dpmac4: ethernet@4 {
1821 compa 1821 compatible = "fsl,qoriq-mc-dpmac";
1822 reg = 1822 reg = <0x4>;
1823 pcs-h 1823 pcs-handle = <&pcs4>;
1824 }; 1824 };
1825 1825
1826 dpmac5: ether 1826 dpmac5: ethernet@5 {
1827 compa 1827 compatible = "fsl,qoriq-mc-dpmac";
1828 reg = 1828 reg = <0x5>;
1829 pcs-h 1829 pcs-handle = <&pcs5>;
1830 }; 1830 };
1831 1831
1832 dpmac6: ether 1832 dpmac6: ethernet@6 {
1833 compa 1833 compatible = "fsl,qoriq-mc-dpmac";
1834 reg = 1834 reg = <0x6>;
1835 pcs-h 1835 pcs-handle = <&pcs6>;
1836 }; 1836 };
1837 1837
1838 dpmac7: ether 1838 dpmac7: ethernet@7 {
1839 compa 1839 compatible = "fsl,qoriq-mc-dpmac";
1840 reg = 1840 reg = <0x7>;
1841 pcs-h 1841 pcs-handle = <&pcs7>;
1842 }; 1842 };
1843 1843
1844 dpmac8: ether 1844 dpmac8: ethernet@8 {
1845 compa 1845 compatible = "fsl,qoriq-mc-dpmac";
1846 reg = 1846 reg = <0x8>;
1847 pcs-h 1847 pcs-handle = <&pcs8>;
1848 }; 1848 };
1849 1849
1850 dpmac9: ether 1850 dpmac9: ethernet@9 {
1851 compa 1851 compatible = "fsl,qoriq-mc-dpmac";
1852 reg = 1852 reg = <0x9>;
1853 pcs-h 1853 pcs-handle = <&pcs9>;
1854 }; 1854 };
1855 1855
1856 dpmac10: ethe 1856 dpmac10: ethernet@a {
1857 compa 1857 compatible = "fsl,qoriq-mc-dpmac";
1858 reg = 1858 reg = <0xa>;
1859 pcs-h 1859 pcs-handle = <&pcs10>;
1860 }; 1860 };
1861 1861
1862 dpmac11: ethe 1862 dpmac11: ethernet@b {
1863 compa 1863 compatible = "fsl,qoriq-mc-dpmac";
1864 reg = 1864 reg = <0xb>;
1865 pcs-h 1865 pcs-handle = <&pcs11>;
1866 }; 1866 };
1867 1867
1868 dpmac12: ethe 1868 dpmac12: ethernet@c {
1869 compa 1869 compatible = "fsl,qoriq-mc-dpmac";
1870 reg = 1870 reg = <0xc>;
1871 pcs-h 1871 pcs-handle = <&pcs12>;
1872 }; 1872 };
1873 1873
1874 dpmac13: ethe 1874 dpmac13: ethernet@d {
1875 compa 1875 compatible = "fsl,qoriq-mc-dpmac";
1876 reg = 1876 reg = <0xd>;
1877 pcs-h 1877 pcs-handle = <&pcs13>;
1878 }; 1878 };
1879 1879
1880 dpmac14: ethe 1880 dpmac14: ethernet@e {
1881 compa 1881 compatible = "fsl,qoriq-mc-dpmac";
1882 reg = 1882 reg = <0xe>;
1883 pcs-h 1883 pcs-handle = <&pcs14>;
1884 }; 1884 };
1885 1885
1886 dpmac15: ethe 1886 dpmac15: ethernet@f {
1887 compa 1887 compatible = "fsl,qoriq-mc-dpmac";
1888 reg = 1888 reg = <0xf>;
1889 pcs-h 1889 pcs-handle = <&pcs15>;
1890 }; 1890 };
1891 1891
1892 dpmac16: ethe 1892 dpmac16: ethernet@10 {
1893 compa 1893 compatible = "fsl,qoriq-mc-dpmac";
1894 reg = 1894 reg = <0x10>;
1895 pcs-h 1895 pcs-handle = <&pcs16>;
1896 }; 1896 };
1897 1897
1898 dpmac17: ethe 1898 dpmac17: ethernet@11 {
1899 compa 1899 compatible = "fsl,qoriq-mc-dpmac";
1900 reg = 1900 reg = <0x11>;
1901 pcs-h 1901 pcs-handle = <&pcs17>;
1902 }; 1902 };
1903 1903
1904 dpmac18: ethe 1904 dpmac18: ethernet@12 {
1905 compa 1905 compatible = "fsl,qoriq-mc-dpmac";
1906 reg = 1906 reg = <0x12>;
1907 pcs-h 1907 pcs-handle = <&pcs18>;
1908 }; 1908 };
1909 }; 1909 };
1910 }; 1910 };
1911 }; 1911 };
1912 1912
1913 firmware { 1913 firmware {
1914 optee: optee { 1914 optee: optee {
1915 compatible = "linaro, 1915 compatible = "linaro,optee-tz";
1916 method = "smc"; 1916 method = "smc";
1917 status = "disabled"; 1917 status = "disabled";
1918 }; 1918 };
1919 }; 1919 };
1920 }; 1920 };
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