1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 // 2 //
3 // Device Tree file for LX2162AQDS 3 // Device Tree file for LX2162AQDS
4 // 4 //
5 // Copyright 2020 NXP 5 // Copyright 2020 NXP
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "fsl-lx2160a.dtsi" 9 #include "fsl-lx2160a.dtsi"
10 10
11 / { 11 / {
12 model = "NXP Layerscape LX2162AQDS"; 12 model = "NXP Layerscape LX2162AQDS";
13 compatible = "fsl,lx2162a-qds", "fsl,l 13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
14 14
15 aliases { 15 aliases {
16 crypto = &crypto; 16 crypto = &crypto;
17 mmc0 = &esdhc0; <<
18 mmc1 = &esdhc1; <<
19 serial0 = &uart0; 17 serial0 = &uart0;
20 }; 18 };
21 19
22 chosen { 20 chosen {
23 stdout-path = "serial0:115200n 21 stdout-path = "serial0:115200n8";
24 }; 22 };
25 23
26 sb_3v3: regulator-sb3v3 { 24 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed" 25 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3V 26 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <330 27 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <330 28 regulator-max-microvolt = <3300000>;
31 }; 29 };
32 30
33 mdio-mux-1 { 31 mdio-mux-1 {
34 compatible = "mdio-mux-multipl 32 compatible = "mdio-mux-multiplexer";
35 mux-controls = <&mux 0>; 33 mux-controls = <&mux 0>;
36 mdio-parent-bus = <&emdio1>; 34 mdio-parent-bus = <&emdio1>;
37 #address-cells = <1>; !! 35 #address-cells=<1>;
38 #size-cells = <0>; 36 #size-cells = <0>;
39 37
40 mdio@0 { /* On-board RTL8211F 38 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
41 reg = <0x00>; 39 reg = <0x00>;
42 #address-cells = <1>; 40 #address-cells = <1>;
43 #size-cells = <0>; 41 #size-cells = <0>;
44 42
45 rgmii_phy1: ethernet-p 43 rgmii_phy1: ethernet-phy@1 {
46 compatible = " 44 compatible = "ethernet-phy-id001c.c916";
47 reg = <0x1>; 45 reg = <0x1>;
48 eee-broken-100 46 eee-broken-1000t;
49 }; 47 };
50 }; 48 };
51 49
52 mdio@8 { /* On-board RTL8211F 50 mdio@8 { /* On-board RTL8211F PHY #2 RGMII2 */
53 reg = <0x8>; 51 reg = <0x8>;
54 #address-cells = <1>; 52 #address-cells = <1>;
55 #size-cells = <0>; 53 #size-cells = <0>;
56 54
57 rgmii_phy2: ethernet-p 55 rgmii_phy2: ethernet-phy@2 {
58 compatible = " 56 compatible = "ethernet-phy-id001c.c916";
59 reg = <0x2>; 57 reg = <0x2>;
60 eee-broken-100 58 eee-broken-1000t;
61 }; 59 };
62 }; 60 };
63 61
64 mdio@18 { /* Slot #1 */ 62 mdio@18 { /* Slot #1 */
65 reg = <0x18>; 63 reg = <0x18>;
66 #address-cells = <1>; 64 #address-cells = <1>;
67 #size-cells = <0>; 65 #size-cells = <0>;
68 }; 66 };
69 67
70 mdio@19 { /* Slot #2 */ 68 mdio@19 { /* Slot #2 */
71 reg = <0x19>; 69 reg = <0x19>;
72 #address-cells = <1>; 70 #address-cells = <1>;
73 #size-cells = <0>; 71 #size-cells = <0>;
74 }; 72 };
75 73
76 mdio@1a { /* Slot #3 */ 74 mdio@1a { /* Slot #3 */
77 reg = <0x1a>; 75 reg = <0x1a>;
78 #address-cells = <1>; 76 #address-cells = <1>;
79 #size-cells = <0>; 77 #size-cells = <0>;
80 }; 78 };
81 79
82 mdio@1b { /* Slot #4 */ 80 mdio@1b { /* Slot #4 */
83 reg = <0x1b>; 81 reg = <0x1b>;
84 #address-cells = <1>; 82 #address-cells = <1>;
85 #size-cells = <0>; 83 #size-cells = <0>;
86 }; 84 };
87 85
88 mdio@1c { /* Slot #5 */ 86 mdio@1c { /* Slot #5 */
89 reg = <0x1c>; 87 reg = <0x1c>;
90 #address-cells = <1>; 88 #address-cells = <1>;
91 #size-cells = <0>; 89 #size-cells = <0>;
92 }; 90 };
93 91
94 mdio@1d { /* Slot #6 */ 92 mdio@1d { /* Slot #6 */
95 reg = <0x1d>; 93 reg = <0x1d>;
96 #address-cells = <1>; 94 #address-cells = <1>;
97 #size-cells = <0>; 95 #size-cells = <0>;
98 }; 96 };
99 97
100 mdio@1e { /* Slot #7 */ 98 mdio@1e { /* Slot #7 */
101 reg = <0x1e>; 99 reg = <0x1e>;
102 #address-cells = <1>; 100 #address-cells = <1>;
103 #size-cells = <0>; 101 #size-cells = <0>;
104 }; 102 };
105 103
106 mdio@1f { /* Slot #8 */ 104 mdio@1f { /* Slot #8 */
107 reg = <0x1f>; 105 reg = <0x1f>;
108 #address-cells = <1>; 106 #address-cells = <1>;
109 #size-cells = <0>; 107 #size-cells = <0>;
110 }; 108 };
111 }; 109 };
112 110
113 mdio-mux-2 { 111 mdio-mux-2 {
114 compatible = "mdio-mux-multipl 112 compatible = "mdio-mux-multiplexer";
115 mux-controls = <&mux 1>; 113 mux-controls = <&mux 1>;
116 mdio-parent-bus = <&emdio2>; 114 mdio-parent-bus = <&emdio2>;
117 #address-cells = <1>; !! 115 #address-cells=<1>;
118 #size-cells = <0>; 116 #size-cells = <0>;
119 117
120 mdio@0 { /* Slot #1 (secondary 118 mdio@0 { /* Slot #1 (secondary EMI) */
121 reg = <0x00>; 119 reg = <0x00>;
122 #address-cells = <1>; 120 #address-cells = <1>;
123 #size-cells = <0>; 121 #size-cells = <0>;
124 }; 122 };
125 123
126 mdio@1 { /* Slot #2 (secondary 124 mdio@1 { /* Slot #2 (secondary EMI) */
127 reg = <0x01>; 125 reg = <0x01>;
128 #address-cells = <1>; 126 #address-cells = <1>;
129 #size-cells = <0>; 127 #size-cells = <0>;
130 }; 128 };
131 129
132 mdio@2 { /* Slot #3 (secondary 130 mdio@2 { /* Slot #3 (secondary EMI) */
133 reg = <0x02>; 131 reg = <0x02>;
134 #address-cells = <1>; 132 #address-cells = <1>;
135 #size-cells = <0>; 133 #size-cells = <0>;
136 }; 134 };
137 135
138 mdio@3 { /* Slot #4 (secondary 136 mdio@3 { /* Slot #4 (secondary EMI) */
139 reg = <0x03>; 137 reg = <0x03>;
140 #address-cells = <1>; 138 #address-cells = <1>;
141 #size-cells = <0>; 139 #size-cells = <0>;
142 }; 140 };
143 141
144 mdio@4 { /* Slot #5 (secondary 142 mdio@4 { /* Slot #5 (secondary EMI) */
145 reg = <0x04>; 143 reg = <0x04>;
146 #address-cells = <1>; 144 #address-cells = <1>;
147 #size-cells = <0>; 145 #size-cells = <0>;
148 }; 146 };
149 147
150 mdio@5 { /* Slot #6 (secondary 148 mdio@5 { /* Slot #6 (secondary EMI) */
151 reg = <0x05>; 149 reg = <0x05>;
152 #address-cells = <1>; 150 #address-cells = <1>;
153 #size-cells = <0>; 151 #size-cells = <0>;
154 }; 152 };
155 153
156 mdio@6 { /* Slot #7 (secondary 154 mdio@6 { /* Slot #7 (secondary EMI) */
157 reg = <0x06>; 155 reg = <0x06>;
158 #address-cells = <1>; 156 #address-cells = <1>;
159 #size-cells = <0>; 157 #size-cells = <0>;
160 }; 158 };
161 159
162 mdio@7 { /* Slot #8 (secondary 160 mdio@7 { /* Slot #8 (secondary EMI) */
163 reg = <0x07>; 161 reg = <0x07>;
164 #address-cells = <1>; 162 #address-cells = <1>;
165 #size-cells = <0>; 163 #size-cells = <0>;
166 }; 164 };
167 }; 165 };
168 }; 166 };
169 167
170 &can0 { <<
171 status = "okay"; <<
172 }; <<
173 <<
174 &can1 { <<
175 status = "okay"; <<
176 }; <<
177 <<
178 &crypto { 168 &crypto {
179 status = "okay"; 169 status = "okay";
180 }; 170 };
181 171
182 &dpmac17 { 172 &dpmac17 {
183 phy-handle = <&rgmii_phy1>; 173 phy-handle = <&rgmii_phy1>;
184 phy-connection-type = "rgmii-id"; 174 phy-connection-type = "rgmii-id";
185 }; 175 };
186 176
187 &dpmac18 { 177 &dpmac18 {
188 phy-handle = <&rgmii_phy2>; 178 phy-handle = <&rgmii_phy2>;
189 phy-connection-type = "rgmii-id"; 179 phy-connection-type = "rgmii-id";
190 }; 180 };
191 181
192 &dspi0 { 182 &dspi0 {
193 status = "okay"; 183 status = "okay";
194 184
195 dflash0: flash@0 { 185 dflash0: flash@0 {
196 #address-cells = <1>; 186 #address-cells = <1>;
197 #size-cells = <1>; 187 #size-cells = <1>;
198 compatible = "jedec,spi-nor"; 188 compatible = "jedec,spi-nor";
199 reg = <0>; 189 reg = <0>;
200 spi-max-frequency = <1000000>; 190 spi-max-frequency = <1000000>;
201 }; 191 };
202 }; 192 };
203 193
204 &dspi1 { 194 &dspi1 {
205 status = "okay"; 195 status = "okay";
206 196
207 dflash1: flash@0 { 197 dflash1: flash@0 {
208 #address-cells = <1>; 198 #address-cells = <1>;
209 #size-cells = <1>; 199 #size-cells = <1>;
210 compatible = "jedec,spi-nor"; 200 compatible = "jedec,spi-nor";
211 reg = <0>; 201 reg = <0>;
212 spi-max-frequency = <1000000>; 202 spi-max-frequency = <1000000>;
213 }; 203 };
214 }; 204 };
215 205
216 &dspi2 { 206 &dspi2 {
217 status = "okay"; 207 status = "okay";
218 208
219 dflash2: flash@0 { 209 dflash2: flash@0 {
220 #address-cells = <1>; 210 #address-cells = <1>;
221 #size-cells = <1>; 211 #size-cells = <1>;
222 compatible = "jedec,spi-nor"; 212 compatible = "jedec,spi-nor";
223 reg = <0>; 213 reg = <0>;
224 spi-max-frequency = <1000000>; 214 spi-max-frequency = <1000000>;
225 }; 215 };
226 }; 216 };
227 217
228 &emdio1 { 218 &emdio1 {
229 status = "okay"; 219 status = "okay";
230 }; 220 };
231 221
232 &emdio2 { 222 &emdio2 {
233 status = "okay"; 223 status = "okay";
234 }; 224 };
235 225
236 &esdhc0 { 226 &esdhc0 {
237 sd-uhs-sdr104; <<
238 sd-uhs-sdr50; <<
239 sd-uhs-sdr25; <<
240 sd-uhs-sdr12; <<
241 status = "okay"; 227 status = "okay";
242 }; 228 };
243 229
244 &esdhc1 { 230 &esdhc1 {
245 mmc-hs200-1_8v; <<
246 mmc-hs400-1_8v; <<
247 bus-width = <8>; <<
248 status = "okay"; 231 status = "okay";
249 }; 232 };
250 233
251 &fspi { 234 &fspi {
252 status = "okay"; 235 status = "okay";
253 236
254 mt35xu512aba0: flash@0 { 237 mt35xu512aba0: flash@0 {
255 #address-cells = <1>; 238 #address-cells = <1>;
256 #size-cells = <1>; 239 #size-cells = <1>;
257 compatible = "jedec,spi-nor"; 240 compatible = "jedec,spi-nor";
258 m25p,fast-read; 241 m25p,fast-read;
259 spi-max-frequency = <50000000> 242 spi-max-frequency = <50000000>;
260 reg = <0>; 243 reg = <0>;
261 spi-rx-bus-width = <8>; 244 spi-rx-bus-width = <8>;
262 spi-tx-bus-width = <8>; 245 spi-tx-bus-width = <8>;
263 }; 246 };
264 }; 247 };
265 248
266 &i2c0 { 249 &i2c0 {
267 status = "okay"; 250 status = "okay";
268 251
269 fpga@66 { 252 fpga@66 {
270 compatible = "fsl,lx2160aqds-f 253 compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
271 "simple-mfd"; 254 "simple-mfd";
272 reg = <0x66>; 255 reg = <0x66>;
273 256
274 mux: mux-controller { 257 mux: mux-controller {
275 compatible = "reg-mux" 258 compatible = "reg-mux";
276 #mux-control-cells = < 259 #mux-control-cells = <1>;
277 mux-reg-masks = <0x54 260 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
278 <0x54 261 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
279 }; 262 };
280 }; 263 };
281 264
282 i2c-mux@77 { 265 i2c-mux@77 {
283 compatible = "nxp,pca9547"; 266 compatible = "nxp,pca9547";
284 reg = <0x77>; 267 reg = <0x77>;
285 #address-cells = <1>; 268 #address-cells = <1>;
286 #size-cells = <0>; 269 #size-cells = <0>;
287 270
288 i2c@2 { 271 i2c@2 {
289 #address-cells = <1>; 272 #address-cells = <1>;
290 #size-cells = <0>; 273 #size-cells = <0>;
291 reg = <0x2>; 274 reg = <0x2>;
292 275
293 power-monitor@40 { 276 power-monitor@40 {
294 compatible = " 277 compatible = "ti,ina220";
295 reg = <0x40>; 278 reg = <0x40>;
296 shunt-resistor 279 shunt-resistor = <500>;
297 }; 280 };
298 281
299 power-monitor@41 { 282 power-monitor@41 {
300 compatible = " 283 compatible = "ti,ina220";
301 reg = <0x41>; 284 reg = <0x41>;
302 shunt-resistor 285 shunt-resistor = <1000>;
303 }; 286 };
304 }; 287 };
305 288
306 i2c@3 { 289 i2c@3 {
307 #address-cells = <1>; 290 #address-cells = <1>;
308 #size-cells = <0>; 291 #size-cells = <0>;
309 reg = <0x3>; 292 reg = <0x3>;
310 293
311 temperature-sensor@4c 294 temperature-sensor@4c {
312 compatible = " 295 compatible = "nxp,sa56004";
313 reg = <0x4c>; 296 reg = <0x4c>;
314 vcc-supply = < 297 vcc-supply = <&sb_3v3>;
315 }; 298 };
316 299
317 rtc@51 { 300 rtc@51 {
318 compatible = " 301 compatible = "nxp,pcf2129";
319 reg = <0x51>; 302 reg = <0x51>;
320 /* IRQ_RTC_B - <<
321 interrupts-ext <<
322 }; 303 };
323 }; 304 };
324 }; 305 };
325 }; <<
326 <<
327 &optee { <<
328 status = "okay"; <<
329 }; 306 };
330 307
331 &sata0 { 308 &sata0 {
332 status = "okay"; 309 status = "okay";
333 }; 310 };
334 311
335 &sata1 { 312 &sata1 {
336 status = "okay"; 313 status = "okay";
337 }; 314 };
338 315
339 &sata2 { 316 &sata2 {
340 status = "okay"; 317 status = "okay";
341 }; 318 };
342 319
343 &sata3 { 320 &sata3 {
344 status = "okay"; 321 status = "okay";
345 }; 322 };
346 323
347 &uart0 { 324 &uart0 {
348 status = "okay"; 325 status = "okay";
349 }; 326 };
350 327
351 &uart1 { 328 &uart1 {
352 status = "okay"; 329 status = "okay";
353 }; 330 };
354 331
355 &usb0 { 332 &usb0 {
356 status = "okay"; 333 status = "okay";
357 }; 334 };
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