1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/pwm/pwm.h> 6 #include <dt-bindings/pwm/pwm.h>
7 7
8 / { 8 / {
9 chosen { 9 chosen {
10 stdout-path = &lpuart1; 10 stdout-path = &lpuart1;
11 }; 11 };
12 12
13 /* Apalis BKL1 */ 13 /* Apalis BKL1 */
14 backlight: backlight { 14 backlight: backlight {
15 compatible = "pwm-backlight"; 15 compatible = "pwm-backlight";
16 pinctrl-names = "default"; 16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_bkl 17 pinctrl-0 = <&pinctrl_gpio_bkl_on>;
18 brightness-levels = <0 45 63 8 18 brightness-levels = <0 45 63 88 119 158 203 255>;
19 default-brightness-level = <4> 19 default-brightness-level = <4>;
20 enable-gpios = <&lsio_gpio1 4 20 enable-gpios = <&lsio_gpio1 4 GPIO_ACTIVE_HIGH>; /* Apalis BKL1_ON */
21 /* TODO: hook-up to Apalis BKL 21 /* TODO: hook-up to Apalis BKL1_PWM */
22 status = "disabled"; 22 status = "disabled";
23 }; 23 };
24 24
25 gpio_fan: gpio-fan { 25 gpio_fan: gpio-fan {
26 compatible = "gpio-fan"; 26 compatible = "gpio-fan";
27 pinctrl-names = "default"; 27 pinctrl-names = "default";
28 pinctrl-0 = <&pinctrl_gpio8>; 28 pinctrl-0 = <&pinctrl_gpio8>;
29 gpios = <&lsio_gpio3 28 GPIO_A 29 gpios = <&lsio_gpio3 28 GPIO_ACTIVE_HIGH>;
30 gpio-fan,speed-map = < 0 0 30 gpio-fan,speed-map = < 0 0
31 3000 1>; 31 3000 1>;
32 }; 32 };
33 33
34 /* TODO: LVDS Panel */ 34 /* TODO: LVDS Panel */
35 35
36 /* TODO: Shared PCIe/SATA Reference Cl 36 /* TODO: Shared PCIe/SATA Reference Clock */
37 37
38 /* TODO: PCIe Wi-Fi Reference Clock */ 38 /* TODO: PCIe Wi-Fi Reference Clock */
39 39
40 /* 40 /*
41 * Power management bus used to contro 41 * Power management bus used to control LDO1OUT of the
42 * second PMIC PF8100. This is used fo 42 * second PMIC PF8100. This is used for controlling voltage levels of
43 * typespecific RGMII signals and Apal 43 * typespecific RGMII signals and Apalis UART2_RTS UART2_CTS.
44 * 44 *
45 * IMX_SC_R_BOARD_R1 for 3.3V 45 * IMX_SC_R_BOARD_R1 for 3.3V
46 * IMX_SC_R_BOARD_R2 for 1.8V 46 * IMX_SC_R_BOARD_R2 for 1.8V
47 * IMX_SC_R_BOARD_R3 for 2.5V 47 * IMX_SC_R_BOARD_R3 for 2.5V
48 * Note that for 2.5V operation the pa 48 * Note that for 2.5V operation the pad muxing needs to be changed,
49 * compare with PSW_OVR field of IMX8Q 49 * compare with PSW_OVR field of IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD.
50 * 50 *
51 * those power domains are mutually ex 51 * those power domains are mutually exclusive.
52 */ 52 */
53 reg_ext_rgmii: regulator-ext-rgmii { 53 reg_ext_rgmii: regulator-ext-rgmii {
54 compatible = "regulator-fixed" 54 compatible = "regulator-fixed";
55 power-domains = <&pd IMX_SC_R_ 55 power-domains = <&pd IMX_SC_R_BOARD_R1>;
56 regulator-max-microvolt = <330 56 regulator-max-microvolt = <3300000>;
57 regulator-min-microvolt = <330 57 regulator-min-microvolt = <3300000>;
58 regulator-name = "VDD_EXT_RGMI 58 regulator-name = "VDD_EXT_RGMII (LDO1)";
59 59
60 regulator-state-mem { 60 regulator-state-mem {
61 regulator-off-in-suspe 61 regulator-off-in-suspend;
62 }; 62 };
63 }; 63 };
64 64
65 reg_module_3v3: regulator-module-3v3 { 65 reg_module_3v3: regulator-module-3v3 {
66 compatible = "regulator-fixed" 66 compatible = "regulator-fixed";
67 regulator-max-microvolt = <330 67 regulator-max-microvolt = <3300000>;
68 regulator-min-microvolt = <330 68 regulator-min-microvolt = <3300000>;
69 regulator-name = "+V3.3"; 69 regulator-name = "+V3.3";
70 }; 70 };
71 71
72 reg_module_3v3_avdd: regulator-module- 72 reg_module_3v3_avdd: regulator-module-3v3-avdd {
73 compatible = "regulator-fixed" 73 compatible = "regulator-fixed";
74 regulator-max-microvolt = <330 74 regulator-max-microvolt = <3300000>;
75 regulator-min-microvolt = <330 75 regulator-min-microvolt = <3300000>;
76 regulator-name = "+V3.3_AUDIO" 76 regulator-name = "+V3.3_AUDIO";
77 }; 77 };
78 78
79 reg_module_wifi: regulator-module-wifi 79 reg_module_wifi: regulator-module-wifi {
80 compatible = "regulator-fixed" 80 compatible = "regulator-fixed";
81 pinctrl-names = "default"; 81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_wifi_pdn 82 pinctrl-0 = <&pinctrl_wifi_pdn>;
83 gpio = <&lsio_gpio1 28 GPIO_AC 83 gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>;
84 enable-active-high; 84 enable-active-high;
85 regulator-always-on; <<
86 regulator-name = "wifi_pwrdn_f 85 regulator-name = "wifi_pwrdn_fake_regulator";
87 regulator-settling-time-us = < 86 regulator-settling-time-us = <100>;
>> 87
>> 88 regulator-state-mem {
>> 89 regulator-off-in-suspend;
>> 90 };
88 }; 91 };
89 92
90 reg_pcie_switch: regulator-pcie-switch 93 reg_pcie_switch: regulator-pcie-switch {
91 compatible = "regulator-fixed" 94 compatible = "regulator-fixed";
92 pinctrl-names = "default"; 95 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio7>; 96 pinctrl-0 = <&pinctrl_gpio7>;
94 gpio = <&lsio_gpio3 26 GPIO_AC 97 gpio = <&lsio_gpio3 26 GPIO_ACTIVE_HIGH>;
95 enable-active-high; 98 enable-active-high;
96 regulator-max-microvolt = <180 99 regulator-max-microvolt = <1800000>;
97 regulator-min-microvolt = <180 100 regulator-min-microvolt = <1800000>;
98 regulator-name = "pcie_switch" 101 regulator-name = "pcie_switch";
99 startup-delay-us = <100000>; 102 startup-delay-us = <100000>;
100 }; 103 };
101 104
102 reg_usb_host_vbus: regulator-usb-host- 105 reg_usb_host_vbus: regulator-usb-host-vbus {
103 compatible = "regulator-fixed" 106 compatible = "regulator-fixed";
104 pinctrl-names = "default"; 107 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_usbh_en> 108 pinctrl-0 = <&pinctrl_usbh_en>;
106 /* Apalis USBH_EN */ 109 /* Apalis USBH_EN */
107 gpio = <&lsio_gpio4 4 GPIO_ACT 110 gpio = <&lsio_gpio4 4 GPIO_ACTIVE_HIGH>;
108 enable-active-high; 111 enable-active-high;
109 regulator-always-on; 112 regulator-always-on;
110 regulator-max-microvolt = <500 113 regulator-max-microvolt = <5000000>;
111 regulator-min-microvolt = <500 114 regulator-min-microvolt = <5000000>;
112 regulator-name = "usb-host-vbu 115 regulator-name = "usb-host-vbus";
113 }; 116 };
114 117
115 reg_usb_hsic: regulator-usb-hsic { 118 reg_usb_hsic: regulator-usb-hsic {
116 compatible = "regulator-fixed" 119 compatible = "regulator-fixed";
117 regulator-max-microvolt = <300 120 regulator-max-microvolt = <3000000>;
118 regulator-min-microvolt = <300 121 regulator-min-microvolt = <3000000>;
119 regulator-name = "usb-hsic-dum 122 regulator-name = "usb-hsic-dummy";
120 }; 123 };
121 124
122 reg_usb_phy: regulator-usb-hsic1 { 125 reg_usb_phy: regulator-usb-hsic1 {
123 compatible = "regulator-fixed" 126 compatible = "regulator-fixed";
124 regulator-max-microvolt = <300 127 regulator-max-microvolt = <3000000>;
125 regulator-min-microvolt = <300 128 regulator-min-microvolt = <3000000>;
126 regulator-name = "usb-phy-dumm 129 regulator-name = "usb-phy-dummy";
127 }; 130 };
128 131
129 reserved-memory { 132 reserved-memory {
130 #address-cells = <2>; 133 #address-cells = <2>;
131 #size-cells = <2>; 134 #size-cells = <2>;
132 ranges; 135 ranges;
133 136
134 decoder_boot: decoder-boot@840 137 decoder_boot: decoder-boot@84000000 {
135 reg = <0 0x84000000 0 138 reg = <0 0x84000000 0 0x2000000>;
136 no-map; 139 no-map;
137 }; 140 };
138 141
139 encoder1_boot: encoder1-boot@8 142 encoder1_boot: encoder1-boot@86000000 {
140 reg = <0 0x86000000 0 143 reg = <0 0x86000000 0 0x200000>;
141 no-map; 144 no-map;
142 }; 145 };
143 146
144 encoder2_boot: encoder2-boot@8 147 encoder2_boot: encoder2-boot@86200000 {
145 reg = <0 0x86200000 0 148 reg = <0 0x86200000 0 0x200000>;
146 no-map; 149 no-map;
147 }; 150 };
148 151
149 /* 152 /*
150 * reserved-memory layout 153 * reserved-memory layout
151 * 0x8800_0000 ~ 0x8FFF_FFFF i 154 * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4
152 * Shouldn't be used at A core 155 * Shouldn't be used at A core and Linux side.
153 * 156 *
154 */ 157 */
155 m4_reserved: m4@88000000 { 158 m4_reserved: m4@88000000 {
156 reg = <0 0x88000000 0 159 reg = <0 0x88000000 0 0x8000000>;
157 no-map; 160 no-map;
158 }; 161 };
159 162
160 rpmsg_reserved: rpmsg@90200000 163 rpmsg_reserved: rpmsg@90200000 {
161 reg = <0 0x90200000 0 164 reg = <0 0x90200000 0 0x200000>;
162 no-map; 165 no-map;
163 }; 166 };
164 167
165 vdevbuffer: vdevbuffer@9040000 168 vdevbuffer: vdevbuffer@90400000 {
166 compatible = "shared-d 169 compatible = "shared-dma-pool";
167 reg = <0 0x90400000 0 170 reg = <0 0x90400000 0 0x100000>;
168 no-map; 171 no-map;
169 }; 172 };
170 173
171 decoder_rpc: decoder-rpc@92000 174 decoder_rpc: decoder-rpc@92000000 {
172 reg = <0 0x92000000 0 175 reg = <0 0x92000000 0 0x200000>;
173 no-map; 176 no-map;
174 }; 177 };
175 178
176 dsp_reserved: dsp@92400000 { 179 dsp_reserved: dsp@92400000 {
177 reg = <0 0x92400000 0 180 reg = <0 0x92400000 0 0x2000000>;
178 no-map; 181 no-map;
179 }; 182 };
180 183
181 encoder1_rpc: encoder1-rpc@944 184 encoder1_rpc: encoder1-rpc@94400000 {
182 reg = <0 0x94400000 0 185 reg = <0 0x94400000 0 0x700000>;
183 no-map; 186 no-map;
184 }; 187 };
185 188
186 encoder2_rpc: encoder2-rpc@94b 189 encoder2_rpc: encoder2-rpc@94b00000 {
187 reg = <0 0x94b00000 0 190 reg = <0 0x94b00000 0 0x700000>;
188 no-map; 191 no-map;
189 }; 192 };
190 193
191 /* global autoconfigured regio 194 /* global autoconfigured region for contiguous allocations */
192 linux,cma { 195 linux,cma {
193 compatible = "shared-d 196 compatible = "shared-dma-pool";
194 alloc-ranges = <0 0xc0 197 alloc-ranges = <0 0xc0000000 0 0x3c000000>;
195 linux,cma-default; 198 linux,cma-default;
196 reusable; 199 reusable;
197 size = <0 0x3c000000>; 200 size = <0 0x3c000000>;
198 }; 201 };
199 }; 202 };
200 203
201 /* TODO: Apalis Analogue Audio */ 204 /* TODO: Apalis Analogue Audio */
202 205
203 /* TODO: HDMI Audio */ 206 /* TODO: HDMI Audio */
204 207
205 /* TODO: Apalis SPDIF1 */ 208 /* TODO: Apalis SPDIF1 */
206 209
207 touchscreen: touchscreen { 210 touchscreen: touchscreen {
208 compatible = "toradex,vf50-tou 211 compatible = "toradex,vf50-touchscreen";
209 interrupt-parent = <&lsio_gpio 212 interrupt-parent = <&lsio_gpio3>;
210 interrupts = <22 IRQ_TYPE_LEVE 213 interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
211 pinctrl-names = "idle", "defau 214 pinctrl-names = "idle", "default";
212 pinctrl-0 = <&pinctrl_touchctr 215 pinctrl-0 = <&pinctrl_touchctrl_idle>, <&pinctrl_touchctrl_gpios>;
213 pinctrl-1 = <&pinctrl_adc1>, < 216 pinctrl-1 = <&pinctrl_adc1>, <&pinctrl_touchctrl_gpios>;
214 io-channels = <&adc1 2>, <&adc 217 io-channels = <&adc1 2>, <&adc1 1>,
215 <&adc1 0>, <&adc 218 <&adc1 0>, <&adc1 3>;
216 vf50-ts-min-pressure = <200>; 219 vf50-ts-min-pressure = <200>;
217 xp-gpios = <&lsio_gpio2 4 GPIO 220 xp-gpios = <&lsio_gpio2 4 GPIO_ACTIVE_LOW>;
218 xm-gpios = <&lsio_gpio2 5 GPIO 221 xm-gpios = <&lsio_gpio2 5 GPIO_ACTIVE_HIGH>;
219 yp-gpios = <&lsio_gpio2 17 GPI 222 yp-gpios = <&lsio_gpio2 17 GPIO_ACTIVE_LOW>;
220 ym-gpios = <&lsio_gpio2 21 GPI 223 ym-gpios = <&lsio_gpio2 21 GPIO_ACTIVE_HIGH>;
221 /* 224 /*
222 * NOTE: you must remove the p 225 * NOTE: you must remove the pinctrl-adc1 from the adc1
223 * node below to use the touch 226 * node below to use the touchscreen
224 */ 227 */
225 status = "disabled"; 228 status = "disabled";
226 }; 229 };
227 230
228 }; 231 };
229 232
230 &adc0 { 233 &adc0 {
231 pinctrl-names = "default"; 234 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_adc0>; 235 pinctrl-0 = <&pinctrl_adc0>;
233 }; 236 };
234 237
235 &adc1 { 238 &adc1 {
236 pinctrl-names = "default"; 239 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_adc1>; 240 pinctrl-0 = <&pinctrl_adc1>;
238 }; 241 };
239 242
240 /* TODO: Asynchronous Sample Rate Converter (A 243 /* TODO: Asynchronous Sample Rate Converter (ASRC) */
241 244
242 /* Apalis ETH1 */ 245 /* Apalis ETH1 */
243 &fec1 { 246 &fec1 {
244 pinctrl-names = "default", "sleep"; 247 pinctrl-names = "default", "sleep";
245 pinctrl-0 = <&pinctrl_fec1>; 248 pinctrl-0 = <&pinctrl_fec1>;
246 pinctrl-1 = <&pinctrl_fec1_sleep>; 249 pinctrl-1 = <&pinctrl_fec1_sleep>;
247 fsl,magic-packet; 250 fsl,magic-packet;
248 phy-handle = <ðphy0>; 251 phy-handle = <ðphy0>;
249 phy-mode = "rgmii-id"; 252 phy-mode = "rgmii-id";
250 253
251 mdio { 254 mdio {
252 #address-cells = <1>; 255 #address-cells = <1>;
253 #size-cells = <0>; 256 #size-cells = <0>;
254 257
255 ethphy0: ethernet-phy@7 { 258 ethphy0: ethernet-phy@7 {
256 compatible = "ethernet 259 compatible = "ethernet-phy-ieee802.3-c22";
257 reg = <7>; 260 reg = <7>;
258 interrupt-parent = <&l 261 interrupt-parent = <&lsio_gpio1>;
259 interrupts = <29 IRQ_T 262 interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
260 micrel,led-mode = <0>; 263 micrel,led-mode = <0>;
261 reset-assert-us = <2>; 264 reset-assert-us = <2>;
262 reset-deassert-us = <2 265 reset-deassert-us = <2>;
263 reset-gpios = <&lsio_g 266 reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>;
>> 267 reset-names = "phy-reset";
264 }; 268 };
265 }; 269 };
266 }; 270 };
267 271
268 /* Apalis CAN1 */ 272 /* Apalis CAN1 */
269 &flexcan1 { 273 &flexcan1 {
270 pinctrl-names = "default"; 274 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_flexcan1>; 275 pinctrl-0 = <&pinctrl_flexcan1>;
272 }; 276 };
273 277
274 /* Apalis CAN2 */ 278 /* Apalis CAN2 */
275 &flexcan2 { 279 &flexcan2 {
276 pinctrl-names = "default"; 280 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_flexcan2>; 281 pinctrl-0 = <&pinctrl_flexcan2>;
278 }; 282 };
279 283
280 /* Apalis CAN3 (optional) */ 284 /* Apalis CAN3 (optional) */
281 &flexcan3 { 285 &flexcan3 {
282 pinctrl-names = "default"; 286 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_flexcan3>; 287 pinctrl-0 = <&pinctrl_flexcan3>;
284 }; 288 };
285 289
286 /* TODO: Apalis HDMI1 */ 290 /* TODO: Apalis HDMI1 */
287 291
288 /* On-module I2C */ 292 /* On-module I2C */
289 &i2c1 { 293 &i2c1 {
290 pinctrl-names = "default"; 294 pinctrl-names = "default";
291 pinctrl-0 = <&pinctrl_lpi2c1>; 295 pinctrl-0 = <&pinctrl_lpi2c1>;
292 #address-cells = <1>; 296 #address-cells = <1>;
293 #size-cells = <0>; 297 #size-cells = <0>;
294 clock-frequency = <100000>; 298 clock-frequency = <100000>;
295 status = "okay"; 299 status = "okay";
296 300
297 /* TODO: Audio Codec */ 301 /* TODO: Audio Codec */
298 302
299 /* USB3503A */ 303 /* USB3503A */
300 usb-hub@8 { 304 usb-hub@8 {
301 compatible = "smsc,usb3503a"; 305 compatible = "smsc,usb3503a";
302 reg = <0x08>; 306 reg = <0x08>;
303 pinctrl-names = "default"; 307 pinctrl-names = "default";
304 pinctrl-0 = <&pinctrl_usb3503a 308 pinctrl-0 = <&pinctrl_usb3503a>;
305 connect-gpios = <&lsio_gpio0 3 309 connect-gpios = <&lsio_gpio0 31 GPIO_ACTIVE_LOW>;
306 initial-mode = <1>; 310 initial-mode = <1>;
307 intn-gpios = <&lsio_gpio1 1 GP 311 intn-gpios = <&lsio_gpio1 1 GPIO_ACTIVE_HIGH>;
308 refclk-frequency = <25000000>; 312 refclk-frequency = <25000000>;
309 reset-gpios = <&lsio_gpio1 2 G 313 reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
310 }; 314 };
311 }; 315 };
312 316
313 /* Apalis I2C1 */ 317 /* Apalis I2C1 */
314 &i2c2 { 318 &i2c2 {
315 pinctrl-names = "default"; 319 pinctrl-names = "default";
316 pinctrl-0 = <&pinctrl_lpi2c2>; 320 pinctrl-0 = <&pinctrl_lpi2c2>;
317 #address-cells = <1>; 321 #address-cells = <1>;
318 #size-cells = <0>; 322 #size-cells = <0>;
319 clock-frequency = <100000>; 323 clock-frequency = <100000>;
320 324
321 atmel_mxt_ts: touch@4a { 325 atmel_mxt_ts: touch@4a {
322 compatible = "atmel,maxtouch"; 326 compatible = "atmel,maxtouch";
323 reg = <0x4a>; 327 reg = <0x4a>;
324 interrupt-parent = <&lsio_gpio 328 interrupt-parent = <&lsio_gpio4>;
325 interrupts = <1 IRQ_TYPE_EDGE_ 329 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; /* Apalis GPIO5 */
326 pinctrl-names = "default"; 330 pinctrl-names = "default";
327 pinctrl-0 = <&pinctrl_gpio5>, 331 pinctrl-0 = <&pinctrl_gpio5>, <&pinctrl_gpio6>;
328 reset-gpios = <&lsio_gpio4 2 G 332 reset-gpios = <&lsio_gpio4 2 GPIO_ACTIVE_LOW>; /* Apalis GPIO6 */
329 status = "disabled"; 333 status = "disabled";
330 }; 334 };
331 335
332 /* M41T0M6 real time clock on carrier 336 /* M41T0M6 real time clock on carrier board */
333 rtc_i2c: rtc@68 { 337 rtc_i2c: rtc@68 {
334 compatible = "st,m41t0"; 338 compatible = "st,m41t0";
335 reg = <0x68>; 339 reg = <0x68>;
336 status = "disabled"; 340 status = "disabled";
337 }; 341 };
338 }; 342 };
339 343
340 /* Apalis I2C3 (CAM) */ 344 /* Apalis I2C3 (CAM) */
341 &i2c3 { 345 &i2c3 {
342 pinctrl-names = "default"; 346 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_lpi2c3>; 347 pinctrl-0 = <&pinctrl_lpi2c3>;
344 #address-cells = <1>; 348 #address-cells = <1>;
345 #size-cells = <0>; 349 #size-cells = <0>;
346 clock-frequency = <100000>; 350 clock-frequency = <100000>;
347 }; 351 };
348 352
349 &jpegdec { 353 &jpegdec {
350 status = "okay"; 354 status = "okay";
351 }; 355 };
352 356
353 &jpegenc { 357 &jpegenc {
354 status = "okay"; 358 status = "okay";
355 }; 359 };
356 360
357 /* TODO: Apalis LVDS1 */ 361 /* TODO: Apalis LVDS1 */
358 362
359 /* Apalis SPI1 */ 363 /* Apalis SPI1 */
360 &lpspi0 { 364 &lpspi0 {
361 pinctrl-names = "default"; 365 pinctrl-names = "default";
362 pinctrl-0 = <&pinctrl_lpspi0>; 366 pinctrl-0 = <&pinctrl_lpspi0>;
363 #address-cells = <1>; 367 #address-cells = <1>;
364 #size-cells = <0>; 368 #size-cells = <0>;
365 cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_ 369 cs-gpios = <&lsio_gpio3 5 GPIO_ACTIVE_LOW>;
366 }; 370 };
367 371
368 /* Apalis SPI2 */ 372 /* Apalis SPI2 */
369 &lpspi2 { 373 &lpspi2 {
370 pinctrl-names = "default"; 374 pinctrl-names = "default";
371 pinctrl-0 = <&pinctrl_lpspi2>; 375 pinctrl-0 = <&pinctrl_lpspi2>;
372 #address-cells = <1>; 376 #address-cells = <1>;
373 #size-cells = <0>; 377 #size-cells = <0>;
374 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE 378 cs-gpios = <&lsio_gpio3 10 GPIO_ACTIVE_LOW>;
375 }; 379 };
376 380
377 /* Apalis UART3 */ 381 /* Apalis UART3 */
378 &lpuart0 { 382 &lpuart0 {
379 pinctrl-names = "default"; 383 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_lpuart0>; 384 pinctrl-0 = <&pinctrl_lpuart0>;
381 }; 385 };
382 386
383 /* Apalis UART1 */ 387 /* Apalis UART1 */
384 &lpuart1 { 388 &lpuart1 {
385 pinctrl-names = "default"; 389 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_lpuart1>; 390 pinctrl-0 = <&pinctrl_lpuart1>;
387 }; 391 };
388 392
389 /* Apalis UART4 */ 393 /* Apalis UART4 */
390 &lpuart2 { 394 &lpuart2 {
391 pinctrl-names = "default"; 395 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_lpuart2>; 396 pinctrl-0 = <&pinctrl_lpuart2>;
393 }; 397 };
394 398
395 /* Apalis UART2 */ 399 /* Apalis UART2 */
396 &lpuart3 { 400 &lpuart3 {
397 pinctrl-names = "default"; 401 pinctrl-names = "default";
398 pinctrl-0 = <&pinctrl_lpuart3>; 402 pinctrl-0 = <&pinctrl_lpuart3>;
399 }; 403 };
400 404
401 &lsio_gpio0 { 405 &lsio_gpio0 {
402 gpio-line-names = "MXM3_279", 406 gpio-line-names = "MXM3_279",
403 "MXM3_277", 407 "MXM3_277",
404 "MXM3_135", 408 "MXM3_135",
405 "MXM3_203", 409 "MXM3_203",
406 "MXM3_201", 410 "MXM3_201",
407 "MXM3_275", 411 "MXM3_275",
408 "MXM3_110", 412 "MXM3_110",
409 "MXM3_120", 413 "MXM3_120",
410 "MXM3_1/GPIO1", 414 "MXM3_1/GPIO1",
411 "MXM3_3/GPIO2", 415 "MXM3_3/GPIO2",
412 "MXM3_124", 416 "MXM3_124",
413 "MXM3_122", 417 "MXM3_122",
414 "MXM3_5/GPIO3", 418 "MXM3_5/GPIO3",
415 "MXM3_7/GPIO4", 419 "MXM3_7/GPIO4",
416 "", 420 "",
417 "", 421 "",
418 "MXM3_4", 422 "MXM3_4",
419 "MXM3_211", 423 "MXM3_211",
420 "MXM3_209", 424 "MXM3_209",
421 "MXM3_2", 425 "MXM3_2",
422 "MXM3_136", 426 "MXM3_136",
423 "MXM3_134", 427 "MXM3_134",
424 "MXM3_6", 428 "MXM3_6",
425 "MXM3_8", 429 "MXM3_8",
426 "MXM3_112", 430 "MXM3_112",
427 "MXM3_118", 431 "MXM3_118",
428 "MXM3_114", 432 "MXM3_114",
429 "MXM3_116"; 433 "MXM3_116";
430 }; 434 };
431 435
432 &lsio_gpio1 { 436 &lsio_gpio1 {
433 gpio-line-names = "", 437 gpio-line-names = "",
434 "", 438 "",
435 "", 439 "",
436 "", 440 "",
437 "MXM3_286", 441 "MXM3_286",
438 "", 442 "",
439 "MXM3_87", 443 "MXM3_87",
440 "MXM3_99", 444 "MXM3_99",
441 "MXM3_138", 445 "MXM3_138",
442 "MXM3_140", 446 "MXM3_140",
443 "MXM3_239", 447 "MXM3_239",
444 "", 448 "",
445 "MXM3_281", 449 "MXM3_281",
446 "MXM3_283", 450 "MXM3_283",
447 "MXM3_126", 451 "MXM3_126",
448 "MXM3_132", 452 "MXM3_132",
449 "", 453 "",
450 "", 454 "",
451 "", 455 "",
452 "", 456 "",
453 "MXM3_173", 457 "MXM3_173",
454 "MXM3_175", 458 "MXM3_175",
455 "MXM3_123"; 459 "MXM3_123";
456 460
457 hdmi-ctrl-hog { 461 hdmi-ctrl-hog {
458 pinctrl-names = "default"; 462 pinctrl-names = "default";
459 pinctrl-0 = <&pinctrl_hdmi_ctr 463 pinctrl-0 = <&pinctrl_hdmi_ctrl>;
460 gpio-hog; 464 gpio-hog;
461 gpios = <30 GPIO_ACTIVE_HIGH>; 465 gpios = <30 GPIO_ACTIVE_HIGH>;
462 line-name = "CONNECTOR_IS_HDMI 466 line-name = "CONNECTOR_IS_HDMI";
463 /* Set signals depending on HD 467 /* Set signals depending on HDP device type, 0 DP, 1 HDMI */
464 output-high; 468 output-high;
465 }; 469 };
466 }; 470 };
467 471
468 &lsio_gpio2 { 472 &lsio_gpio2 {
469 gpio-line-names = "", 473 gpio-line-names = "",
470 "", 474 "",
471 "", 475 "",
472 "", 476 "",
473 "", 477 "",
474 "", 478 "",
475 "", 479 "",
476 "MXM3_198", 480 "MXM3_198",
477 "MXM3_35", 481 "MXM3_35",
478 "MXM3_164", 482 "MXM3_164",
479 "", 483 "",
480 "", 484 "",
481 "", 485 "",
482 "", 486 "",
483 "MXM3_217", 487 "MXM3_217",
484 "MXM3_215", 488 "MXM3_215",
485 "", 489 "",
486 "", 490 "",
487 "MXM3_193", 491 "MXM3_193",
488 "MXM3_194", 492 "MXM3_194",
489 "MXM3_37", 493 "MXM3_37",
490 "", 494 "",
491 "MXM3_271", 495 "MXM3_271",
492 "MXM3_273", 496 "MXM3_273",
493 "MXM3_195", 497 "MXM3_195",
494 "MXM3_197", 498 "MXM3_197",
495 "MXM3_177", 499 "MXM3_177",
496 "MXM3_179", 500 "MXM3_179",
497 "MXM3_181", 501 "MXM3_181",
498 "MXM3_183", 502 "MXM3_183",
499 "MXM3_185", 503 "MXM3_185",
500 "MXM3_187"; 504 "MXM3_187";
501 505
>> 506 /*
>> 507 * Add GPIO2_20 as a wakeup source:
>> 508 * Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO)
>> 509 * Type: 5 SC_PAD_WAKEUP_FALL_EDGE
>> 510 * Line: 20
>> 511 */
>> 512 pad-wakeup = <IMX8QM_SPI3_CS0 5 20>;
>> 513 pad-wakeup-num = <1>;
>> 514
502 pcie-wifi-hog { 515 pcie-wifi-hog {
503 pinctrl-names = "default"; 516 pinctrl-names = "default";
504 pinctrl-0 = <&pinctrl_pcie_wif 517 pinctrl-0 = <&pinctrl_pcie_wifi_refclk>;
505 gpio-hog; 518 gpio-hog;
506 gpios = <11 GPIO_ACTIVE_HIGH>; 519 gpios = <11 GPIO_ACTIVE_HIGH>;
507 line-name = "PCIE_WIFI_CLK"; 520 line-name = "PCIE_WIFI_CLK";
508 output-high; 521 output-high;
509 }; 522 };
510 }; 523 };
511 524
512 &lsio_gpio3 { 525 &lsio_gpio3 {
513 gpio-line-names = "MXM3_191", 526 gpio-line-names = "MXM3_191",
514 "", 527 "",
515 "MXM3_221", 528 "MXM3_221",
516 "MXM3_225", 529 "MXM3_225",
517 "MXM3_223", 530 "MXM3_223",
518 "MXM3_227", 531 "MXM3_227",
519 "MXM3_200", 532 "MXM3_200",
520 "MXM3_235", 533 "MXM3_235",
521 "MXM3_231", 534 "MXM3_231",
522 "MXM3_229", 535 "MXM3_229",
523 "MXM3_233", 536 "MXM3_233",
524 "MXM3_204", 537 "MXM3_204",
525 "MXM3_196", 538 "MXM3_196",
526 "", 539 "",
527 "MXM3_202", 540 "MXM3_202",
528 "", 541 "",
529 "", 542 "",
530 "", 543 "",
531 "MXM3_305", 544 "MXM3_305",
532 "MXM3_307", 545 "MXM3_307",
533 "MXM3_309", 546 "MXM3_309",
534 "MXM3_311", 547 "MXM3_311",
535 "MXM3_315", 548 "MXM3_315",
536 "MXM3_317", 549 "MXM3_317",
537 "MXM3_319", 550 "MXM3_319",
538 "MXM3_321", 551 "MXM3_321",
539 "MXM3_15/GPIO7", 552 "MXM3_15/GPIO7",
540 "MXM3_63", 553 "MXM3_63",
541 "MXM3_17/GPIO8", 554 "MXM3_17/GPIO8",
542 "MXM3_12", 555 "MXM3_12",
543 "MXM3_14", 556 "MXM3_14",
544 "MXM3_16"; 557 "MXM3_16";
545 }; 558 };
546 559
547 &lsio_gpio4 { 560 &lsio_gpio4 {
548 gpio-line-names = "MXM3_18", 561 gpio-line-names = "MXM3_18",
549 "MXM3_11/GPIO5", 562 "MXM3_11/GPIO5",
550 "MXM3_13/GPIO6", 563 "MXM3_13/GPIO6",
551 "MXM3_274", 564 "MXM3_274",
552 "MXM3_84", 565 "MXM3_84",
553 "MXM3_262", 566 "MXM3_262",
554 "MXM3_96", 567 "MXM3_96",
555 "", 568 "",
556 "", 569 "",
557 "", 570 "",
558 "", 571 "",
559 "", 572 "",
560 "MXM3_190", 573 "MXM3_190",
561 "", 574 "",
562 "", 575 "",
563 "", 576 "",
564 "MXM3_269", 577 "MXM3_269",
565 "MXM3_251", 578 "MXM3_251",
566 "MXM3_253", 579 "MXM3_253",
567 "MXM3_295", 580 "MXM3_295",
568 "MXM3_299", 581 "MXM3_299",
569 "MXM3_301", 582 "MXM3_301",
570 "MXM3_297", 583 "MXM3_297",
571 "MXM3_293", 584 "MXM3_293",
572 "MXM3_291", 585 "MXM3_291",
573 "MXM3_289", 586 "MXM3_289",
574 "MXM3_287"; 587 "MXM3_287";
575 588
576 /* Enable pcie root / sata ref clock u 589 /* Enable pcie root / sata ref clock unconditionally */
577 pcie-sata-hog { 590 pcie-sata-hog {
578 pinctrl-names = "default"; 591 pinctrl-names = "default";
579 pinctrl-0 = <&pinctrl_pcie_sat 592 pinctrl-0 = <&pinctrl_pcie_sata_refclk>;
580 gpio-hog; 593 gpio-hog;
581 gpios = <11 GPIO_ACTIVE_HIGH>; 594 gpios = <11 GPIO_ACTIVE_HIGH>;
582 line-name = "PCIE_SATA_CLK"; 595 line-name = "PCIE_SATA_CLK";
583 output-high; 596 output-high;
584 }; 597 };
585 }; 598 };
586 599
587 &lsio_gpio5 { 600 &lsio_gpio5 {
588 gpio-line-names = "", 601 gpio-line-names = "",
589 "", 602 "",
590 "", 603 "",
591 "", 604 "",
592 "", 605 "",
593 "", 606 "",
594 "", 607 "",
595 "", 608 "",
596 "", 609 "",
597 "", 610 "",
598 "", 611 "",
599 "", 612 "",
600 "", 613 "",
601 "", 614 "",
602 "MXM3_150", 615 "MXM3_150",
603 "MXM3_160", 616 "MXM3_160",
604 "MXM3_162", 617 "MXM3_162",
605 "MXM3_144", 618 "MXM3_144",
606 "MXM3_146", 619 "MXM3_146",
607 "MXM3_148", 620 "MXM3_148",
608 "MXM3_152", 621 "MXM3_152",
609 "MXM3_156", 622 "MXM3_156",
610 "MXM3_158", 623 "MXM3_158",
611 "MXM3_159", 624 "MXM3_159",
612 "MXM3_184", 625 "MXM3_184",
613 "MXM3_180", 626 "MXM3_180",
614 "MXM3_186", 627 "MXM3_186",
615 "MXM3_188", 628 "MXM3_188",
616 "MXM3_176", 629 "MXM3_176",
617 "MXM3_178"; 630 "MXM3_178";
618 }; 631 };
619 632
620 &lsio_gpio6 { 633 &lsio_gpio6 {
621 gpio-line-names = "", 634 gpio-line-names = "",
622 "", 635 "",
623 "", 636 "",
624 "", 637 "",
625 "", 638 "",
626 "", 639 "",
627 "", 640 "",
628 "", 641 "",
629 "", 642 "",
630 "", 643 "",
631 "MXM3_261", 644 "MXM3_261",
632 "MXM3_263", 645 "MXM3_263",
633 "MXM3_259", 646 "MXM3_259",
634 "MXM3_257", 647 "MXM3_257",
635 "MXM3_255", 648 "MXM3_255",
636 "MXM3_128", 649 "MXM3_128",
637 "MXM3_130", 650 "MXM3_130",
638 "MXM3_265", 651 "MXM3_265",
639 "MXM3_249", 652 "MXM3_249",
640 "MXM3_247", 653 "MXM3_247",
641 "MXM3_245", 654 "MXM3_245",
642 "MXM3_243"; 655 "MXM3_243";
643 }; 656 };
644 657
645 /* Apalis PWM3, MXM3 pin 6 */ 658 /* Apalis PWM3, MXM3 pin 6 */
646 &lsio_pwm0 { 659 &lsio_pwm0 {
647 pinctrl-names = "default"; 660 pinctrl-names = "default";
648 pinctrl-0 = <&pinctrl_pwm0>; 661 pinctrl-0 = <&pinctrl_pwm0>;
649 #pwm-cells = <3>; 662 #pwm-cells = <3>;
650 }; 663 };
651 664
652 /* Apalis PWM4, MXM3 pin 8 */ 665 /* Apalis PWM4, MXM3 pin 8 */
653 &lsio_pwm1 { 666 &lsio_pwm1 {
654 pinctrl-names = "default"; 667 pinctrl-names = "default";
655 pinctrl-0 = <&pinctrl_pwm1>; 668 pinctrl-0 = <&pinctrl_pwm1>;
656 #pwm-cells = <3>; 669 #pwm-cells = <3>;
657 }; 670 };
658 671
659 /* Apalis PWM1, MXM3 pin 2 */ 672 /* Apalis PWM1, MXM3 pin 2 */
660 &lsio_pwm2 { 673 &lsio_pwm2 {
661 pinctrl-names = "default"; 674 pinctrl-names = "default";
662 pinctrl-0 = <&pinctrl_pwm2>; 675 pinctrl-0 = <&pinctrl_pwm2>;
663 #pwm-cells = <3>; 676 #pwm-cells = <3>;
664 }; 677 };
665 678
666 /* Apalis PWM2, MXM3 pin 4 */ 679 /* Apalis PWM2, MXM3 pin 4 */
667 &lsio_pwm3 { 680 &lsio_pwm3 {
668 pinctrl-names = "default"; 681 pinctrl-names = "default";
669 pinctrl-0 = <&pinctrl_pwm3>; 682 pinctrl-0 = <&pinctrl_pwm3>;
670 #pwm-cells = <3>; 683 #pwm-cells = <3>;
671 }; 684 };
672 685
673 /* Messaging Units */ 686 /* Messaging Units */
674 &mu_m0 { !! 687 &mu_m0{
675 status = "okay"; 688 status = "okay";
676 }; 689 };
677 690
678 &mu1_m0 { !! 691 &mu1_m0{
679 status = "okay"; 692 status = "okay";
680 }; 693 };
681 694
682 &mu2_m0 { !! 695 &mu2_m0{
683 status = "okay"; 696 status = "okay";
684 }; 697 };
685 698
686 /* TODO: Apalis PCIE1 */ 699 /* TODO: Apalis PCIE1 */
687 700
688 /* TODO: On-module Wi-Fi */ 701 /* TODO: On-module Wi-Fi */
689 702
690 /* TODO: Apalis BKL1_PWM */ 703 /* TODO: Apalis BKL1_PWM */
691 704
692 /* TODO: Apalis DAP1 */ 705 /* TODO: Apalis DAP1 */
693 706
694 /* TODO: Analogue Audio */ 707 /* TODO: Analogue Audio */
695 708
696 /* TODO: Apalis SATA1 */ 709 /* TODO: Apalis SATA1 */
697 710
698 /* TODO: Apalis SPDIF1 */ 711 /* TODO: Apalis SPDIF1 */
699 712
700 /* TODO: Thermal Zones */ 713 /* TODO: Thermal Zones */
701 714
702 /* TODO: Apalis USBH2, Apalis USBH3 and on-mod 715 /* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
703 716
704 /* TODO: Apalis USBH4 */ 717 /* TODO: Apalis USBH4 */
705 718
706 /* Apalis USBO1 */ 719 /* Apalis USBO1 */
707 &usbphy1 { 720 &usbphy1 {
708 phy-3p0-supply = <®_usb_phy>; 721 phy-3p0-supply = <®_usb_phy>;
709 status = "okay"; 722 status = "okay";
710 }; 723 };
711 724
712 &usbotg1 { 725 &usbotg1 {
713 pinctrl-names = "default"; 726 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_usbotg1>; 727 pinctrl-0 = <&pinctrl_usbotg1>;
715 adp-disable; 728 adp-disable;
716 hnp-disable; 729 hnp-disable;
717 over-current-active-low; 730 over-current-active-low;
718 power-active-high; 731 power-active-high;
719 srp-disable; 732 srp-disable;
720 }; 733 };
721 734
722 /* On-module eMMC */ 735 /* On-module eMMC */
723 &usdhc1 { 736 &usdhc1 {
724 pinctrl-names = "default", "state_100m 737 pinctrl-names = "default", "state_100mhz", "state_200mhz";
725 pinctrl-0 = <&pinctrl_usdhc1>; 738 pinctrl-0 = <&pinctrl_usdhc1>;
726 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 739 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
727 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 740 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
728 bus-width = <8>; 741 bus-width = <8>;
729 non-removable; 742 non-removable;
730 status = "okay"; 743 status = "okay";
731 }; 744 };
732 745
733 /* Apalis MMC1 */ 746 /* Apalis MMC1 */
734 &usdhc2 { 747 &usdhc2 {
735 pinctrl-names = "default", "state_100m 748 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
736 pinctrl-0 = <&pinctrl_usdhc2_4bit>, 749 pinctrl-0 = <&pinctrl_usdhc2_4bit>,
737 <&pinctrl_usdhc2_8bit>, 750 <&pinctrl_usdhc2_8bit>,
738 <&pinctrl_mmc1_cd>; 751 <&pinctrl_mmc1_cd>;
739 pinctrl-1 = <&pinctrl_usdhc2_4bit_100m 752 pinctrl-1 = <&pinctrl_usdhc2_4bit_100mhz>,
740 <&pinctrl_usdhc2_8bit_100m 753 <&pinctrl_usdhc2_8bit_100mhz>,
741 <&pinctrl_mmc1_cd>; 754 <&pinctrl_mmc1_cd>;
742 pinctrl-2 = <&pinctrl_usdhc2_4bit_200m 755 pinctrl-2 = <&pinctrl_usdhc2_4bit_200mhz>,
743 <&pinctrl_usdhc2_8bit_200m 756 <&pinctrl_usdhc2_8bit_200mhz>,
744 <&pinctrl_mmc1_cd>; 757 <&pinctrl_mmc1_cd>;
745 pinctrl-3 = <&pinctrl_usdhc2_4bit_slee 758 pinctrl-3 = <&pinctrl_usdhc2_4bit_sleep>,
746 <&pinctrl_usdhc2_8bit_slee 759 <&pinctrl_usdhc2_8bit_sleep>,
747 <&pinctrl_mmc1_cd_sleep>; 760 <&pinctrl_mmc1_cd_sleep>;
748 bus-width = <8>; 761 bus-width = <8>;
749 cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_ 762 cd-gpios = <&lsio_gpio2 9 GPIO_ACTIVE_LOW>; /* Apalis MMC1_CD# */
750 no-1-8-v; 763 no-1-8-v;
751 }; 764 };
752 765
753 /* Apalis SD1 */ 766 /* Apalis SD1 */
754 &usdhc3 { 767 &usdhc3 {
755 pinctrl-names = "default", "state_100m 768 pinctrl-names = "default", "state_100mhz", "state_200mhz";
756 pinctrl-0 = <&pinctrl_usdhc3>, <&pinct 769 pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_sd1_cd>;
757 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, 770 pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_sd1_cd>;
758 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, 771 pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_sd1_cd>;
759 bus-width = <4>; 772 bus-width = <4>;
760 cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE 773 cd-gpios = <&lsio_gpio4 12 GPIO_ACTIVE_LOW>; /* Apalis SD1_CD# */
761 no-1-8-v; 774 no-1-8-v;
762 }; 775 };
763 776
764 /* Video Processing Unit */ 777 /* Video Processing Unit */
765 &vpu { 778 &vpu {
766 compatible = "nxp,imx8qm-vpu"; 779 compatible = "nxp,imx8qm-vpu";
767 status = "okay"; 780 status = "okay";
768 }; 781 };
769 782
770 &vpu_core0 { 783 &vpu_core0 {
771 reg = <0x2d080000 0x10000>; 784 reg = <0x2d080000 0x10000>;
772 memory-region = <&decoder_boot>, <&dec 785 memory-region = <&decoder_boot>, <&decoder_rpc>;
773 status = "okay"; 786 status = "okay";
774 }; 787 };
775 788
776 &vpu_core1 { 789 &vpu_core1 {
777 reg = <0x2d090000 0x10000>; 790 reg = <0x2d090000 0x10000>;
778 memory-region = <&encoder1_boot>, <&en 791 memory-region = <&encoder1_boot>, <&encoder1_rpc>;
779 status = "okay"; 792 status = "okay";
780 }; 793 };
781 794
782 &vpu_core2 { 795 &vpu_core2 {
783 reg = <0x2d0a0000 0x10000>; 796 reg = <0x2d0a0000 0x10000>;
784 memory-region = <&encoder2_boot>, <&en 797 memory-region = <&encoder2_boot>, <&encoder2_rpc>;
785 status = "okay"; 798 status = "okay";
786 }; 799 };
787 800
788 &iomuxc { 801 &iomuxc {
789 pinctrl-names = "default"; 802 pinctrl-names = "default";
790 pinctrl-0 = <&pinctrl_cam1_gpios>, <&p 803 pinctrl-0 = <&pinctrl_cam1_gpios>, <&pinctrl_dap1_gpios>,
791 <&pinctrl_esai0_gpios>, <& 804 <&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
792 <&pinctrl_gpio3>, <&pinctr 805 <&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
793 <&pinctrl_gpio_usbh_oc_n>, 806 <&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
794 <&pinctrl_lvds0_i2c0_gpio> 807 <&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
795 <&pinctrl_mipi_dsi_0_1_en> 808 <&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
796 <&pinctrl_mlb_gpios>, <&pi 809 <&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
797 <&pinctrl_sata1_act>, <&pi 810 <&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
798 <&pinctrl_usdhc1_gpios>; 811 <&pinctrl_usdhc1_gpios>;
799 812
800 /* Apalis AN1_ADC */ 813 /* Apalis AN1_ADC */
801 pinctrl_adc0: adc0grp { 814 pinctrl_adc0: adc0grp {
802 fsl,pins = /* Apalis AN1_ADC0 815 fsl,pins = /* Apalis AN1_ADC0 */
803 <IMX8QM_ADC_IN0_DMA 816 <IMX8QM_ADC_IN0_DMA_ADC0_IN0 0xc0000060>,
804 /* Apalis AN1_ADC1 817 /* Apalis AN1_ADC1 */
805 <IMX8QM_ADC_IN1_DMA 818 <IMX8QM_ADC_IN1_DMA_ADC0_IN1 0xc0000060>,
806 /* Apalis AN1_ADC2 819 /* Apalis AN1_ADC2 */
807 <IMX8QM_ADC_IN2_DMA 820 <IMX8QM_ADC_IN2_DMA_ADC0_IN2 0xc0000060>,
808 /* Apalis AN1_TSWIP 821 /* Apalis AN1_TSWIP_ADC3 */
809 <IMX8QM_ADC_IN3_DMA 822 <IMX8QM_ADC_IN3_DMA_ADC0_IN3 0xc0000060>;
810 }; 823 };
811 824
812 /* Apalis AN1_TS */ 825 /* Apalis AN1_TS */
813 pinctrl_adc1: adc1grp { 826 pinctrl_adc1: adc1grp {
814 fsl,pins = /* Apalis AN1_TSPX 827 fsl,pins = /* Apalis AN1_TSPX */
815 <IMX8QM_ADC_IN4_DMA 828 <IMX8QM_ADC_IN4_DMA_ADC1_IN0 0xc0000060>,
816 /* Apalis AN1_TSMX 829 /* Apalis AN1_TSMX */
817 <IMX8QM_ADC_IN5_DMA 830 <IMX8QM_ADC_IN5_DMA_ADC1_IN1 0xc0000060>,
818 /* Apalis AN1_TSPY 831 /* Apalis AN1_TSPY */
819 <IMX8QM_ADC_IN6_DMA 832 <IMX8QM_ADC_IN6_DMA_ADC1_IN2 0xc0000060>,
820 /* Apalis AN1_TSMY 833 /* Apalis AN1_TSMY */
821 <IMX8QM_ADC_IN7_DMA 834 <IMX8QM_ADC_IN7_DMA_ADC1_IN3 0xc0000060>;
822 }; 835 };
823 836
824 /* Apalis CAM1 */ 837 /* Apalis CAM1 */
825 pinctrl_cam1_gpios: cam1gpiosgrp { 838 pinctrl_cam1_gpios: cam1gpiosgrp {
826 fsl,pins = /* Apalis CAM1_D7 * 839 fsl,pins = /* Apalis CAM1_D7 */
827 <IMX8QM_MIPI_DSI1_I 840 <IMX8QM_MIPI_DSI1_I2C0_SCL_LSIO_GPIO1_IO20 0x00000021>,
828 /* Apalis CAM1_D6 * 841 /* Apalis CAM1_D6 */
829 <IMX8QM_MIPI_DSI1_I 842 <IMX8QM_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO21 0x00000021>,
830 /* Apalis CAM1_D5 * 843 /* Apalis CAM1_D5 */
831 <IMX8QM_ESAI0_TX0_L 844 <IMX8QM_ESAI0_TX0_LSIO_GPIO2_IO26 0x00000021>,
832 /* Apalis CAM1_D4 * 845 /* Apalis CAM1_D4 */
833 <IMX8QM_ESAI0_TX1_L 846 <IMX8QM_ESAI0_TX1_LSIO_GPIO2_IO27 0x00000021>,
834 /* Apalis CAM1_D3 * 847 /* Apalis CAM1_D3 */
835 <IMX8QM_ESAI0_TX2_R 848 <IMX8QM_ESAI0_TX2_RX3_LSIO_GPIO2_IO28 0x00000021>,
836 /* Apalis CAM1_D2 * 849 /* Apalis CAM1_D2 */
837 <IMX8QM_ESAI0_TX3_R 850 <IMX8QM_ESAI0_TX3_RX2_LSIO_GPIO2_IO29 0x00000021>,
838 /* Apalis CAM1_D1 * 851 /* Apalis CAM1_D1 */
839 <IMX8QM_ESAI0_TX4_R 852 <IMX8QM_ESAI0_TX4_RX1_LSIO_GPIO2_IO30 0x00000021>,
840 /* Apalis CAM1_D0 * 853 /* Apalis CAM1_D0 */
841 <IMX8QM_ESAI0_TX5_R 854 <IMX8QM_ESAI0_TX5_RX0_LSIO_GPIO2_IO31 0x00000021>,
842 /* Apalis CAM1_PCLK 855 /* Apalis CAM1_PCLK */
843 <IMX8QM_MCLK_IN0_LS 856 <IMX8QM_MCLK_IN0_LSIO_GPIO3_IO00 0x00000021>,
844 /* Apalis CAM1_MCLK 857 /* Apalis CAM1_MCLK */
845 <IMX8QM_SPI3_SDO_LS 858 <IMX8QM_SPI3_SDO_LSIO_GPIO2_IO18 0x00000021>,
846 /* Apalis CAM1_VSYN 859 /* Apalis CAM1_VSYNC */
847 <IMX8QM_ESAI0_SCKR_ 860 <IMX8QM_ESAI0_SCKR_LSIO_GPIO2_IO24 0x00000021>,
848 /* Apalis CAM1_HSYN 861 /* Apalis CAM1_HSYNC */
849 <IMX8QM_ESAI0_SCKT_ 862 <IMX8QM_ESAI0_SCKT_LSIO_GPIO2_IO25 0x00000021>;
850 }; 863 };
851 864
852 /* Apalis DAP1 */ 865 /* Apalis DAP1 */
853 pinctrl_dap1_gpios: dap1gpiosgrp { 866 pinctrl_dap1_gpios: dap1gpiosgrp {
854 fsl,pins = /* Apalis DAP1_MCLK 867 fsl,pins = /* Apalis DAP1_MCLK */
855 <IMX8QM_SPI3_SDI_LS 868 <IMX8QM_SPI3_SDI_LSIO_GPIO2_IO19 0x00000021>,
856 /* Apalis DAP1_D_OU 869 /* Apalis DAP1_D_OUT */
857 <IMX8QM_SAI1_RXC_LS 870 <IMX8QM_SAI1_RXC_LSIO_GPIO3_IO12 0x00000021>,
858 /* Apalis DAP1_RESE 871 /* Apalis DAP1_RESET */
859 <IMX8QM_ESAI1_SCKT_ 872 <IMX8QM_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021>,
860 /* Apalis DAP1_BIT_ 873 /* Apalis DAP1_BIT_CLK */
861 <IMX8QM_SPI0_CS1_LS 874 <IMX8QM_SPI0_CS1_LSIO_GPIO3_IO06 0x00000021>,
862 /* Apalis DAP1_D_IN 875 /* Apalis DAP1_D_IN */
863 <IMX8QM_SAI1_RXFS_L 876 <IMX8QM_SAI1_RXFS_LSIO_GPIO3_IO14 0x00000021>,
864 /* Apalis DAP1_SYNC 877 /* Apalis DAP1_SYNC */
865 <IMX8QM_SPI2_CS1_LS 878 <IMX8QM_SPI2_CS1_LSIO_GPIO3_IO11 0x00000021>,
866 /* On-module Wi-Fi_ 879 /* On-module Wi-Fi_I2S_EN# */
867 <IMX8QM_ESAI1_TX5_R 880 <IMX8QM_ESAI1_TX5_RX0_LSIO_GPIO2_IO13 0x00000021>;
868 }; 881 };
869 882
870 /* Apalis LCD1_G1+2 */ 883 /* Apalis LCD1_G1+2 */
871 pinctrl_esai0_gpios: esai0gpiosgrp { 884 pinctrl_esai0_gpios: esai0gpiosgrp {
872 fsl,pins = /* Apalis LCD1_G1 * 885 fsl,pins = /* Apalis LCD1_G1 */
873 <IMX8QM_ESAI0_FSR_L 886 <IMX8QM_ESAI0_FSR_LSIO_GPIO2_IO22 0x00000021>,
874 /* Apalis LCD1_G2 * 887 /* Apalis LCD1_G2 */
875 <IMX8QM_ESAI0_FST_L 888 <IMX8QM_ESAI0_FST_LSIO_GPIO2_IO23 0x00000021>;
876 }; 889 };
877 890
878 /* On-module Gigabit Ethernet PHY Micr 891 /* On-module Gigabit Ethernet PHY Micrel KSZ9031 for Apalis GLAN */
879 pinctrl_fec1: fec1grp { 892 pinctrl_fec1: fec1grp {
880 fsl,pins = /* Use pads in 3.3V 893 fsl,pins = /* Use pads in 3.3V mode */
881 <IMX8QM_COMP_CTL_GP 894 <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
882 <IMX8QM_ENET0_MDC_C 895 <IMX8QM_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
883 <IMX8QM_ENET0_MDIO_ 896 <IMX8QM_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
884 <IMX8QM_ENET0_RGMII 897 <IMX8QM_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020>,
885 <IMX8QM_ENET0_RGMII 898 <IMX8QM_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020>,
886 <IMX8QM_ENET0_RGMII 899 <IMX8QM_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020>,
887 <IMX8QM_ENET0_RGMII 900 <IMX8QM_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020>,
888 <IMX8QM_ENET0_RGMII 901 <IMX8QM_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020>,
889 <IMX8QM_ENET0_RGMII 902 <IMX8QM_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020>,
890 <IMX8QM_ENET0_RGMII 903 <IMX8QM_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020>,
891 <IMX8QM_ENET0_RGMII 904 <IMX8QM_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020>,
892 <IMX8QM_ENET0_RGMII 905 <IMX8QM_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020>,
893 <IMX8QM_ENET0_RGMII 906 <IMX8QM_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020>,
894 <IMX8QM_ENET0_RGMII 907 <IMX8QM_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020>,
895 <IMX8QM_ENET0_RGMII 908 <IMX8QM_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020>,
896 <IMX8QM_ENET0_REFCL 909 <IMX8QM_ENET0_REFCLK_125M_25M_CONN_ENET0_REFCLK_125M_25M 0x06000020>,
897 /* On-module ETH_RE 910 /* On-module ETH_RESET# */
898 <IMX8QM_LVDS1_GPIO0 911 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
899 /* On-module ETH_IN 912 /* On-module ETH_INT# */
900 <IMX8QM_MIPI_CSI1_M 913 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000060>;
901 }; 914 };
902 915
903 pinctrl_fec1_sleep: fec1-sleepgrp { 916 pinctrl_fec1_sleep: fec1-sleepgrp {
904 fsl,pins = <IMX8QM_COMP_CTL_GP 917 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0>,
905 <IMX8QM_ENET0_MDC_L 918 <IMX8QM_ENET0_MDC_LSIO_GPIO4_IO14 0x04000040>,
906 <IMX8QM_ENET0_MDIO_ 919 <IMX8QM_ENET0_MDIO_LSIO_GPIO4_IO13 0x04000040>,
907 <IMX8QM_ENET0_RGMII 920 <IMX8QM_ENET0_RGMII_TX_CTL_LSIO_GPIO5_IO31 0x04000040>,
908 <IMX8QM_ENET0_RGMII 921 <IMX8QM_ENET0_RGMII_TXC_LSIO_GPIO5_IO30 0x04000040>,
909 <IMX8QM_ENET0_RGMII 922 <IMX8QM_ENET0_RGMII_TXD0_LSIO_GPIO6_IO00 0x04000040>,
910 <IMX8QM_ENET0_RGMII 923 <IMX8QM_ENET0_RGMII_TXD1_LSIO_GPIO6_IO01 0x04000040>,
911 <IMX8QM_ENET0_RGMII 924 <IMX8QM_ENET0_RGMII_TXD2_LSIO_GPIO6_IO02 0x04000040>,
912 <IMX8QM_ENET0_RGMII 925 <IMX8QM_ENET0_RGMII_TXD3_LSIO_GPIO6_IO03 0x04000040>,
913 <IMX8QM_ENET0_RGMII 926 <IMX8QM_ENET0_RGMII_RXC_LSIO_GPIO6_IO04 0x04000040>,
914 <IMX8QM_ENET0_RGMII 927 <IMX8QM_ENET0_RGMII_RX_CTL_LSIO_GPIO6_IO05 0x04000040>,
915 <IMX8QM_ENET0_RGMII 928 <IMX8QM_ENET0_RGMII_RXD0_LSIO_GPIO6_IO06 0x04000040>,
916 <IMX8QM_ENET0_RGMII 929 <IMX8QM_ENET0_RGMII_RXD1_LSIO_GPIO6_IO07 0x04000040>,
917 <IMX8QM_ENET0_RGMII 930 <IMX8QM_ENET0_RGMII_RXD2_LSIO_GPIO6_IO08 0x04000040>,
918 <IMX8QM_ENET0_RGMII 931 <IMX8QM_ENET0_RGMII_RXD3_LSIO_GPIO6_IO09 0x04000040>,
919 <IMX8QM_ENET0_REFCL 932 <IMX8QM_ENET0_REFCLK_125M_25M_LSIO_GPIO4_IO15 0x04000040>,
920 <IMX8QM_LVDS1_GPIO0 933 <IMX8QM_LVDS1_GPIO01_LSIO_GPIO1_IO11 0x06000020>,
921 <IMX8QM_MIPI_CSI1_M 934 <IMX8QM_MIPI_CSI1_MCLK_OUT_LSIO_GPIO1_IO29 0x04000040>;
922 }; 935 };
923 936
924 /* Apalis LCD1_ */ 937 /* Apalis LCD1_ */
925 pinctrl_fec2_gpios: fec2gpiosgrp { 938 pinctrl_fec2_gpios: fec2gpiosgrp {
926 fsl,pins = <IMX8QM_COMP_CTL_GP 939 fsl,pins = <IMX8QM_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0>,
927 /* Apalis LCD1_R1 * 940 /* Apalis LCD1_R1 */
928 <IMX8QM_ENET1_MDC_L 941 <IMX8QM_ENET1_MDC_LSIO_GPIO4_IO18 0x00000021>,
929 /* Apalis LCD1_R0 * 942 /* Apalis LCD1_R0 */
930 <IMX8QM_ENET1_MDIO_ 943 <IMX8QM_ENET1_MDIO_LSIO_GPIO4_IO17 0x00000021>,
931 /* Apalis LCD1_G0 * 944 /* Apalis LCD1_G0 */
932 <IMX8QM_ENET1_REFCL 945 <IMX8QM_ENET1_REFCLK_125M_25M_LSIO_GPIO4_IO16 0x00000021>,
933 /* Apalis LCD1_R7 * 946 /* Apalis LCD1_R7 */
934 <IMX8QM_ENET1_RGMII 947 <IMX8QM_ENET1_RGMII_RX_CTL_LSIO_GPIO6_IO17 0x00000021>,
935 /* Apalis LCD1_DE * 948 /* Apalis LCD1_DE */
936 <IMX8QM_ENET1_RGMII 949 <IMX8QM_ENET1_RGMII_RXD0_LSIO_GPIO6_IO18 0x00000021>,
937 /* Apalis LCD1_HSYN 950 /* Apalis LCD1_HSYNC */
938 <IMX8QM_ENET1_RGMII 951 <IMX8QM_ENET1_RGMII_RXD1_LSIO_GPIO6_IO19 0x00000021>,
939 /* Apalis LCD1_VSYN 952 /* Apalis LCD1_VSYNC */
940 <IMX8QM_ENET1_RGMII 953 <IMX8QM_ENET1_RGMII_RXD2_LSIO_GPIO6_IO20 0x00000021>,
941 /* Apalis LCD1_PCLK 954 /* Apalis LCD1_PCLK */
942 <IMX8QM_ENET1_RGMII 955 <IMX8QM_ENET1_RGMII_RXD3_LSIO_GPIO6_IO21 0x00000021>,
943 /* Apalis LCD1_R6 * 956 /* Apalis LCD1_R6 */
944 <IMX8QM_ENET1_RGMII 957 <IMX8QM_ENET1_RGMII_TX_CTL_LSIO_GPIO6_IO11 0x00000021>,
945 /* Apalis LCD1_R5 * 958 /* Apalis LCD1_R5 */
946 <IMX8QM_ENET1_RGMII 959 <IMX8QM_ENET1_RGMII_TXC_LSIO_GPIO6_IO10 0x00000021>,
947 /* Apalis LCD1_R4 * 960 /* Apalis LCD1_R4 */
948 <IMX8QM_ENET1_RGMII 961 <IMX8QM_ENET1_RGMII_TXD0_LSIO_GPIO6_IO12 0x00000021>,
949 /* Apalis LCD1_R3 * 962 /* Apalis LCD1_R3 */
950 <IMX8QM_ENET1_RGMII 963 <IMX8QM_ENET1_RGMII_TXD1_LSIO_GPIO6_IO13 0x00000021>,
951 /* Apalis LCD1_R2 * 964 /* Apalis LCD1_R2 */
952 <IMX8QM_ENET1_RGMII 965 <IMX8QM_ENET1_RGMII_TXD2_LSIO_GPIO6_IO14 0x00000021>;
953 }; 966 };
954 967
955 /* Apalis CAN1 */ 968 /* Apalis CAN1 */
956 pinctrl_flexcan1: flexcan0grp { 969 pinctrl_flexcan1: flexcan0grp {
957 fsl,pins = <IMX8QM_FLEXCAN0_TX 970 fsl,pins = <IMX8QM_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x00000021>,
958 <IMX8QM_FLEXCAN0_RX 971 <IMX8QM_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x00000021>;
959 }; 972 };
960 973
961 /* Apalis CAN2 */ 974 /* Apalis CAN2 */
962 pinctrl_flexcan2: flexcan1grp { 975 pinctrl_flexcan2: flexcan1grp {
963 fsl,pins = <IMX8QM_FLEXCAN1_TX 976 fsl,pins = <IMX8QM_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x00000021>,
964 <IMX8QM_FLEXCAN1_RX 977 <IMX8QM_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x00000021>;
965 }; 978 };
966 979
967 /* Apalis CAN3 (optional) */ 980 /* Apalis CAN3 (optional) */
968 pinctrl_flexcan3: flexcan2grp { 981 pinctrl_flexcan3: flexcan2grp {
969 fsl,pins = <IMX8QM_FLEXCAN2_TX 982 fsl,pins = <IMX8QM_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x00000021>,
970 <IMX8QM_FLEXCAN2_RX 983 <IMX8QM_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x00000021>;
971 }; 984 };
972 985
973 /* Apalis GPIO1 */ 986 /* Apalis GPIO1 */
974 pinctrl_gpio1: gpio1grp { 987 pinctrl_gpio1: gpio1grp {
975 fsl,pins = <IMX8QM_M40_GPIO0_0 988 fsl,pins = <IMX8QM_M40_GPIO0_00_LSIO_GPIO0_IO08 0x06000021>;
976 }; 989 };
977 990
978 /* Apalis GPIO2 */ 991 /* Apalis GPIO2 */
979 pinctrl_gpio2: gpio2grp { 992 pinctrl_gpio2: gpio2grp {
980 fsl,pins = <IMX8QM_M40_GPIO0_0 993 fsl,pins = <IMX8QM_M40_GPIO0_01_LSIO_GPIO0_IO09 0x06000021>;
981 }; 994 };
982 995
983 /* Apalis GPIO3 */ 996 /* Apalis GPIO3 */
984 pinctrl_gpio3: gpio3grp { 997 pinctrl_gpio3: gpio3grp {
985 fsl,pins = <IMX8QM_M41_GPIO0_0 998 fsl,pins = <IMX8QM_M41_GPIO0_00_LSIO_GPIO0_IO12 0x06000021>;
986 }; 999 };
987 1000
988 /* Apalis GPIO4 */ 1001 /* Apalis GPIO4 */
989 pinctrl_gpio4: gpio4grp { 1002 pinctrl_gpio4: gpio4grp {
990 fsl,pins = <IMX8QM_M41_GPIO0_0 1003 fsl,pins = <IMX8QM_M41_GPIO0_01_LSIO_GPIO0_IO13 0x06000021>;
991 }; 1004 };
992 1005
993 /* Apalis GPIO5 */ 1006 /* Apalis GPIO5 */
994 pinctrl_gpio5: gpio5grp { 1007 pinctrl_gpio5: gpio5grp {
995 fsl,pins = <IMX8QM_FLEXCAN2_RX 1008 fsl,pins = <IMX8QM_FLEXCAN2_RX_LSIO_GPIO4_IO01 0x06000021>;
996 }; 1009 };
997 1010
998 /* Apalis GPIO6 */ 1011 /* Apalis GPIO6 */
999 pinctrl_gpio6: gpio6grp { 1012 pinctrl_gpio6: gpio6grp {
1000 fsl,pins = <IMX8QM_FLEXCAN2_T 1013 fsl,pins = <IMX8QM_FLEXCAN2_TX_LSIO_GPIO4_IO02 0x00000021>;
1001 }; 1014 };
1002 1015
1003 /* Apalis GPIO7 */ 1016 /* Apalis GPIO7 */
1004 pinctrl_gpio7: gpio7grp { 1017 pinctrl_gpio7: gpio7grp {
1005 fsl,pins = <IMX8QM_MLB_SIG_LS 1018 fsl,pins = <IMX8QM_MLB_SIG_LSIO_GPIO3_IO26 0x00000021>;
1006 }; 1019 };
1007 1020
1008 /* Apalis GPIO8 */ 1021 /* Apalis GPIO8 */
1009 pinctrl_gpio8: gpio8grp { 1022 pinctrl_gpio8: gpio8grp {
1010 fsl,pins = <IMX8QM_MLB_DATA_L 1023 fsl,pins = <IMX8QM_MLB_DATA_LSIO_GPIO3_IO28 0x00000021>;
1011 }; 1024 };
1012 1025
1013 /* Apalis BKL1_ON */ 1026 /* Apalis BKL1_ON */
1014 pinctrl_gpio_bkl_on: gpiobklongrp { 1027 pinctrl_gpio_bkl_on: gpiobklongrp {
1015 fsl,pins = <IMX8QM_LVDS0_GPIO 1028 fsl,pins = <IMX8QM_LVDS0_GPIO00_LSIO_GPIO1_IO04 0x00000021>;
1016 }; 1029 };
1017 1030
1018 /* Apalis WAKE1_MICO */ 1031 /* Apalis WAKE1_MICO */
1019 pinctrl_gpio_keys: gpiokeysgrp { 1032 pinctrl_gpio_keys: gpiokeysgrp {
1020 fsl,pins = <IMX8QM_SPI3_CS0_L 1033 fsl,pins = <IMX8QM_SPI3_CS0_LSIO_GPIO2_IO20 0x06700021>;
1021 }; 1034 };
1022 1035
1023 /* Apalis USBH_OC# */ 1036 /* Apalis USBH_OC# */
1024 pinctrl_gpio_usbh_oc_n: gpiousbhocngr 1037 pinctrl_gpio_usbh_oc_n: gpiousbhocngrp {
1025 fsl,pins = <IMX8QM_USB_SS3_TC 1038 fsl,pins = <IMX8QM_USB_SS3_TC3_LSIO_GPIO4_IO06 0x04000021>;
1026 }; 1039 };
1027 1040
1028 /* On-module HDMI_CTRL */ 1041 /* On-module HDMI_CTRL */
1029 pinctrl_hdmi_ctrl: hdmictrlgrp { 1042 pinctrl_hdmi_ctrl: hdmictrlgrp {
1030 fsl,pins = <IMX8QM_MIPI_CSI1_ 1043 fsl,pins = <IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0x00000061>;
1031 }; 1044 };
1032 1045
1033 /* On-module I2C */ 1046 /* On-module I2C */
1034 pinctrl_lpi2c1: lpi2c1grp { 1047 pinctrl_lpi2c1: lpi2c1grp {
1035 fsl,pins = <IMX8QM_GPT0_CLK_D 1048 fsl,pins = <IMX8QM_GPT0_CLK_DMA_I2C1_SCL 0x04000020>,
1036 <IMX8QM_GPT0_CAPTU 1049 <IMX8QM_GPT0_CAPTURE_DMA_I2C1_SDA 0x04000020>;
1037 }; 1050 };
1038 1051
1039 /* Apalis I2C1 */ 1052 /* Apalis I2C1 */
1040 pinctrl_lpi2c2: lpi2c2grp { 1053 pinctrl_lpi2c2: lpi2c2grp {
1041 fsl,pins = <IMX8QM_GPT1_CLK_D 1054 fsl,pins = <IMX8QM_GPT1_CLK_DMA_I2C2_SCL 0x04000020>,
1042 <IMX8QM_GPT1_CAPTU 1055 <IMX8QM_GPT1_CAPTURE_DMA_I2C2_SDA 0x04000020>;
1043 }; 1056 };
1044 1057
1045 /* Apalis I2C3 (CAM) */ 1058 /* Apalis I2C3 (CAM) */
1046 pinctrl_lpi2c3: lpi2c3grp { 1059 pinctrl_lpi2c3: lpi2c3grp {
1047 fsl,pins = <IMX8QM_SIM0_PD_DM 1060 fsl,pins = <IMX8QM_SIM0_PD_DMA_I2C3_SCL 0x04000020>,
1048 <IMX8QM_SIM0_POWER 1061 <IMX8QM_SIM0_POWER_EN_DMA_I2C3_SDA 0x04000020>;
1049 }; 1062 };
1050 1063
1051 /* Apalis SPI1 */ 1064 /* Apalis SPI1 */
1052 pinctrl_lpspi0: lpspi0grp { 1065 pinctrl_lpspi0: lpspi0grp {
1053 fsl,pins = <IMX8QM_SPI0_SCK_D 1066 fsl,pins = <IMX8QM_SPI0_SCK_DMA_SPI0_SCK 0x0600004c>,
1054 <IMX8QM_SPI0_SDO_D 1067 <IMX8QM_SPI0_SDO_DMA_SPI0_SDO 0x0600004c>,
1055 <IMX8QM_SPI0_SDI_D 1068 <IMX8QM_SPI0_SDI_DMA_SPI0_SDI 0x0600004c>,
1056 <IMX8QM_SPI0_CS0_L 1069 <IMX8QM_SPI0_CS0_LSIO_GPIO3_IO05 0x0600004c>;
1057 }; 1070 };
1058 1071
1059 /* Apalis SPI2 */ 1072 /* Apalis SPI2 */
1060 pinctrl_lpspi2: lpspi2grp { 1073 pinctrl_lpspi2: lpspi2grp {
1061 fsl,pins = <IMX8QM_SPI2_SCK_D 1074 fsl,pins = <IMX8QM_SPI2_SCK_DMA_SPI2_SCK 0x0600004c>,
1062 <IMX8QM_SPI2_SDO_D 1075 <IMX8QM_SPI2_SDO_DMA_SPI2_SDO 0x0600004c>,
1063 <IMX8QM_SPI2_SDI_D 1076 <IMX8QM_SPI2_SDI_DMA_SPI2_SDI 0x0600004c>,
1064 <IMX8QM_SPI2_CS0_L 1077 <IMX8QM_SPI2_CS0_LSIO_GPIO3_IO10 0x0600004c>;
1065 }; 1078 };
1066 1079
1067 /* Apalis UART3 */ 1080 /* Apalis UART3 */
1068 pinctrl_lpuart0: lpuart0grp { 1081 pinctrl_lpuart0: lpuart0grp {
1069 fsl,pins = <IMX8QM_UART0_RX_D 1082 fsl,pins = <IMX8QM_UART0_RX_DMA_UART0_RX 0x06000020>,
1070 <IMX8QM_UART0_TX_D 1083 <IMX8QM_UART0_TX_DMA_UART0_TX 0x06000020>;
1071 }; 1084 };
1072 1085
1073 /* Apalis UART1 */ 1086 /* Apalis UART1 */
1074 pinctrl_lpuart1: lpuart1grp { 1087 pinctrl_lpuart1: lpuart1grp {
1075 fsl,pins = <IMX8QM_UART1_RX_D 1088 fsl,pins = <IMX8QM_UART1_RX_DMA_UART1_RX 0x06000020>,
1076 <IMX8QM_UART1_TX_D 1089 <IMX8QM_UART1_TX_DMA_UART1_TX 0x06000020>,
1077 <IMX8QM_UART1_CTS_ 1090 <IMX8QM_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020>,
1078 <IMX8QM_UART1_RTS_ 1091 <IMX8QM_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020>;
1079 }; 1092 };
1080 1093
1081 /* Apalis UART1 */ 1094 /* Apalis UART1 */
1082 pinctrl_lpuart1ctrl: lpuart1ctrlgrp { 1095 pinctrl_lpuart1ctrl: lpuart1ctrlgrp {
1083 fsl,pins = /* Apalis UART1_DT 1096 fsl,pins = /* Apalis UART1_DTR */
1084 <IMX8QM_M40_I2C0_S 1097 <IMX8QM_M40_I2C0_SCL_LSIO_GPIO0_IO06 0x00000021>,
1085 /* Apalis UART1_DS 1098 /* Apalis UART1_DSR */
1086 <IMX8QM_M40_I2C0_S 1099 <IMX8QM_M40_I2C0_SDA_LSIO_GPIO0_IO07 0x00000021>,
1087 /* Apalis UART1_DC 1100 /* Apalis UART1_DCD */
1088 <IMX8QM_M41_I2C0_S 1101 <IMX8QM_M41_I2C0_SCL_LSIO_GPIO0_IO10 0x00000021>,
1089 /* Apalis UART1_RI 1102 /* Apalis UART1_RI */
1090 <IMX8QM_M41_I2C0_S 1103 <IMX8QM_M41_I2C0_SDA_LSIO_GPIO0_IO11 0x00000021>;
1091 }; 1104 };
1092 1105
1093 /* Apalis UART4 */ 1106 /* Apalis UART4 */
1094 pinctrl_lpuart2: lpuart2grp { 1107 pinctrl_lpuart2: lpuart2grp {
1095 fsl,pins = <IMX8QM_LVDS0_I2C1 1108 fsl,pins = <IMX8QM_LVDS0_I2C1_SCL_DMA_UART2_TX 0x06000020>,
1096 <IMX8QM_LVDS0_I2C1 1109 <IMX8QM_LVDS0_I2C1_SDA_DMA_UART2_RX 0x06000020>;
1097 }; 1110 };
1098 1111
1099 /* Apalis UART2 */ 1112 /* Apalis UART2 */
1100 pinctrl_lpuart3: lpuart3grp { 1113 pinctrl_lpuart3: lpuart3grp {
1101 fsl,pins = <IMX8QM_LVDS1_I2C1 1114 fsl,pins = <IMX8QM_LVDS1_I2C1_SCL_DMA_UART3_TX 0x06000020>,
1102 <IMX8QM_LVDS1_I2C1 1115 <IMX8QM_LVDS1_I2C1_SDA_DMA_UART3_RX 0x06000020>,
1103 <IMX8QM_ENET1_RGMI 1116 <IMX8QM_ENET1_RGMII_TXD3_DMA_UART3_RTS_B 0x06000020>,
1104 <IMX8QM_ENET1_RGMI 1117 <IMX8QM_ENET1_RGMII_RXC_DMA_UART3_CTS_B 0x06000020>;
1105 }; 1118 };
1106 1119
1107 /* Apalis TS_2 */ 1120 /* Apalis TS_2 */
1108 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpi 1121 pinctrl_lvds0_i2c0_gpio: lvds0i2c0gpiogrp {
1109 fsl,pins = <IMX8QM_LVDS0_I2C0 1122 fsl,pins = <IMX8QM_LVDS0_I2C0_SCL_LSIO_GPIO1_IO06 0x00000021>;
1110 }; 1123 };
1111 1124
1112 /* Apalis LCD1_G6+7 */ 1125 /* Apalis LCD1_G6+7 */
1113 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gp 1126 pinctrl_lvds1_i2c0_gpios: lvds1i2c0gpiosgrp {
1114 fsl,pins = /* Apalis LCD1_G6 1127 fsl,pins = /* Apalis LCD1_G6 */
1115 <IMX8QM_LVDS1_I2C0 1128 <IMX8QM_LVDS1_I2C0_SCL_LSIO_GPIO1_IO12 0x00000021>,
1116 /* Apalis LCD1_G7 1129 /* Apalis LCD1_G7 */
1117 <IMX8QM_LVDS1_I2C0 1130 <IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x00000021>;
1118 }; 1131 };
1119 1132
1120 /* Apalis TS_3 */ 1133 /* Apalis TS_3 */
1121 pinctrl_mipi_dsi_0_1_en: mipidsi0-1en 1134 pinctrl_mipi_dsi_0_1_en: mipidsi0-1engrp {
1122 fsl,pins = <IMX8QM_LVDS0_I2C0 1135 fsl,pins = <IMX8QM_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021>;
1123 }; 1136 };
1124 1137
1125 /* Apalis TS_4 */ 1138 /* Apalis TS_4 */
1126 pinctrl_mipi_dsi1_gpios: mipidsi1gpio 1139 pinctrl_mipi_dsi1_gpios: mipidsi1gpiosgrp {
1127 fsl,pins = <IMX8QM_MIPI_DSI1_ 1140 fsl,pins = <IMX8QM_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO22 0x00000021>;
1128 }; 1141 };
1129 1142
1130 /* Apalis TS_1 */ 1143 /* Apalis TS_1 */
1131 pinctrl_mlb_gpios: mlbgpiosgrp { 1144 pinctrl_mlb_gpios: mlbgpiosgrp {
1132 fsl,pins = <IMX8QM_MLB_CLK_LS 1145 fsl,pins = <IMX8QM_MLB_CLK_LSIO_GPIO3_IO27 0x00000021>;
1133 }; 1146 };
1134 1147
1135 /* Apalis MMC1_CD# */ 1148 /* Apalis MMC1_CD# */
1136 pinctrl_mmc1_cd: mmc1cdgrp { 1149 pinctrl_mmc1_cd: mmc1cdgrp {
1137 fsl,pins = <IMX8QM_ESAI1_TX1_ 1150 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021>;
1138 }; 1151 };
1139 1152
1140 pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp 1153 pinctrl_mmc1_cd_sleep: mmc1cdsleepgrp {
1141 fsl,pins = <IMX8QM_ESAI1_TX1_ 1154 fsl,pins = <IMX8QM_ESAI1_TX1_LSIO_GPIO2_IO09 0x04000021>;
1142 }; 1155 };
1143 1156
1144 /* On-module PCIe_Wi-Fi */ 1157 /* On-module PCIe_Wi-Fi */
1145 pinctrl_pcieb: pciebgrp { 1158 pinctrl_pcieb: pciebgrp {
1146 fsl,pins = <IMX8QM_PCIE_CTRL1 1159 fsl,pins = <IMX8QM_PCIE_CTRL1_CLKREQ_B_LSIO_GPIO4_IO30 0x00000021>,
1147 <IMX8QM_PCIE_CTRL1 1160 <IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x00000021>,
1148 <IMX8QM_PCIE_CTRL1 1161 <IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x00000021>;
1149 }; 1162 };
1150 1163
1151 /* On-module PCIe_CLK_EN1 */ 1164 /* On-module PCIe_CLK_EN1 */
1152 pinctrl_pcie_sata_refclk: pciesataref 1165 pinctrl_pcie_sata_refclk: pciesatarefclkgrp {
1153 fsl,pins = <IMX8QM_USDHC2_WP_ 1166 fsl,pins = <IMX8QM_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021>;
1154 }; 1167 };
1155 1168
1156 /* On-module PCIe_CLK_EN2 */ 1169 /* On-module PCIe_CLK_EN2 */
1157 pinctrl_pcie_wifi_refclk: pciewifiref 1170 pinctrl_pcie_wifi_refclk: pciewifirefclkgrp {
1158 fsl,pins = <IMX8QM_ESAI1_TX3_ 1171 fsl,pins = <IMX8QM_ESAI1_TX3_RX2_LSIO_GPIO2_IO11 0x00000021>;
1159 }; 1172 };
1160 1173
1161 /* Apalis PWM3 */ 1174 /* Apalis PWM3 */
1162 pinctrl_pwm0: pwm0grp { 1175 pinctrl_pwm0: pwm0grp {
1163 fsl,pins = <IMX8QM_UART0_RTS_ 1176 fsl,pins = <IMX8QM_UART0_RTS_B_LSIO_PWM0_OUT 0x00000020>;
1164 }; 1177 };
1165 1178
1166 /* Apalis PWM4 */ 1179 /* Apalis PWM4 */
1167 pinctrl_pwm1: pwm1grp { 1180 pinctrl_pwm1: pwm1grp {
1168 fsl,pins = <IMX8QM_UART0_CTS_ 1181 fsl,pins = <IMX8QM_UART0_CTS_B_LSIO_PWM1_OUT 0x00000020>;
1169 }; 1182 };
1170 1183
1171 /* Apalis PWM1 */ 1184 /* Apalis PWM1 */
1172 pinctrl_pwm2: pwm2grp { 1185 pinctrl_pwm2: pwm2grp {
1173 fsl,pins = <IMX8QM_GPT1_COMPA 1186 fsl,pins = <IMX8QM_GPT1_COMPARE_LSIO_PWM2_OUT 0x00000020>;
1174 }; 1187 };
1175 1188
1176 /* Apalis PWM2 */ 1189 /* Apalis PWM2 */
1177 pinctrl_pwm3: pwm3grp { 1190 pinctrl_pwm3: pwm3grp {
1178 fsl,pins = <IMX8QM_GPT0_COMPA 1191 fsl,pins = <IMX8QM_GPT0_COMPARE_LSIO_PWM3_OUT 0x00000020>;
1179 }; 1192 };
1180 1193
1181 /* Apalis BKL1_PWM */ 1194 /* Apalis BKL1_PWM */
1182 pinctrl_pwm_bkl: pwmbklgrp { 1195 pinctrl_pwm_bkl: pwmbklgrp {
1183 fsl,pins = <IMX8QM_LVDS1_GPIO 1196 fsl,pins = <IMX8QM_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020>;
1184 }; 1197 };
1185 1198
1186 /* Apalis LCD1_ */ 1199 /* Apalis LCD1_ */
1187 pinctrl_qspi1a_gpios: qspi1agpiosgrp 1200 pinctrl_qspi1a_gpios: qspi1agpiosgrp {
1188 fsl,pins = /* Apalis LCD1_B0 1201 fsl,pins = /* Apalis LCD1_B0 */
1189 <IMX8QM_QSPI1A_DAT 1202 <IMX8QM_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021>,
1190 /* Apalis LCD1_B1 1203 /* Apalis LCD1_B1 */
1191 <IMX8QM_QSPI1A_DAT 1204 <IMX8QM_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x00000021>,
1192 /* Apalis LCD1_B2 1205 /* Apalis LCD1_B2 */
1193 <IMX8QM_QSPI1A_DAT 1206 <IMX8QM_QSPI1A_DATA2_LSIO_GPIO4_IO24 0x00000021>,
1194 /* Apalis LCD1_B3 1207 /* Apalis LCD1_B3 */
1195 <IMX8QM_QSPI1A_DAT 1208 <IMX8QM_QSPI1A_DATA3_LSIO_GPIO4_IO23 0x00000021>,
1196 /* Apalis LCD1_B5 1209 /* Apalis LCD1_B5 */
1197 <IMX8QM_QSPI1A_DQS 1210 <IMX8QM_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021>,
1198 /* Apalis LCD1_B7 1211 /* Apalis LCD1_B7 */
1199 <IMX8QM_QSPI1A_SCL 1212 <IMX8QM_QSPI1A_SCLK_LSIO_GPIO4_IO21 0x00000021>,
1200 /* Apalis LCD1_B4 1213 /* Apalis LCD1_B4 */
1201 <IMX8QM_QSPI1A_SS0 1214 <IMX8QM_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x00000021>,
1202 /* Apalis LCD1_B6 1215 /* Apalis LCD1_B6 */
1203 <IMX8QM_QSPI1A_SS1 1216 <IMX8QM_QSPI1A_SS1_B_LSIO_GPIO4_IO20 0x00000021>;
1204 }; 1217 };
1205 1218
1206 /* On-module RESET_MOCI#_DRV */ 1219 /* On-module RESET_MOCI#_DRV */
1207 pinctrl_reset_moci: resetmocigrp { 1220 pinctrl_reset_moci: resetmocigrp {
1208 fsl,pins = <IMX8QM_SCU_GPIO0_ 1221 fsl,pins = <IMX8QM_SCU_GPIO0_02_LSIO_GPIO0_IO30 0x00000021>;
1209 }; 1222 };
1210 1223
1211 /* On-module I2S SGTL5000 for Apalis 1224 /* On-module I2S SGTL5000 for Apalis Analogue Audio */
1212 pinctrl_sai1: sai1grp { 1225 pinctrl_sai1: sai1grp {
1213 fsl,pins = <IMX8QM_SAI1_TXD_A 1226 fsl,pins = <IMX8QM_SAI1_TXD_AUD_SAI1_TXD 0xc600006c>,
1214 <IMX8QM_SAI1_RXD_A 1227 <IMX8QM_SAI1_RXD_AUD_SAI1_RXD 0xc600004c>,
1215 <IMX8QM_SAI1_TXC_A 1228 <IMX8QM_SAI1_TXC_AUD_SAI1_TXC 0xc600004c>,
1216 <IMX8QM_SAI1_TXFS_ 1229 <IMX8QM_SAI1_TXFS_AUD_SAI1_TXFS 0xc600004c>;
1217 }; 1230 };
1218 1231
1219 /* Apalis SATA1_ACT# */ 1232 /* Apalis SATA1_ACT# */
1220 pinctrl_sata1_act: sata1actgrp { 1233 pinctrl_sata1_act: sata1actgrp {
1221 fsl,pins = <IMX8QM_ESAI1_TX0_ 1234 fsl,pins = <IMX8QM_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021>;
1222 }; 1235 };
1223 1236
1224 /* Apalis SD1_CD# */ 1237 /* Apalis SD1_CD# */
1225 pinctrl_sd1_cd: sd1cdgrp { 1238 pinctrl_sd1_cd: sd1cdgrp {
1226 fsl,pins = <IMX8QM_USDHC2_CD_ 1239 fsl,pins = <IMX8QM_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021>;
1227 }; 1240 };
1228 1241
1229 /* On-module I2S SGTL5000 SYS_MCLK */ 1242 /* On-module I2S SGTL5000 SYS_MCLK */
1230 pinctrl_sgtl5000: sgtl5000grp { 1243 pinctrl_sgtl5000: sgtl5000grp {
1231 fsl,pins = <IMX8QM_MCLK_OUT0_ 1244 fsl,pins = <IMX8QM_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0xc600004c>;
1232 }; 1245 };
1233 1246
1234 /* Apalis LCD1_ */ 1247 /* Apalis LCD1_ */
1235 pinctrl_sim0_gpios: sim0gpiosgrp { 1248 pinctrl_sim0_gpios: sim0gpiosgrp {
1236 fsl,pins = /* Apalis LCD1_G5 1249 fsl,pins = /* Apalis LCD1_G5 */
1237 <IMX8QM_SIM0_CLK_L 1250 <IMX8QM_SIM0_CLK_LSIO_GPIO0_IO00 0x00000021>,
1238 /* Apalis LCD1_G3 1251 /* Apalis LCD1_G3 */
1239 <IMX8QM_SIM0_GPIO0 1252 <IMX8QM_SIM0_GPIO0_00_LSIO_GPIO0_IO05 0x00000021>,
1240 /* Apalis TS_5 */ 1253 /* Apalis TS_5 */
1241 <IMX8QM_SIM0_IO_LS 1254 <IMX8QM_SIM0_IO_LSIO_GPIO0_IO02 0x00000021>,
1242 /* Apalis LCD1_G4 1255 /* Apalis LCD1_G4 */
1243 <IMX8QM_SIM0_RST_L 1256 <IMX8QM_SIM0_RST_LSIO_GPIO0_IO01 0x00000021>;
1244 }; 1257 };
1245 1258
1246 /* Apalis SPDIF */ 1259 /* Apalis SPDIF */
1247 pinctrl_spdif0: spdif0grp { 1260 pinctrl_spdif0: spdif0grp {
1248 fsl,pins = <IMX8QM_SPDIF0_TX_ 1261 fsl,pins = <IMX8QM_SPDIF0_TX_AUD_SPDIF0_TX 0xc6000040>,
1249 <IMX8QM_SPDIF0_RX_ 1262 <IMX8QM_SPDIF0_RX_AUD_SPDIF0_RX 0xc6000040>;
1250 }; 1263 };
1251 1264
1252 pinctrl_touchctrl_gpios: touchctrlgpi 1265 pinctrl_touchctrl_gpios: touchctrlgpiosgrp {
1253 fsl,pins = <IMX8QM_ESAI1_FSR_ 1266 fsl,pins = <IMX8QM_ESAI1_FSR_LSIO_GPIO2_IO04 0x00000021>,
1254 <IMX8QM_ESAI1_FST_ 1267 <IMX8QM_ESAI1_FST_LSIO_GPIO2_IO05 0x00000041>,
1255 <IMX8QM_SPI3_SCK_L 1268 <IMX8QM_SPI3_SCK_LSIO_GPIO2_IO17 0x00000021>,
1256 <IMX8QM_SPI3_CS1_L 1269 <IMX8QM_SPI3_CS1_LSIO_GPIO2_IO21 0x00000041>;
1257 }; 1270 };
1258 1271
1259 pinctrl_touchctrl_idle: touchctrlidle 1272 pinctrl_touchctrl_idle: touchctrlidlegrp {
1260 fsl,pins = <IMX8QM_ADC_IN4_LS 1273 fsl,pins = <IMX8QM_ADC_IN4_LSIO_GPIO3_IO22 0x00000021>,
1261 <IMX8QM_ADC_IN5_LS 1274 <IMX8QM_ADC_IN5_LSIO_GPIO3_IO23 0x00000021>,
1262 <IMX8QM_ADC_IN6_LS 1275 <IMX8QM_ADC_IN6_LSIO_GPIO3_IO24 0x00000021>,
1263 <IMX8QM_ADC_IN7_LS 1276 <IMX8QM_ADC_IN7_LSIO_GPIO3_IO25 0x00000021>;
1264 }; 1277 };
1265 1278
1266 /* On-module USB HSIC HUB (active) */ 1279 /* On-module USB HSIC HUB (active) */
1267 pinctrl_usb_hsic_active: usbh1activeg 1280 pinctrl_usb_hsic_active: usbh1activegrp {
1268 fsl,pins = <IMX8QM_USB_HSIC0_ 1281 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>,
1269 <IMX8QM_USB_HSIC0_ 1282 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000ff>;
1270 }; 1283 };
1271 1284
1272 /* On-module USB HSIC HUB (idle) */ 1285 /* On-module USB HSIC HUB (idle) */
1273 pinctrl_usb_hsic_idle: usbh1idlegrp { 1286 pinctrl_usb_hsic_idle: usbh1idlegrp {
1274 fsl,pins = <IMX8QM_USB_HSIC0_ 1287 fsl,pins = <IMX8QM_USB_HSIC0_DATA_CONN_USB_HSIC0_DATA 0x000000cf>,
1275 <IMX8QM_USB_HSIC0_ 1288 <IMX8QM_USB_HSIC0_STROBE_CONN_USB_HSIC0_STROBE 0x000000cf>;
1276 }; 1289 };
1277 1290
1278 /* On-module USB HSIC HUB */ 1291 /* On-module USB HSIC HUB */
1279 pinctrl_usb3503a: usb3503agrp { 1292 pinctrl_usb3503a: usb3503agrp {
1280 fsl,pins = /* On-module HSIC_ 1293 fsl,pins = /* On-module HSIC_HUB_CONNECT */
1281 <IMX8QM_SCU_GPIO0_ 1294 <IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x00000041>,
1282 /* On-module HSIC_ 1295 /* On-module HSIC_INT_N */
1283 <IMX8QM_SCU_GPIO0_ 1296 <IMX8QM_SCU_GPIO0_05_LSIO_GPIO1_IO01 0x00000021>,
1284 /* On-module HSIC_ 1297 /* On-module HSIC_RESET_N */
1285 <IMX8QM_SCU_GPIO0_ 1298 <IMX8QM_SCU_GPIO0_06_LSIO_GPIO1_IO02 0x00000041>;
1286 }; 1299 };
1287 1300
1288 /* Apalis USBH_EN */ 1301 /* Apalis USBH_EN */
1289 pinctrl_usbh_en: usbhengrp { 1302 pinctrl_usbh_en: usbhengrp {
1290 fsl,pins = <IMX8QM_USB_SS3_TC 1303 fsl,pins = <IMX8QM_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021>;
1291 }; 1304 };
1292 1305
1293 /* Apalis USBO1 */ 1306 /* Apalis USBO1 */
1294 pinctrl_usbotg1: usbotg1grp { 1307 pinctrl_usbotg1: usbotg1grp {
1295 fsl,pins = /* Apalis USBO1_EN 1308 fsl,pins = /* Apalis USBO1_EN */
1296 <IMX8QM_USB_SS3_TC 1309 <IMX8QM_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021>,
1297 /* Apalis USBO1_OC 1310 /* Apalis USBO1_OC# */
1298 <IMX8QM_USB_SS3_TC 1311 <IMX8QM_USB_SS3_TC2_CONN_USB_OTG1_OC 0x04000021>;
1299 }; 1312 };
1300 1313
1301 /* On-module eMMC */ 1314 /* On-module eMMC */
1302 pinctrl_usdhc1: usdhc1grp { 1315 pinctrl_usdhc1: usdhc1grp {
1303 fsl,pins = <IMX8QM_EMMC0_CLK_ 1316 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
1304 <IMX8QM_EMMC0_CMD_ 1317 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021>,
1305 <IMX8QM_EMMC0_DATA 1318 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021>,
1306 <IMX8QM_EMMC0_DATA 1319 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021>,
1307 <IMX8QM_EMMC0_DATA 1320 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021>,
1308 <IMX8QM_EMMC0_DATA 1321 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021>,
1309 <IMX8QM_EMMC0_DATA 1322 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021>,
1310 <IMX8QM_EMMC0_DATA 1323 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021>,
1311 <IMX8QM_EMMC0_DATA 1324 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021>,
1312 <IMX8QM_EMMC0_DATA 1325 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021>,
1313 <IMX8QM_EMMC0_STRO 1326 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041>,
1314 <IMX8QM_EMMC0_RESE 1327 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021>;
1315 }; 1328 };
1316 1329
1317 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1330 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1318 fsl,pins = <IMX8QM_EMMC0_CLK_ 1331 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
1319 <IMX8QM_EMMC0_CMD_ 1332 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>,
1320 <IMX8QM_EMMC0_DATA 1333 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>,
1321 <IMX8QM_EMMC0_DATA 1334 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>,
1322 <IMX8QM_EMMC0_DATA 1335 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>,
1323 <IMX8QM_EMMC0_DATA 1336 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>,
1324 <IMX8QM_EMMC0_DATA 1337 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>,
1325 <IMX8QM_EMMC0_DATA 1338 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>,
1326 <IMX8QM_EMMC0_DATA 1339 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>,
1327 <IMX8QM_EMMC0_DATA 1340 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>,
1328 <IMX8QM_EMMC0_STRO 1341 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>,
1329 <IMX8QM_EMMC0_RESE 1342 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>;
1330 }; 1343 };
1331 1344
1332 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1345 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1333 fsl,pins = <IMX8QM_EMMC0_CLK_ 1346 fsl,pins = <IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040>,
1334 <IMX8QM_EMMC0_CMD_ 1347 <IMX8QM_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020>,
1335 <IMX8QM_EMMC0_DATA 1348 <IMX8QM_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020>,
1336 <IMX8QM_EMMC0_DATA 1349 <IMX8QM_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020>,
1337 <IMX8QM_EMMC0_DATA 1350 <IMX8QM_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020>,
1338 <IMX8QM_EMMC0_DATA 1351 <IMX8QM_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020>,
1339 <IMX8QM_EMMC0_DATA 1352 <IMX8QM_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020>,
1340 <IMX8QM_EMMC0_DATA 1353 <IMX8QM_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020>,
1341 <IMX8QM_EMMC0_DATA 1354 <IMX8QM_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020>,
1342 <IMX8QM_EMMC0_DATA 1355 <IMX8QM_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020>,
1343 <IMX8QM_EMMC0_STRO 1356 <IMX8QM_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040>,
1344 <IMX8QM_EMMC0_RESE 1357 <IMX8QM_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020>;
1345 }; 1358 };
1346 1359
1347 /* Apalis TS_6 */ 1360 /* Apalis TS_6 */
1348 pinctrl_usdhc1_gpios: usdhc1gpiosgrp 1361 pinctrl_usdhc1_gpios: usdhc1gpiosgrp {
1349 fsl,pins = <IMX8QM_USDHC1_STR 1362 fsl,pins = <IMX8QM_USDHC1_STROBE_LSIO_GPIO5_IO23 0x00000021>;
1350 }; 1363 };
1351 1364
1352 /* Apalis MMC1 */ 1365 /* Apalis MMC1 */
1353 pinctrl_usdhc2_4bit: usdhc2grp4bitgrp 1366 pinctrl_usdhc2_4bit: usdhc2grp4bitgrp {
1354 fsl,pins = <IMX8QM_USDHC1_CLK 1367 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>,
1355 <IMX8QM_USDHC1_CMD 1368 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021>,
1356 <IMX8QM_USDHC1_DAT 1369 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021>,
1357 <IMX8QM_USDHC1_DAT 1370 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021>,
1358 <IMX8QM_USDHC1_DAT 1371 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021>,
1359 <IMX8QM_USDHC1_DAT 1372 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021>,
1360 /* On-module PMIC 1373 /* On-module PMIC use */
1361 <IMX8QM_USDHC1_VSE 1374 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1362 }; 1375 };
1363 1376
1364 pinctrl_usdhc2_4bit_100mhz: usdhc2-4b 1377 pinctrl_usdhc2_4bit_100mhz: usdhc2-4bit100mhzgrp {
1365 fsl,pins = <IMX8QM_USDHC1_CLK 1378 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
1366 <IMX8QM_USDHC1_CMD 1379 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
1367 <IMX8QM_USDHC1_DAT 1380 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
1368 <IMX8QM_USDHC1_DAT 1381 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
1369 <IMX8QM_USDHC1_DAT 1382 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
1370 <IMX8QM_USDHC1_DAT 1383 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
1371 /* On-module PMIC 1384 /* On-module PMIC use */
1372 <IMX8QM_USDHC1_VSE 1385 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1373 }; 1386 };
1374 1387
1375 pinctrl_usdhc2_4bit_200mhz: usdhc2-4b 1388 pinctrl_usdhc2_4bit_200mhz: usdhc2-4bit200mhzgrp {
1376 fsl,pins = <IMX8QM_USDHC1_CLK 1389 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040>,
1377 <IMX8QM_USDHC1_CMD 1390 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020>,
1378 <IMX8QM_USDHC1_DAT 1391 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020>,
1379 <IMX8QM_USDHC1_DAT 1392 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020>,
1380 <IMX8QM_USDHC1_DAT 1393 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020>,
1381 <IMX8QM_USDHC1_DAT 1394 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020>,
1382 /* On-module PMIC 1395 /* On-module PMIC use */
1383 <IMX8QM_USDHC1_VSE 1396 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1384 }; 1397 };
1385 1398
1386 pinctrl_usdhc2_8bit: usdhc2grp8bitgrp 1399 pinctrl_usdhc2_8bit: usdhc2grp8bitgrp {
1387 fsl,pins = <IMX8QM_USDHC1_DAT 1400 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000021>,
1388 <IMX8QM_USDHC1_DAT 1401 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000021>,
1389 <IMX8QM_USDHC1_DAT 1402 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000021>,
1390 <IMX8QM_USDHC1_DAT 1403 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000021>;
1391 }; 1404 };
1392 1405
1393 pinctrl_usdhc2_8bit_100mhz: usdhc2-8b 1406 pinctrl_usdhc2_8bit_100mhz: usdhc2-8bit100mhzgrp {
1394 fsl,pins = <IMX8QM_USDHC1_DAT 1407 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>,
1395 <IMX8QM_USDHC1_DAT 1408 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>,
1396 <IMX8QM_USDHC1_DAT 1409 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>,
1397 <IMX8QM_USDHC1_DAT 1410 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>;
1398 }; 1411 };
1399 1412
1400 pinctrl_usdhc2_8bit_200mhz: usdhc2-8b 1413 pinctrl_usdhc2_8bit_200mhz: usdhc2-8bit200mhzgrp {
1401 fsl,pins = <IMX8QM_USDHC1_DAT 1414 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x00000020>,
1402 <IMX8QM_USDHC1_DAT 1415 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x00000020>,
1403 <IMX8QM_USDHC1_DAT 1416 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x00000020>,
1404 <IMX8QM_USDHC1_DAT 1417 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x00000020>;
1405 }; 1418 };
1406 1419
1407 pinctrl_usdhc2_4bit_sleep: usdhc2-4bi 1420 pinctrl_usdhc2_4bit_sleep: usdhc2-4bitsleepgrp {
1408 fsl,pins = <IMX8QM_USDHC1_CLK 1421 fsl,pins = <IMX8QM_USDHC1_CLK_CONN_USDHC1_CLK 0x04000061>,
1409 <IMX8QM_USDHC1_CMD 1422 <IMX8QM_USDHC1_CMD_CONN_USDHC1_CMD 0x04000061>,
1410 <IMX8QM_USDHC1_DAT 1423 <IMX8QM_USDHC1_DATA0_CONN_USDHC1_DATA0 0x04000061>,
1411 <IMX8QM_USDHC1_DAT 1424 <IMX8QM_USDHC1_DATA1_CONN_USDHC1_DATA1 0x04000061>,
1412 <IMX8QM_USDHC1_DAT 1425 <IMX8QM_USDHC1_DATA2_CONN_USDHC1_DATA2 0x04000061>,
1413 <IMX8QM_USDHC1_DAT 1426 <IMX8QM_USDHC1_DATA3_CONN_USDHC1_DATA3 0x04000061>,
1414 /* On-module PMIC 1427 /* On-module PMIC use */
1415 <IMX8QM_USDHC1_VSE 1428 <IMX8QM_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021>;
1416 }; 1429 };
1417 1430
1418 pinctrl_usdhc2_8bit_sleep: usdhc2-8bi 1431 pinctrl_usdhc2_8bit_sleep: usdhc2-8bitsleepgrp {
1419 fsl,pins = <IMX8QM_USDHC1_DAT 1432 fsl,pins = <IMX8QM_USDHC1_DATA4_CONN_USDHC1_DATA4 0x04000061>,
1420 <IMX8QM_USDHC1_DAT 1433 <IMX8QM_USDHC1_DATA5_CONN_USDHC1_DATA5 0x04000061>,
1421 <IMX8QM_USDHC1_DAT 1434 <IMX8QM_USDHC1_DATA6_CONN_USDHC1_DATA6 0x04000061>,
1422 <IMX8QM_USDHC1_DAT 1435 <IMX8QM_USDHC1_DATA7_CONN_USDHC1_DATA7 0x04000061>;
1423 }; 1436 };
1424 1437
1425 /* Apalis SD1 */ 1438 /* Apalis SD1 */
1426 pinctrl_usdhc3: usdhc3grp { 1439 pinctrl_usdhc3: usdhc3grp {
1427 fsl,pins = <IMX8QM_USDHC2_CLK 1440 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1428 <IMX8QM_USDHC2_CMD 1441 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1429 <IMX8QM_USDHC2_DAT 1442 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1430 <IMX8QM_USDHC2_DAT 1443 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1431 <IMX8QM_USDHC2_DAT 1444 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1432 <IMX8QM_USDHC2_DAT 1445 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1433 /* On-module PMIC 1446 /* On-module PMIC use */
1434 <IMX8QM_USDHC2_VSE 1447 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1435 }; 1448 };
1436 1449
1437 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1450 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1438 fsl,pins = <IMX8QM_USDHC2_CLK 1451 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1439 <IMX8QM_USDHC2_CMD 1452 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1440 <IMX8QM_USDHC2_DAT 1453 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1441 <IMX8QM_USDHC2_DAT 1454 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1442 <IMX8QM_USDHC2_DAT 1455 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1443 <IMX8QM_USDHC2_DAT 1456 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1444 /* On-module PMIC 1457 /* On-module PMIC use */
1445 <IMX8QM_USDHC2_VSE 1458 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1446 }; 1459 };
1447 1460
1448 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1461 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1449 fsl,pins = <IMX8QM_USDHC2_CLK 1462 fsl,pins = <IMX8QM_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041>,
1450 <IMX8QM_USDHC2_CMD 1463 <IMX8QM_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021>,
1451 <IMX8QM_USDHC2_DAT 1464 <IMX8QM_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021>,
1452 <IMX8QM_USDHC2_DAT 1465 <IMX8QM_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021>,
1453 <IMX8QM_USDHC2_DAT 1466 <IMX8QM_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021>,
1454 <IMX8QM_USDHC2_DAT 1467 <IMX8QM_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021>,
1455 /* On-module PMIC 1468 /* On-module PMIC use */
1456 <IMX8QM_USDHC2_VSE 1469 <IMX8QM_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021>;
1457 }; 1470 };
1458 1471
1459 /* On-module Wi-Fi */ 1472 /* On-module Wi-Fi */
1460 pinctrl_wifi: wifigrp { 1473 pinctrl_wifi: wifigrp {
1461 fsl,pins = /* On-module Wi-Fi 1474 fsl,pins = /* On-module Wi-Fi_SUSCLK_32k */
1462 <IMX8QM_SCU_GPIO0_ 1475 <IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x06000021>,
1463 /* On-module Wi-Fi 1476 /* On-module Wi-Fi_PCIE_W_DISABLE */
1464 <IMX8QM_MIPI_CSI0_ 1477 <IMX8QM_MIPI_CSI0_MCLK_OUT_LSIO_GPIO1_IO24 0x06000021>;
1465 }; 1478 };
1466 1479
1467 pinctrl_wifi_pdn: wifipdngrp { 1480 pinctrl_wifi_pdn: wifipdngrp {
1468 fsl,pins = /* On-module Wi-Fi 1481 fsl,pins = /* On-module Wi-Fi_POWER_DOWN */
1469 <IMX8QM_MIPI_CSI0_ 1482 <IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0x06000021>;
1470 }; 1483 };
1471 }; 1484 };
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