1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/imx8-lpcg.h> 7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/firmware/imx/rsrc.h>
9 9
10 conn_axi_clk: clock-conn-axi { <<
11 compatible = "fixed-clock"; <<
12 #clock-cells = <0>; <<
13 clock-frequency = <333333333>; <<
14 clock-output-names = "conn_axi_clk"; <<
15 }; <<
16 <<
17 conn_ahb_clk: clock-conn-ahb { <<
18 compatible = "fixed-clock"; <<
19 #clock-cells = <0>; <<
20 clock-frequency = <166666666>; <<
21 clock-output-names = "conn_ahb_clk"; <<
22 }; <<
23 <<
24 conn_ipg_clk: clock-conn-ipg { <<
25 compatible = "fixed-clock"; <<
26 #clock-cells = <0>; <<
27 clock-frequency = <83333333>; <<
28 clock-output-names = "conn_ipg_clk"; <<
29 }; <<
30 <<
31 conn_bch_clk: clock-conn-bch { <<
32 compatible = "fixed-clock"; <<
33 #clock-cells = <0>; <<
34 clock-frequency = <400000000>; <<
35 clock-output-names = "conn_bch_clk"; <<
36 }; <<
37 <<
38 conn_subsys: bus@5b000000 { 10 conn_subsys: bus@5b000000 {
39 compatible = "simple-bus"; 11 compatible = "simple-bus";
40 #address-cells = <1>; 12 #address-cells = <1>;
41 #size-cells = <1>; 13 #size-cells = <1>;
42 ranges = <0x5b000000 0x0 0x5b000000 0x 14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
43 15
44 usbotg1: usb@5b0d0000 { !! 16 conn_axi_clk: clock-conn-axi {
45 compatible = "fsl,imx7ulp-usb" !! 17 compatible = "fixed-clock";
46 reg = <0x5b0d0000 0x200>; !! 18 #clock-cells = <0>;
47 interrupt-parent = <&gic>; !! 19 clock-frequency = <333333333>;
48 interrupts = <GIC_SPI 267 IRQ_ !! 20 clock-output-names = "conn_axi_clk";
49 fsl,usbphy = <&usbphy1>; !! 21 };
50 fsl,usbmisc = <&usbmisc1 0>; !! 22
51 clocks = <&usb2_lpcg IMX_LPCG_ !! 23 conn_ahb_clk: clock-conn-ahb {
52 ahb-burst-config = <0x0>; !! 24 compatible = "fixed-clock";
53 tx-burst-size-dword = <0x10>; !! 25 #clock-cells = <0>;
54 rx-burst-size-dword = <0x10>; !! 26 clock-frequency = <166666666>;
55 power-domains = <&pd IMX_SC_R_ !! 27 clock-output-names = "conn_ahb_clk";
56 status = "disabled"; !! 28 };
57 }; !! 29
58 !! 30 conn_ipg_clk: clock-conn-ipg {
59 usbmisc1: usbmisc@5b0d0200 { !! 31 compatible = "fixed-clock";
60 #index-cells = <1>; !! 32 #clock-cells = <0>;
61 compatible = "fsl,imx7ulp-usbm !! 33 clock-frequency = <83333333>;
62 reg = <0x5b0d0200 0x200>; !! 34 clock-output-names = "conn_ipg_clk";
63 }; <<
64 <<
65 usbphy1: usbphy@5b100000 { <<
66 compatible = "fsl,imx7ulp-usbp <<
67 reg = <0x5b100000 0x1000>; <<
68 clocks = <&usb2_lpcg IMX_LPCG_ <<
69 power-domains = <&pd IMX_SC_R_ <<
70 status = "disabled"; <<
71 }; 35 };
72 36
73 usdhc1: mmc@5b010000 { 37 usdhc1: mmc@5b010000 {
74 interrupts = <GIC_SPI 232 IRQ_ 38 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
75 reg = <0x5b010000 0x10000>; 39 reg = <0x5b010000 0x10000>;
76 clocks = <&sdhc0_lpcg IMX_LPCG 40 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
77 <&sdhc0_lpcg IMX_LPCG 41 <&sdhc0_lpcg IMX_LPCG_CLK_5>,
78 <&sdhc0_lpcg IMX_LPCG 42 <&sdhc0_lpcg IMX_LPCG_CLK_0>;
79 clock-names = "ipg", "ahb", "p !! 43 clock-names = "ipg", "per", "ahb";
80 power-domains = <&pd IMX_SC_R_ 44 power-domains = <&pd IMX_SC_R_SDHC_0>;
81 status = "disabled"; 45 status = "disabled";
82 }; 46 };
83 47
84 usdhc2: mmc@5b020000 { 48 usdhc2: mmc@5b020000 {
85 interrupts = <GIC_SPI 233 IRQ_ 49 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
86 reg = <0x5b020000 0x10000>; 50 reg = <0x5b020000 0x10000>;
87 clocks = <&sdhc1_lpcg IMX_LPCG 51 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
88 <&sdhc1_lpcg IMX_LPCG 52 <&sdhc1_lpcg IMX_LPCG_CLK_5>,
89 <&sdhc1_lpcg IMX_LPCG 53 <&sdhc1_lpcg IMX_LPCG_CLK_0>;
90 clock-names = "ipg", "ahb", "p !! 54 clock-names = "ipg", "per", "ahb";
91 power-domains = <&pd IMX_SC_R_ 55 power-domains = <&pd IMX_SC_R_SDHC_1>;
92 fsl,tuning-start-tap = <20>; 56 fsl,tuning-start-tap = <20>;
93 fsl,tuning-step = <2>; !! 57 fsl,tuning-step= <2>;
94 status = "disabled"; 58 status = "disabled";
95 }; 59 };
96 60
97 usdhc3: mmc@5b030000 { 61 usdhc3: mmc@5b030000 {
98 interrupts = <GIC_SPI 234 IRQ_ 62 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
99 reg = <0x5b030000 0x10000>; 63 reg = <0x5b030000 0x10000>;
100 clocks = <&sdhc2_lpcg IMX_LPCG 64 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
101 <&sdhc2_lpcg IMX_LPCG 65 <&sdhc2_lpcg IMX_LPCG_CLK_5>,
102 <&sdhc2_lpcg IMX_LPCG 66 <&sdhc2_lpcg IMX_LPCG_CLK_0>;
103 clock-names = "ipg", "ahb", "p !! 67 clock-names = "ipg", "per", "ahb";
104 power-domains = <&pd IMX_SC_R_ 68 power-domains = <&pd IMX_SC_R_SDHC_2>;
105 status = "disabled"; 69 status = "disabled";
106 }; 70 };
107 71
108 fec1: ethernet@5b040000 { 72 fec1: ethernet@5b040000 {
109 reg = <0x5b040000 0x10000>; 73 reg = <0x5b040000 0x10000>;
110 interrupts = <GIC_SPI 258 IRQ_ 74 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 256 IRQ_ 75 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 257 IRQ_ 76 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 259 IRQ_ 77 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&enet0_lpcg IMX_LPCG 78 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
115 <&enet0_lpcg IMX_LPCG 79 <&enet0_lpcg IMX_LPCG_CLK_2>,
116 <&enet0_lpcg IMX_LPCG 80 <&enet0_lpcg IMX_LPCG_CLK_3>,
117 <&enet0_lpcg IMX_LPCG 81 <&enet0_lpcg IMX_LPCG_CLK_0>;
118 clock-names = "ipg", "ahb", "e 82 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
119 assigned-clocks = <&clk IMX_SC 83 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
120 <&clk IMX_SC 84 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
121 assigned-clock-rates = <250000 85 assigned-clock-rates = <250000000>, <125000000>;
122 fsl,num-tx-queues = <3>; !! 86 fsl,num-tx-queues=<3>;
123 fsl,num-rx-queues = <3>; !! 87 fsl,num-rx-queues=<3>;
124 power-domains = <&pd IMX_SC_R_ 88 power-domains = <&pd IMX_SC_R_ENET_0>;
125 status = "disabled"; 89 status = "disabled";
126 }; 90 };
127 91
128 fec2: ethernet@5b050000 { 92 fec2: ethernet@5b050000 {
129 reg = <0x5b050000 0x10000>; 93 reg = <0x5b050000 0x10000>;
130 interrupts = <GIC_SPI 262 IRQ_ 94 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 260 I 95 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 261 I 96 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 263 I 97 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&enet1_lpcg IMX_LPCG 98 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
135 <&enet1_lpcg IMX_LPCG 99 <&enet1_lpcg IMX_LPCG_CLK_2>,
136 <&enet1_lpcg IMX_LPCG 100 <&enet1_lpcg IMX_LPCG_CLK_3>,
137 <&enet1_lpcg IMX_LPCG 101 <&enet1_lpcg IMX_LPCG_CLK_0>;
138 clock-names = "ipg", "ahb", "e 102 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
139 assigned-clocks = <&clk IMX_SC 103 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
140 <&clk IMX_SC 104 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
141 assigned-clock-rates = <250000 105 assigned-clock-rates = <250000000>, <125000000>;
142 fsl,num-tx-queues = <3>; !! 106 fsl,num-tx-queues=<3>;
143 fsl,num-rx-queues = <3>; !! 107 fsl,num-rx-queues=<3>;
144 power-domains = <&pd IMX_SC_R_ 108 power-domains = <&pd IMX_SC_R_ENET_1>;
145 status = "disabled"; 109 status = "disabled";
146 }; 110 };
147 111
148 usbotg3: usb@5b110000 { <<
149 compatible = "fsl,imx8qm-usb3" <<
150 reg = <0x5b110000 0x10000>; <<
151 #address-cells = <1>; <<
152 #size-cells = <1>; <<
153 ranges; <<
154 clocks = <&usb3_lpcg IMX_LPCG_ <<
155 <&usb3_lpcg IMX_LPCG_ <<
156 <&usb3_lpcg IMX_LPCG_ <<
157 <&usb3_lpcg IMX_LPCG_ <<
158 <&usb3_lpcg IMX_LPCG_ <<
159 clock-names = "lpm", "bus", "a <<
160 assigned-clocks = <&clk IMX_SC <<
161 assigned-clock-rates = <250000 <<
162 power-domains = <&pd IMX_SC_R_ <<
163 status = "disabled"; <<
164 <<
165 usbotg3_cdns3: usb@5b120000 { <<
166 compatible = "cdns,usb <<
167 reg = <0x5b120000 0x10 <<
168 <0x5b130000 0x10 <<
169 <0x5b140000 0x10 <<
170 reg-names = "otg", "xh <<
171 interrupt-parent = <&g <<
172 interrupts = <GIC_SPI <<
173 <GIC_SPI <<
174 <GIC_SPI <<
175 <GIC_SPI <<
176 interrupt-names = "hos <<
177 phys = <&usb3_phy>; <<
178 phy-names = "cdns3,usb <<
179 cdns,on-chip-buff-size <<
180 status = "disabled"; <<
181 }; <<
182 }; <<
183 <<
184 usb3_phy: usb-phy@5b160000 { <<
185 compatible = "nxp,salvo-phy"; <<
186 reg = <0x5b160000 0x40000>; <<
187 clocks = <&usb3_lpcg IMX_LPCG_ <<
188 clock-names = "salvo_phy_clk"; <<
189 power-domains = <&pd IMX_SC_R_ <<
190 #phy-cells = <0>; <<
191 status = "disabled"; <<
192 }; <<
193 <<
194 /* LPCG clocks */ 112 /* LPCG clocks */
195 sdhc0_lpcg: clock-controller@5b200000 113 sdhc0_lpcg: clock-controller@5b200000 {
196 compatible = "fsl,imx8qxp-lpcg 114 compatible = "fsl,imx8qxp-lpcg";
197 reg = <0x5b200000 0x10000>; 115 reg = <0x5b200000 0x10000>;
198 #clock-cells = <1>; 116 #clock-cells = <1>;
199 clocks = <&clk IMX_SC_R_SDHC_0 117 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
200 <&conn_ipg_clk>, <&co 118 <&conn_ipg_clk>, <&conn_axi_clk>;
201 clock-indices = <IMX_LPCG_CLK_ 119 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
202 <IMX_LPCG_CLK_ 120 <IMX_LPCG_CLK_5>;
203 clock-output-names = "sdhc0_lp 121 clock-output-names = "sdhc0_lpcg_per_clk",
204 "sdhc0_lp 122 "sdhc0_lpcg_ipg_clk",
205 "sdhc0_lp 123 "sdhc0_lpcg_ahb_clk";
206 power-domains = <&pd IMX_SC_R_ 124 power-domains = <&pd IMX_SC_R_SDHC_0>;
207 }; 125 };
208 126
209 sdhc1_lpcg: clock-controller@5b210000 127 sdhc1_lpcg: clock-controller@5b210000 {
210 compatible = "fsl,imx8qxp-lpcg 128 compatible = "fsl,imx8qxp-lpcg";
211 reg = <0x5b210000 0x10000>; 129 reg = <0x5b210000 0x10000>;
212 #clock-cells = <1>; 130 #clock-cells = <1>;
213 clocks = <&clk IMX_SC_R_SDHC_1 131 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
214 <&conn_ipg_clk>, <&co 132 <&conn_ipg_clk>, <&conn_axi_clk>;
215 clock-indices = <IMX_LPCG_CLK_ 133 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
216 <IMX_LPCG_CLK_ 134 <IMX_LPCG_CLK_5>;
217 clock-output-names = "sdhc1_lp 135 clock-output-names = "sdhc1_lpcg_per_clk",
218 "sdhc1_lp 136 "sdhc1_lpcg_ipg_clk",
219 "sdhc1_lp 137 "sdhc1_lpcg_ahb_clk";
220 power-domains = <&pd IMX_SC_R_ 138 power-domains = <&pd IMX_SC_R_SDHC_1>;
221 }; 139 };
222 140
223 sdhc2_lpcg: clock-controller@5b220000 141 sdhc2_lpcg: clock-controller@5b220000 {
224 compatible = "fsl,imx8qxp-lpcg 142 compatible = "fsl,imx8qxp-lpcg";
225 reg = <0x5b220000 0x10000>; 143 reg = <0x5b220000 0x10000>;
226 #clock-cells = <1>; 144 #clock-cells = <1>;
227 clocks = <&clk IMX_SC_R_SDHC_2 145 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
228 <&conn_ipg_clk>, <&co 146 <&conn_ipg_clk>, <&conn_axi_clk>;
229 clock-indices = <IMX_LPCG_CLK_ 147 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
230 <IMX_LPCG_CLK_ 148 <IMX_LPCG_CLK_5>;
231 clock-output-names = "sdhc2_lp 149 clock-output-names = "sdhc2_lpcg_per_clk",
232 "sdhc2_lp 150 "sdhc2_lpcg_ipg_clk",
233 "sdhc2_lp 151 "sdhc2_lpcg_ahb_clk";
234 power-domains = <&pd IMX_SC_R_ 152 power-domains = <&pd IMX_SC_R_SDHC_2>;
235 }; 153 };
236 154
237 enet0_lpcg: clock-controller@5b230000 155 enet0_lpcg: clock-controller@5b230000 {
238 compatible = "fsl,imx8qxp-lpcg 156 compatible = "fsl,imx8qxp-lpcg";
239 reg = <0x5b230000 0x10000>; 157 reg = <0x5b230000 0x10000>;
240 #clock-cells = <1>; 158 #clock-cells = <1>;
241 clocks = <&clk IMX_SC_R_ENET_0 159 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
242 <&clk IMX_SC_R_ENET_0 160 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
243 <&conn_axi_clk>, 161 <&conn_axi_clk>,
244 <&clk IMX_SC_R_ENET_0 162 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
245 <&conn_ipg_clk>, 163 <&conn_ipg_clk>,
246 <&conn_ipg_clk>; 164 <&conn_ipg_clk>;
247 clock-indices = <IMX_LPCG_CLK_ 165 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
248 <IMX_LPCG_CLK_ 166 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
249 <IMX_LPCG_CLK_ 167 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
250 clock-output-names = "enet0_lp 168 clock-output-names = "enet0_lpcg_timer_clk",
251 "enet0_lp 169 "enet0_lpcg_txc_sampling_clk",
252 "enet0_lp 170 "enet0_lpcg_ahb_clk",
253 "enet0_lp 171 "enet0_lpcg_rgmii_txc_clk",
254 "enet0_lp 172 "enet0_lpcg_ipg_clk",
255 "enet0_lp 173 "enet0_lpcg_ipg_s_clk";
256 power-domains = <&pd IMX_SC_R_ 174 power-domains = <&pd IMX_SC_R_ENET_0>;
257 }; 175 };
258 176
259 enet1_lpcg: clock-controller@5b240000 177 enet1_lpcg: clock-controller@5b240000 {
260 compatible = "fsl,imx8qxp-lpcg 178 compatible = "fsl,imx8qxp-lpcg";
261 reg = <0x5b240000 0x10000>; 179 reg = <0x5b240000 0x10000>;
262 #clock-cells = <1>; 180 #clock-cells = <1>;
263 clocks = <&clk IMX_SC_R_ENET_1 181 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
264 <&clk IMX_SC_R_ENET_1 182 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
265 <&conn_axi_clk>, 183 <&conn_axi_clk>,
266 <&clk IMX_SC_R_ENET_1 184 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
267 <&conn_ipg_clk>, 185 <&conn_ipg_clk>,
268 <&conn_ipg_clk>; 186 <&conn_ipg_clk>;
269 clock-indices = <IMX_LPCG_CLK_ 187 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
270 <IMX_LPCG_CLK_ 188 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
271 <IMX_LPCG_CLK_ 189 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
272 clock-output-names = "enet1_lp 190 clock-output-names = "enet1_lpcg_timer_clk",
273 "enet1_lp 191 "enet1_lpcg_txc_sampling_clk",
274 "enet1_lp 192 "enet1_lpcg_ahb_clk",
275 "enet1_lp 193 "enet1_lpcg_rgmii_txc_clk",
276 "enet1_lp 194 "enet1_lpcg_ipg_clk",
277 "enet1_lp 195 "enet1_lpcg_ipg_s_clk";
278 power-domains = <&pd IMX_SC_R_ 196 power-domains = <&pd IMX_SC_R_ENET_1>;
279 }; <<
280 <<
281 usb2_lpcg: clock-controller@5b270000 { <<
282 compatible = "fsl,imx8qxp-lpcg <<
283 reg = <0x5b270000 0x10000>; <<
284 #clock-cells = <1>; <<
285 clocks = <&conn_ahb_clk>, <&co <<
286 clock-indices = <IMX_LPCG_CLK_ <<
287 clock-output-names = "usboh3_a <<
288 power-domains = <&pd IMX_SC_R_ <<
289 }; <<
290 <<
291 usb3_lpcg: clock-controller@5b280000 { <<
292 compatible = "fsl,imx8qxp-lpcg <<
293 reg = <0x5b280000 0x10000>; <<
294 #clock-cells = <1>; <<
295 clock-indices = <IMX_LPCG_CLK_ <<
296 <IMX_LPCG_CLK_ <<
297 <IMX_LPCG_CLK_ <<
298 clocks = <&clk IMX_SC_R_USB_2 <<
299 <&clk IMX_SC_R_USB_2 <<
300 <&conn_ipg_clk>, <<
301 <&conn_ipg_clk>, <<
302 <&conn_ipg_clk>, <<
303 <&clk IMX_SC_R_USB_2 <<
304 clock-output-names = "usb3_app <<
305 "usb3_lpm <<
306 "usb3_ipg <<
307 "usb3_cor <<
308 "usb3_phy <<
309 "usb3_acl <<
310 power-domains = <&pd IMX_SC_R_ <<
311 }; <<
312 <<
313 rawnand_0_lpcg: clock-controller@5b290 <<
314 compatible = "fsl,imx8qxp-lpcg <<
315 reg = <0x5b290000 0x4>; <<
316 #clock-cells = <1>; <<
317 clocks = <&clk IMX_SC_R_NAND I <<
318 <&clk IMX_SC_R_NAND I <<
319 <&conn_axi_clk>, <<
320 <&conn_axi_clk>; <<
321 clock-indices = <IMX_LPCG_CLK_ <<
322 <IMX_LPCG_CLK_ <<
323 clock-output-names = "gpmi_bch <<
324 "gpmi_io" <<
325 "gpmi_apb <<
326 "gpmi_bch <<
327 power-domains = <&pd IMX_SC_R_ <<
328 }; <<
329 <<
330 rawnand_4_lpcg: clock-controller@5b290 <<
331 compatible = "fsl,imx8qxp-lpcg <<
332 reg = <0x5b290004 0x10000>; <<
333 #clock-cells = <1>; <<
334 clocks = <&conn_axi_clk>; <<
335 clock-indices = <IMX_LPCG_CLK_ <<
336 clock-output-names = "apbhdma_ <<
337 power-domains = <&pd IMX_SC_R_ <<
338 }; <<
339 <<
340 dma_apbh: dma-controller@5b810000 { <<
341 compatible = "fsl,imx8qxp-dma- <<
342 reg = <0x5b810000 0x2000>; <<
343 interrupts = <GIC_SPI 274 IRQ_ <<
344 <GIC_SPI 274 IRQ_ <<
345 <GIC_SPI 274 IRQ_ <<
346 <GIC_SPI 274 IRQ_ <<
347 #dma-cells = <1>; <<
348 dma-channels = <4>; <<
349 clocks = <&rawnand_4_lpcg IMX_ <<
350 power-domains = <&pd IMX_SC_R_ <<
351 }; <<
352 <<
353 gpmi: nand-controller@5b812000{ <<
354 compatible = "fsl,imx8qxp-gpmi <<
355 reg = <0x5b812000 0x2000>, <0x <<
356 reg-names = "gpmi-nand", "bch" <<
357 #address-cells = <1>; <<
358 #size-cells = <0>; <<
359 interrupts = <GIC_SPI 272 IRQ_ <<
360 interrupt-names = "bch"; <<
361 clocks = <&rawnand_0_lpcg IMX_ <<
362 <&rawnand_0_lpcg IMX_ <<
363 <&rawnand_0_lpcg IMX_ <<
364 <&rawnand_0_lpcg IMX_ <<
365 clock-names = "gpmi_io", "gpmi <<
366 "gpmi_bch", "gpm <<
367 dmas = <&dma_apbh 0>; <<
368 dma-names = "rx-tx"; <<
369 power-domains = <&pd IMX_SC_R_ <<
370 assigned-clocks = <&clk IMX_SC <<
371 assigned-clock-rates = <500000 <<
372 status = "disabled"; <<
373 }; 197 };
374 }; 198 };
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