1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018-2019 NXP 3 * Copyright 2018-2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 #include <dt-bindings/clock/imx8-lpcg.h> 7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/firmware/imx/rsrc.h>
9 9
10 conn_axi_clk: clock-conn-axi { <<
11 compatible = "fixed-clock"; <<
12 #clock-cells = <0>; <<
13 clock-frequency = <333333333>; <<
14 clock-output-names = "conn_axi_clk"; <<
15 }; <<
16 <<
17 conn_ahb_clk: clock-conn-ahb { <<
18 compatible = "fixed-clock"; <<
19 #clock-cells = <0>; <<
20 clock-frequency = <166666666>; <<
21 clock-output-names = "conn_ahb_clk"; <<
22 }; <<
23 <<
24 conn_ipg_clk: clock-conn-ipg { <<
25 compatible = "fixed-clock"; <<
26 #clock-cells = <0>; <<
27 clock-frequency = <83333333>; <<
28 clock-output-names = "conn_ipg_clk"; <<
29 }; <<
30 <<
31 conn_bch_clk: clock-conn-bch { <<
32 compatible = "fixed-clock"; <<
33 #clock-cells = <0>; <<
34 clock-frequency = <400000000>; <<
35 clock-output-names = "conn_bch_clk"; <<
36 }; <<
37 <<
38 conn_subsys: bus@5b000000 { 10 conn_subsys: bus@5b000000 {
39 compatible = "simple-bus"; 11 compatible = "simple-bus";
40 #address-cells = <1>; 12 #address-cells = <1>;
41 #size-cells = <1>; 13 #size-cells = <1>;
42 ranges = <0x5b000000 0x0 0x5b000000 0x 14 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
43 15
>> 16 conn_axi_clk: clock-conn-axi {
>> 17 compatible = "fixed-clock";
>> 18 #clock-cells = <0>;
>> 19 clock-frequency = <333333333>;
>> 20 clock-output-names = "conn_axi_clk";
>> 21 };
>> 22
>> 23 conn_ahb_clk: clock-conn-ahb {
>> 24 compatible = "fixed-clock";
>> 25 #clock-cells = <0>;
>> 26 clock-frequency = <166666666>;
>> 27 clock-output-names = "conn_ahb_clk";
>> 28 };
>> 29
>> 30 conn_ipg_clk: clock-conn-ipg {
>> 31 compatible = "fixed-clock";
>> 32 #clock-cells = <0>;
>> 33 clock-frequency = <83333333>;
>> 34 clock-output-names = "conn_ipg_clk";
>> 35 };
>> 36
44 usbotg1: usb@5b0d0000 { 37 usbotg1: usb@5b0d0000 {
45 compatible = "fsl,imx7ulp-usb" !! 38 compatible = "fsl,imx7ulp-usb";
46 reg = <0x5b0d0000 0x200>; 39 reg = <0x5b0d0000 0x200>;
47 interrupt-parent = <&gic>; 40 interrupt-parent = <&gic>;
48 interrupts = <GIC_SPI 267 IRQ_ 41 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
49 fsl,usbphy = <&usbphy1>; 42 fsl,usbphy = <&usbphy1>;
50 fsl,usbmisc = <&usbmisc1 0>; 43 fsl,usbmisc = <&usbmisc1 0>;
51 clocks = <&usb2_lpcg IMX_LPCG_ !! 44 clocks = <&usb2_lpcg 0>;
52 ahb-burst-config = <0x0>; 45 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>; 46 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>; 47 rx-burst-size-dword = <0x10>;
55 power-domains = <&pd IMX_SC_R_ 48 power-domains = <&pd IMX_SC_R_USB_0>;
56 status = "disabled"; 49 status = "disabled";
57 }; 50 };
58 51
59 usbmisc1: usbmisc@5b0d0200 { 52 usbmisc1: usbmisc@5b0d0200 {
60 #index-cells = <1>; 53 #index-cells = <1>;
61 compatible = "fsl,imx7ulp-usbm !! 54 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx6q-usbmisc";
62 reg = <0x5b0d0200 0x200>; 55 reg = <0x5b0d0200 0x200>;
63 }; 56 };
64 57
65 usbphy1: usbphy@5b100000 { 58 usbphy1: usbphy@5b100000 {
66 compatible = "fsl,imx7ulp-usbp 59 compatible = "fsl,imx7ulp-usbphy";
67 reg = <0x5b100000 0x1000>; 60 reg = <0x5b100000 0x1000>;
68 clocks = <&usb2_lpcg IMX_LPCG_ !! 61 clocks = <&usb2_lpcg 1>;
69 power-domains = <&pd IMX_SC_R_ 62 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
70 status = "disabled"; 63 status = "disabled";
71 }; 64 };
72 65
73 usdhc1: mmc@5b010000 { 66 usdhc1: mmc@5b010000 {
74 interrupts = <GIC_SPI 232 IRQ_ 67 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
75 reg = <0x5b010000 0x10000>; 68 reg = <0x5b010000 0x10000>;
76 clocks = <&sdhc0_lpcg IMX_LPCG 69 clocks = <&sdhc0_lpcg IMX_LPCG_CLK_4>,
77 <&sdhc0_lpcg IMX_LPCG !! 70 <&sdhc0_lpcg IMX_LPCG_CLK_0>,
78 <&sdhc0_lpcg IMX_LPCG !! 71 <&sdhc0_lpcg IMX_LPCG_CLK_5>;
79 clock-names = "ipg", "ahb", "p 72 clock-names = "ipg", "ahb", "per";
80 power-domains = <&pd IMX_SC_R_ 73 power-domains = <&pd IMX_SC_R_SDHC_0>;
81 status = "disabled"; 74 status = "disabled";
82 }; 75 };
83 76
84 usdhc2: mmc@5b020000 { 77 usdhc2: mmc@5b020000 {
85 interrupts = <GIC_SPI 233 IRQ_ 78 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
86 reg = <0x5b020000 0x10000>; 79 reg = <0x5b020000 0x10000>;
87 clocks = <&sdhc1_lpcg IMX_LPCG 80 clocks = <&sdhc1_lpcg IMX_LPCG_CLK_4>,
88 <&sdhc1_lpcg IMX_LPCG !! 81 <&sdhc1_lpcg IMX_LPCG_CLK_0>,
89 <&sdhc1_lpcg IMX_LPCG !! 82 <&sdhc1_lpcg IMX_LPCG_CLK_5>;
90 clock-names = "ipg", "ahb", "p 83 clock-names = "ipg", "ahb", "per";
91 power-domains = <&pd IMX_SC_R_ 84 power-domains = <&pd IMX_SC_R_SDHC_1>;
92 fsl,tuning-start-tap = <20>; 85 fsl,tuning-start-tap = <20>;
93 fsl,tuning-step = <2>; 86 fsl,tuning-step = <2>;
94 status = "disabled"; 87 status = "disabled";
95 }; 88 };
96 89
97 usdhc3: mmc@5b030000 { 90 usdhc3: mmc@5b030000 {
98 interrupts = <GIC_SPI 234 IRQ_ 91 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
99 reg = <0x5b030000 0x10000>; 92 reg = <0x5b030000 0x10000>;
100 clocks = <&sdhc2_lpcg IMX_LPCG 93 clocks = <&sdhc2_lpcg IMX_LPCG_CLK_4>,
101 <&sdhc2_lpcg IMX_LPCG !! 94 <&sdhc2_lpcg IMX_LPCG_CLK_0>,
102 <&sdhc2_lpcg IMX_LPCG !! 95 <&sdhc2_lpcg IMX_LPCG_CLK_5>;
103 clock-names = "ipg", "ahb", "p 96 clock-names = "ipg", "ahb", "per";
104 power-domains = <&pd IMX_SC_R_ 97 power-domains = <&pd IMX_SC_R_SDHC_2>;
105 status = "disabled"; 98 status = "disabled";
106 }; 99 };
107 100
108 fec1: ethernet@5b040000 { 101 fec1: ethernet@5b040000 {
109 reg = <0x5b040000 0x10000>; 102 reg = <0x5b040000 0x10000>;
110 interrupts = <GIC_SPI 258 IRQ_ 103 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
111 <GIC_SPI 256 IRQ_ 104 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
112 <GIC_SPI 257 IRQ_ 105 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
113 <GIC_SPI 259 IRQ_ 106 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
114 clocks = <&enet0_lpcg IMX_LPCG 107 clocks = <&enet0_lpcg IMX_LPCG_CLK_4>,
115 <&enet0_lpcg IMX_LPCG 108 <&enet0_lpcg IMX_LPCG_CLK_2>,
116 <&enet0_lpcg IMX_LPCG 109 <&enet0_lpcg IMX_LPCG_CLK_3>,
117 <&enet0_lpcg IMX_LPCG 110 <&enet0_lpcg IMX_LPCG_CLK_0>;
118 clock-names = "ipg", "ahb", "e 111 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
119 assigned-clocks = <&clk IMX_SC 112 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
120 <&clk IMX_SC 113 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
121 assigned-clock-rates = <250000 114 assigned-clock-rates = <250000000>, <125000000>;
122 fsl,num-tx-queues = <3>; 115 fsl,num-tx-queues = <3>;
123 fsl,num-rx-queues = <3>; 116 fsl,num-rx-queues = <3>;
124 power-domains = <&pd IMX_SC_R_ 117 power-domains = <&pd IMX_SC_R_ENET_0>;
125 status = "disabled"; 118 status = "disabled";
126 }; 119 };
127 120
128 fec2: ethernet@5b050000 { 121 fec2: ethernet@5b050000 {
129 reg = <0x5b050000 0x10000>; 122 reg = <0x5b050000 0x10000>;
130 interrupts = <GIC_SPI 262 IRQ_ 123 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 260 I 124 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 261 I 125 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 263 I 126 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&enet1_lpcg IMX_LPCG 127 clocks = <&enet1_lpcg IMX_LPCG_CLK_4>,
135 <&enet1_lpcg IMX_LPCG 128 <&enet1_lpcg IMX_LPCG_CLK_2>,
136 <&enet1_lpcg IMX_LPCG 129 <&enet1_lpcg IMX_LPCG_CLK_3>,
137 <&enet1_lpcg IMX_LPCG 130 <&enet1_lpcg IMX_LPCG_CLK_0>;
138 clock-names = "ipg", "ahb", "e 131 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
139 assigned-clocks = <&clk IMX_SC 132 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
140 <&clk IMX_SC 133 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
141 assigned-clock-rates = <250000 134 assigned-clock-rates = <250000000>, <125000000>;
142 fsl,num-tx-queues = <3>; 135 fsl,num-tx-queues = <3>;
143 fsl,num-rx-queues = <3>; 136 fsl,num-rx-queues = <3>;
144 power-domains = <&pd IMX_SC_R_ 137 power-domains = <&pd IMX_SC_R_ENET_1>;
145 status = "disabled"; 138 status = "disabled";
146 }; 139 };
147 140
148 usbotg3: usb@5b110000 { <<
149 compatible = "fsl,imx8qm-usb3" <<
150 reg = <0x5b110000 0x10000>; <<
151 #address-cells = <1>; <<
152 #size-cells = <1>; <<
153 ranges; <<
154 clocks = <&usb3_lpcg IMX_LPCG_ <<
155 <&usb3_lpcg IMX_LPCG_ <<
156 <&usb3_lpcg IMX_LPCG_ <<
157 <&usb3_lpcg IMX_LPCG_ <<
158 <&usb3_lpcg IMX_LPCG_ <<
159 clock-names = "lpm", "bus", "a <<
160 assigned-clocks = <&clk IMX_SC <<
161 assigned-clock-rates = <250000 <<
162 power-domains = <&pd IMX_SC_R_ <<
163 status = "disabled"; <<
164 <<
165 usbotg3_cdns3: usb@5b120000 { <<
166 compatible = "cdns,usb <<
167 reg = <0x5b120000 0x10 <<
168 <0x5b130000 0x10 <<
169 <0x5b140000 0x10 <<
170 reg-names = "otg", "xh <<
171 interrupt-parent = <&g <<
172 interrupts = <GIC_SPI <<
173 <GIC_SPI <<
174 <GIC_SPI <<
175 <GIC_SPI <<
176 interrupt-names = "hos <<
177 phys = <&usb3_phy>; <<
178 phy-names = "cdns3,usb <<
179 cdns,on-chip-buff-size <<
180 status = "disabled"; <<
181 }; <<
182 }; <<
183 <<
184 usb3_phy: usb-phy@5b160000 { <<
185 compatible = "nxp,salvo-phy"; <<
186 reg = <0x5b160000 0x40000>; <<
187 clocks = <&usb3_lpcg IMX_LPCG_ <<
188 clock-names = "salvo_phy_clk"; <<
189 power-domains = <&pd IMX_SC_R_ <<
190 #phy-cells = <0>; <<
191 status = "disabled"; <<
192 }; <<
193 <<
194 /* LPCG clocks */ 141 /* LPCG clocks */
195 sdhc0_lpcg: clock-controller@5b200000 142 sdhc0_lpcg: clock-controller@5b200000 {
196 compatible = "fsl,imx8qxp-lpcg 143 compatible = "fsl,imx8qxp-lpcg";
197 reg = <0x5b200000 0x10000>; 144 reg = <0x5b200000 0x10000>;
198 #clock-cells = <1>; 145 #clock-cells = <1>;
199 clocks = <&clk IMX_SC_R_SDHC_0 146 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
200 <&conn_ipg_clk>, <&co 147 <&conn_ipg_clk>, <&conn_axi_clk>;
201 clock-indices = <IMX_LPCG_CLK_ 148 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
202 <IMX_LPCG_CLK_ 149 <IMX_LPCG_CLK_5>;
203 clock-output-names = "sdhc0_lp 150 clock-output-names = "sdhc0_lpcg_per_clk",
204 "sdhc0_lp 151 "sdhc0_lpcg_ipg_clk",
205 "sdhc0_lp 152 "sdhc0_lpcg_ahb_clk";
206 power-domains = <&pd IMX_SC_R_ 153 power-domains = <&pd IMX_SC_R_SDHC_0>;
207 }; 154 };
208 155
209 sdhc1_lpcg: clock-controller@5b210000 156 sdhc1_lpcg: clock-controller@5b210000 {
210 compatible = "fsl,imx8qxp-lpcg 157 compatible = "fsl,imx8qxp-lpcg";
211 reg = <0x5b210000 0x10000>; 158 reg = <0x5b210000 0x10000>;
212 #clock-cells = <1>; 159 #clock-cells = <1>;
213 clocks = <&clk IMX_SC_R_SDHC_1 160 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
214 <&conn_ipg_clk>, <&co 161 <&conn_ipg_clk>, <&conn_axi_clk>;
215 clock-indices = <IMX_LPCG_CLK_ 162 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
216 <IMX_LPCG_CLK_ 163 <IMX_LPCG_CLK_5>;
217 clock-output-names = "sdhc1_lp 164 clock-output-names = "sdhc1_lpcg_per_clk",
218 "sdhc1_lp 165 "sdhc1_lpcg_ipg_clk",
219 "sdhc1_lp 166 "sdhc1_lpcg_ahb_clk";
220 power-domains = <&pd IMX_SC_R_ 167 power-domains = <&pd IMX_SC_R_SDHC_1>;
221 }; 168 };
222 169
223 sdhc2_lpcg: clock-controller@5b220000 170 sdhc2_lpcg: clock-controller@5b220000 {
224 compatible = "fsl,imx8qxp-lpcg 171 compatible = "fsl,imx8qxp-lpcg";
225 reg = <0x5b220000 0x10000>; 172 reg = <0x5b220000 0x10000>;
226 #clock-cells = <1>; 173 #clock-cells = <1>;
227 clocks = <&clk IMX_SC_R_SDHC_2 174 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
228 <&conn_ipg_clk>, <&co 175 <&conn_ipg_clk>, <&conn_axi_clk>;
229 clock-indices = <IMX_LPCG_CLK_ 176 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
230 <IMX_LPCG_CLK_ 177 <IMX_LPCG_CLK_5>;
231 clock-output-names = "sdhc2_lp 178 clock-output-names = "sdhc2_lpcg_per_clk",
232 "sdhc2_lp 179 "sdhc2_lpcg_ipg_clk",
233 "sdhc2_lp 180 "sdhc2_lpcg_ahb_clk";
234 power-domains = <&pd IMX_SC_R_ 181 power-domains = <&pd IMX_SC_R_SDHC_2>;
235 }; 182 };
236 183
237 enet0_lpcg: clock-controller@5b230000 184 enet0_lpcg: clock-controller@5b230000 {
238 compatible = "fsl,imx8qxp-lpcg 185 compatible = "fsl,imx8qxp-lpcg";
239 reg = <0x5b230000 0x10000>; 186 reg = <0x5b230000 0x10000>;
240 #clock-cells = <1>; 187 #clock-cells = <1>;
241 clocks = <&clk IMX_SC_R_ENET_0 188 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
242 <&clk IMX_SC_R_ENET_0 189 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
243 <&conn_axi_clk>, 190 <&conn_axi_clk>,
244 <&clk IMX_SC_R_ENET_0 191 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
245 <&conn_ipg_clk>, 192 <&conn_ipg_clk>,
246 <&conn_ipg_clk>; 193 <&conn_ipg_clk>;
247 clock-indices = <IMX_LPCG_CLK_ 194 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
248 <IMX_LPCG_CLK_ 195 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
249 <IMX_LPCG_CLK_ 196 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
250 clock-output-names = "enet0_lp 197 clock-output-names = "enet0_lpcg_timer_clk",
251 "enet0_lp 198 "enet0_lpcg_txc_sampling_clk",
252 "enet0_lp 199 "enet0_lpcg_ahb_clk",
253 "enet0_lp 200 "enet0_lpcg_rgmii_txc_clk",
254 "enet0_lp 201 "enet0_lpcg_ipg_clk",
255 "enet0_lp 202 "enet0_lpcg_ipg_s_clk";
256 power-domains = <&pd IMX_SC_R_ 203 power-domains = <&pd IMX_SC_R_ENET_0>;
257 }; 204 };
258 205
259 enet1_lpcg: clock-controller@5b240000 206 enet1_lpcg: clock-controller@5b240000 {
260 compatible = "fsl,imx8qxp-lpcg 207 compatible = "fsl,imx8qxp-lpcg";
261 reg = <0x5b240000 0x10000>; 208 reg = <0x5b240000 0x10000>;
262 #clock-cells = <1>; 209 #clock-cells = <1>;
263 clocks = <&clk IMX_SC_R_ENET_1 210 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
264 <&clk IMX_SC_R_ENET_1 211 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
265 <&conn_axi_clk>, 212 <&conn_axi_clk>,
266 <&clk IMX_SC_R_ENET_1 213 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
267 <&conn_ipg_clk>, 214 <&conn_ipg_clk>,
268 <&conn_ipg_clk>; 215 <&conn_ipg_clk>;
269 clock-indices = <IMX_LPCG_CLK_ 216 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
270 <IMX_LPCG_CLK_ 217 <IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_3>,
271 <IMX_LPCG_CLK_ 218 <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
272 clock-output-names = "enet1_lp 219 clock-output-names = "enet1_lpcg_timer_clk",
273 "enet1_lp 220 "enet1_lpcg_txc_sampling_clk",
274 "enet1_lp 221 "enet1_lpcg_ahb_clk",
275 "enet1_lp 222 "enet1_lpcg_rgmii_txc_clk",
276 "enet1_lp 223 "enet1_lpcg_ipg_clk",
277 "enet1_lp 224 "enet1_lpcg_ipg_s_clk";
278 power-domains = <&pd IMX_SC_R_ 225 power-domains = <&pd IMX_SC_R_ENET_1>;
279 }; 226 };
280 227
281 usb2_lpcg: clock-controller@5b270000 { 228 usb2_lpcg: clock-controller@5b270000 {
282 compatible = "fsl,imx8qxp-lpcg 229 compatible = "fsl,imx8qxp-lpcg";
283 reg = <0x5b270000 0x10000>; 230 reg = <0x5b270000 0x10000>;
284 #clock-cells = <1>; 231 #clock-cells = <1>;
285 clocks = <&conn_ahb_clk>, <&co 232 clocks = <&conn_ahb_clk>, <&conn_ipg_clk>;
286 clock-indices = <IMX_LPCG_CLK_ 233 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
287 clock-output-names = "usboh3_a 234 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
288 power-domains = <&pd IMX_SC_R_ 235 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
289 }; <<
290 <<
291 usb3_lpcg: clock-controller@5b280000 { <<
292 compatible = "fsl,imx8qxp-lpcg <<
293 reg = <0x5b280000 0x10000>; <<
294 #clock-cells = <1>; <<
295 clock-indices = <IMX_LPCG_CLK_ <<
296 <IMX_LPCG_CLK_ <<
297 <IMX_LPCG_CLK_ <<
298 clocks = <&clk IMX_SC_R_USB_2 <<
299 <&clk IMX_SC_R_USB_2 <<
300 <&conn_ipg_clk>, <<
301 <&conn_ipg_clk>, <<
302 <&conn_ipg_clk>, <<
303 <&clk IMX_SC_R_USB_2 <<
304 clock-output-names = "usb3_app <<
305 "usb3_lpm <<
306 "usb3_ipg <<
307 "usb3_cor <<
308 "usb3_phy <<
309 "usb3_acl <<
310 power-domains = <&pd IMX_SC_R_ <<
311 }; <<
312 <<
313 rawnand_0_lpcg: clock-controller@5b290 <<
314 compatible = "fsl,imx8qxp-lpcg <<
315 reg = <0x5b290000 0x4>; <<
316 #clock-cells = <1>; <<
317 clocks = <&clk IMX_SC_R_NAND I <<
318 <&clk IMX_SC_R_NAND I <<
319 <&conn_axi_clk>, <<
320 <&conn_axi_clk>; <<
321 clock-indices = <IMX_LPCG_CLK_ <<
322 <IMX_LPCG_CLK_ <<
323 clock-output-names = "gpmi_bch <<
324 "gpmi_io" <<
325 "gpmi_apb <<
326 "gpmi_bch <<
327 power-domains = <&pd IMX_SC_R_ <<
328 }; <<
329 <<
330 rawnand_4_lpcg: clock-controller@5b290 <<
331 compatible = "fsl,imx8qxp-lpcg <<
332 reg = <0x5b290004 0x10000>; <<
333 #clock-cells = <1>; <<
334 clocks = <&conn_axi_clk>; <<
335 clock-indices = <IMX_LPCG_CLK_ <<
336 clock-output-names = "apbhdma_ <<
337 power-domains = <&pd IMX_SC_R_ <<
338 }; <<
339 <<
340 dma_apbh: dma-controller@5b810000 { <<
341 compatible = "fsl,imx8qxp-dma- <<
342 reg = <0x5b810000 0x2000>; <<
343 interrupts = <GIC_SPI 274 IRQ_ <<
344 <GIC_SPI 274 IRQ_ <<
345 <GIC_SPI 274 IRQ_ <<
346 <GIC_SPI 274 IRQ_ <<
347 #dma-cells = <1>; <<
348 dma-channels = <4>; <<
349 clocks = <&rawnand_4_lpcg IMX_ <<
350 power-domains = <&pd IMX_SC_R_ <<
351 }; <<
352 <<
353 gpmi: nand-controller@5b812000{ <<
354 compatible = "fsl,imx8qxp-gpmi <<
355 reg = <0x5b812000 0x2000>, <0x <<
356 reg-names = "gpmi-nand", "bch" <<
357 #address-cells = <1>; <<
358 #size-cells = <0>; <<
359 interrupts = <GIC_SPI 272 IRQ_ <<
360 interrupt-names = "bch"; <<
361 clocks = <&rawnand_0_lpcg IMX_ <<
362 <&rawnand_0_lpcg IMX_ <<
363 <&rawnand_0_lpcg IMX_ <<
364 <&rawnand_0_lpcg IMX_ <<
365 clock-names = "gpmi_io", "gpmi <<
366 "gpmi_bch", "gpm <<
367 dmas = <&dma_apbh 0>; <<
368 dma-names = "rx-tx"; <<
369 power-domains = <&pd IMX_SC_R_ <<
370 assigned-clocks = <&clk IMX_SC <<
371 assigned-clock-rates = <500000 <<
372 status = "disabled"; <<
373 }; 236 };
374 }; 237 };
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