1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 * Dong Aisheng <aisheng.dong@nxp.com> 4 * Dong Aisheng <aisheng.dong@nxp.com>
5 */ 5 */
6 6
7 #include <dt-bindings/firmware/imx/rsrc.h> 7 #include <dt-bindings/firmware/imx/rsrc.h>
8 8
9 gpu0_subsys: bus@53000000 { 9 gpu0_subsys: bus@53000000 {
10 compatible = "simple-bus"; 10 compatible = "simple-bus";
11 #address-cells = <1>; 11 #address-cells = <1>;
12 #size-cells = <1>; 12 #size-cells = <1>;
13 ranges = <0x53000000 0x0 0x53000000 0x 13 ranges = <0x53000000 0x0 0x53000000 0x1000000>;
14 14
15 gpu_3d0: gpu@53100000 { 15 gpu_3d0: gpu@53100000 {
16 compatible = "vivante,gc"; 16 compatible = "vivante,gc";
17 reg = <0x53100000 0x40000>; 17 reg = <0x53100000 0x40000>;
18 interrupts = <GIC_SPI 64 IRQ_T 18 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
19 clocks = <&clk IMX_SC_R_GPU_0_ 19 clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
20 <&clk IMX_SC_R_GPU_0_ 20 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
21 clock-names = "core", "shader" 21 clock-names = "core", "shader";
22 assigned-clocks = <&clk IMX_SC 22 assigned-clocks = <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_PER>,
23 <&clk IMX_SC 23 <&clk IMX_SC_R_GPU_0_PID0 IMX_SC_PM_CLK_MISC>;
24 assigned-clock-rates = <700000 24 assigned-clock-rates = <700000000>, <850000000>;
25 power-domains = <&pd IMX_SC_R_ 25 power-domains = <&pd IMX_SC_R_GPU_0_PID0>;
26 }; 26 };
27 }; 27 };
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