1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019-2021 NXP 3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com> 4 * Zhou Guoniu <guoniu.zhou@nxp.com>
5 */ 5 */
6 img_ipg_clk: clock-img-ipg { 6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock"; 7 compatible = "fixed-clock";
8 #clock-cells = <0>; 8 #clock-cells = <0>;
9 clock-frequency = <200000000>; 9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk"; 10 clock-output-names = "img_ipg_clk";
11 }; 11 };
12 12
13 img_subsys: bus@58000000 { 13 img_subsys: bus@58000000 {
14 compatible = "simple-bus"; 14 compatible = "simple-bus";
15 #address-cells = <1>; 15 #address-cells = <1>;
16 #size-cells = <1>; 16 #size-cells = <1>;
17 ranges = <0x58000000 0x0 0x58000000 0x 17 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
18 18
19 jpegdec: jpegdec@58400000 { 19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>; 20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_ 21 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
22 clocks = <&img_jpeg_dec_lpcg I 22 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
23 <&img_jpeg_dec_lpcg I 23 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
24 assigned-clocks = <&img_jpeg_d 24 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
25 <&img_jpeg_d 25 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
26 assigned-clock-rates = <200000 26 assigned-clock-rates = <200000000>, <200000000>;
27 power-domains = <&pd IMX_SC_R_ 27 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
28 <&pd IMX_SC_R_ 28 <&pd IMX_SC_R_MJPEG_DEC_S0>;
29 }; 29 };
30 30
31 jpegenc: jpegenc@58450000 { 31 jpegenc: jpegenc@58450000 {
32 reg = <0x58450000 0x00050000>; 32 reg = <0x58450000 0x00050000>;
33 interrupts = <GIC_SPI 305 IRQ_ 33 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&img_jpeg_enc_lpcg I 34 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
35 <&img_jpeg_enc_lpcg I 35 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
36 assigned-clocks = <&img_jpeg_e 36 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
37 <&img_jpeg_e 37 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
38 assigned-clock-rates = <200000 38 assigned-clock-rates = <200000000>, <200000000>;
39 power-domains = <&pd IMX_SC_R_ 39 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
40 <&pd IMX_SC_R_ 40 <&pd IMX_SC_R_MJPEG_ENC_S0>;
41 }; 41 };
42 42
43 img_jpeg_dec_lpcg: clock-controller@58 43 img_jpeg_dec_lpcg: clock-controller@585d0000 {
44 compatible = "fsl,imx8qxp-lpcg 44 compatible = "fsl,imx8qxp-lpcg";
45 reg = <0x585d0000 0x10000>; 45 reg = <0x585d0000 0x10000>;
46 #clock-cells = <1>; 46 #clock-cells = <1>;
47 clocks = <&img_ipg_clk>, <&img 47 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
48 clock-indices = <IMX_LPCG_CLK_ 48 clock-indices = <IMX_LPCG_CLK_0>,
49 <IMX_LPCG_CLK_ 49 <IMX_LPCG_CLK_4>;
50 clock-output-names = "img_jpeg 50 clock-output-names = "img_jpeg_dec_lpcg_clk",
51 "img_jpeg 51 "img_jpeg_dec_lpcg_ipg_clk";
52 power-domains = <&pd IMX_SC_R_ 52 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
53 }; 53 };
54 54
55 img_jpeg_enc_lpcg: clock-controller@58 55 img_jpeg_enc_lpcg: clock-controller@585f0000 {
56 compatible = "fsl,imx8qxp-lpcg 56 compatible = "fsl,imx8qxp-lpcg";
57 reg = <0x585f0000 0x10000>; 57 reg = <0x585f0000 0x10000>;
58 #clock-cells = <1>; 58 #clock-cells = <1>;
59 clocks = <&img_ipg_clk>, <&img 59 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
60 clock-indices = <IMX_LPCG_CLK_ 60 clock-indices = <IMX_LPCG_CLK_0>,
61 <IMX_LPCG_CLK_ 61 <IMX_LPCG_CLK_4>;
62 clock-output-names = "img_jpeg 62 clock-output-names = "img_jpeg_enc_lpcg_clk",
63 "img_jpeg 63 "img_jpeg_enc_lpcg_ipg_clk";
64 power-domains = <&pd IMX_SC_R_ 64 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
65 }; 65 };
66 }; 66 };
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