1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com>
5 */
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
11 };
12
13 img_subsys: bus@58000000 {
14 compatible = "simple-bus";
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges = <0x58000000 0x0 0x58000000 0x
18
19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_
22 clocks = <&img_jpeg_dec_lpcg I
23 <&img_jpeg_dec_lpcg I
24 assigned-clocks = <&img_jpeg_d
25 <&img_jpeg_d
26 assigned-clock-rates = <200000
27 power-domains = <&pd IMX_SC_R_
28 <&pd IMX_SC_R_
29 };
30
31 jpegenc: jpegenc@58450000 {
32 reg = <0x58450000 0x00050000>;
33 interrupts = <GIC_SPI 305 IRQ_
34 clocks = <&img_jpeg_enc_lpcg I
35 <&img_jpeg_enc_lpcg I
36 assigned-clocks = <&img_jpeg_e
37 <&img_jpeg_e
38 assigned-clock-rates = <200000
39 power-domains = <&pd IMX_SC_R_
40 <&pd IMX_SC_R_
41 };
42
43 img_jpeg_dec_lpcg: clock-controller@58
44 compatible = "fsl,imx8qxp-lpcg
45 reg = <0x585d0000 0x10000>;
46 #clock-cells = <1>;
47 clocks = <&img_ipg_clk>, <&img
48 clock-indices = <IMX_LPCG_CLK_
49 <IMX_LPCG_CLK_
50 clock-output-names = "img_jpeg
51 "img_jpeg
52 power-domains = <&pd IMX_SC_R_
53 };
54
55 img_jpeg_enc_lpcg: clock-controller@58
56 compatible = "fsl,imx8qxp-lpcg
57 reg = <0x585f0000 0x10000>;
58 #clock-cells = <1>;
59 clocks = <&img_ipg_clk>, <&img
60 clock-indices = <IMX_LPCG_CLK_
61 <IMX_LPCG_CLK_
62 clock-output-names = "img_jpeg
63 "img_jpeg
64 power-domains = <&pd IMX_SC_R_
65 };
66 };
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