1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019-2021 NXP 3 * Copyright 2019-2021 NXP
4 * Zhou Guoniu <guoniu.zhou@nxp.com> 4 * Zhou Guoniu <guoniu.zhou@nxp.com>
5 */ 5 */
6 img_ipg_clk: clock-img-ipg { <<
7 compatible = "fixed-clock"; <<
8 #clock-cells = <0>; <<
9 clock-frequency = <200000000>; <<
10 clock-output-names = "img_ipg_clk"; <<
11 }; <<
12 <<
13 img_subsys: bus@58000000 { 6 img_subsys: bus@58000000 {
14 compatible = "simple-bus"; 7 compatible = "simple-bus";
15 #address-cells = <1>; 8 #address-cells = <1>;
16 #size-cells = <1>; 9 #size-cells = <1>;
17 ranges = <0x58000000 0x0 0x58000000 0x 10 ranges = <0x58000000 0x0 0x58000000 0x1000000>;
18 11
>> 12 img_ipg_clk: clock-img-ipg {
>> 13 compatible = "fixed-clock";
>> 14 #clock-cells = <0>;
>> 15 clock-frequency = <200000000>;
>> 16 clock-output-names = "img_ipg_clk";
>> 17 };
>> 18
19 jpegdec: jpegdec@58400000 { 19 jpegdec: jpegdec@58400000 {
20 reg = <0x58400000 0x00050000>; 20 reg = <0x58400000 0x00050000>;
21 interrupts = <GIC_SPI 309 IRQ_ !! 21 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
>> 22 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
>> 23 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
>> 24 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
22 clocks = <&img_jpeg_dec_lpcg I 25 clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
23 <&img_jpeg_dec_lpcg I 26 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
>> 27 clock-names = "per", "ipg";
24 assigned-clocks = <&img_jpeg_d 28 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
25 <&img_jpeg_d 29 <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
26 assigned-clock-rates = <200000 30 assigned-clock-rates = <200000000>, <200000000>;
27 power-domains = <&pd IMX_SC_R_ 31 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
28 <&pd IMX_SC_R_ !! 32 <&pd IMX_SC_R_MJPEG_DEC_S0>,
>> 33 <&pd IMX_SC_R_MJPEG_DEC_S1>,
>> 34 <&pd IMX_SC_R_MJPEG_DEC_S2>,
>> 35 <&pd IMX_SC_R_MJPEG_DEC_S3>;
29 }; 36 };
30 37
31 jpegenc: jpegenc@58450000 { 38 jpegenc: jpegenc@58450000 {
32 reg = <0x58450000 0x00050000>; 39 reg = <0x58450000 0x00050000>;
33 interrupts = <GIC_SPI 305 IRQ_ !! 40 interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
>> 41 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
>> 42 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
>> 43 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
34 clocks = <&img_jpeg_enc_lpcg I 44 clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
35 <&img_jpeg_enc_lpcg I 45 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
>> 46 clock-names = "per", "ipg";
36 assigned-clocks = <&img_jpeg_e 47 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
37 <&img_jpeg_e 48 <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>;
38 assigned-clock-rates = <200000 49 assigned-clock-rates = <200000000>, <200000000>;
39 power-domains = <&pd IMX_SC_R_ 50 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
40 <&pd IMX_SC_R_ !! 51 <&pd IMX_SC_R_MJPEG_ENC_S0>,
>> 52 <&pd IMX_SC_R_MJPEG_ENC_S1>,
>> 53 <&pd IMX_SC_R_MJPEG_ENC_S2>,
>> 54 <&pd IMX_SC_R_MJPEG_ENC_S3>;
41 }; 55 };
42 56
43 img_jpeg_dec_lpcg: clock-controller@58 57 img_jpeg_dec_lpcg: clock-controller@585d0000 {
44 compatible = "fsl,imx8qxp-lpcg 58 compatible = "fsl,imx8qxp-lpcg";
45 reg = <0x585d0000 0x10000>; 59 reg = <0x585d0000 0x10000>;
46 #clock-cells = <1>; 60 #clock-cells = <1>;
47 clocks = <&img_ipg_clk>, <&img 61 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
48 clock-indices = <IMX_LPCG_CLK_ 62 clock-indices = <IMX_LPCG_CLK_0>,
49 <IMX_LPCG_CLK_ 63 <IMX_LPCG_CLK_4>;
50 clock-output-names = "img_jpeg 64 clock-output-names = "img_jpeg_dec_lpcg_clk",
51 "img_jpeg 65 "img_jpeg_dec_lpcg_ipg_clk";
52 power-domains = <&pd IMX_SC_R_ 66 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
53 }; 67 };
54 68
55 img_jpeg_enc_lpcg: clock-controller@58 69 img_jpeg_enc_lpcg: clock-controller@585f0000 {
56 compatible = "fsl,imx8qxp-lpcg 70 compatible = "fsl,imx8qxp-lpcg";
57 reg = <0x585f0000 0x10000>; 71 reg = <0x585f0000 0x10000>;
58 #clock-cells = <1>; 72 #clock-cells = <1>;
59 clocks = <&img_ipg_clk>, <&img 73 clocks = <&img_ipg_clk>, <&img_ipg_clk>;
60 clock-indices = <IMX_LPCG_CLK_ 74 clock-indices = <IMX_LPCG_CLK_0>,
61 <IMX_LPCG_CLK_ 75 <IMX_LPCG_CLK_4>;
62 clock-output-names = "img_jpeg 76 clock-output-names = "img_jpeg_enc_lpcg_clk",
63 "img_jpeg 77 "img_jpeg_enc_lpcg_ipg_clk";
64 power-domains = <&pd IMX_SC_R_ 78 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;
65 }; 79 };
66 }; 80 };
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