1 // SPDX-License-Identifier: GPL-2.0-only and M 1 // SPDX-License-Identifier: GPL-2.0-only and MIT
2 2
3 /* 3 /*
4 * Copyright 2024 NXP 4 * Copyright 2024 NXP
5 */ 5 */
6 6
7 lvds0_subsys: bus@56240000 { 7 lvds0_subsys: bus@56240000 {
8 compatible = "simple-bus"; 8 compatible = "simple-bus";
9 #address-cells = <1>; 9 #address-cells = <1>;
10 #size-cells = <1>; 10 #size-cells = <1>;
11 ranges = <0x56240000 0x0 0x56240000 0x 11 ranges = <0x56240000 0x0 0x56240000 0x10000>;
12 12
13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: 13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
14 compatible = "fsl,imx8qxp-lpcg 14 compatible = "fsl,imx8qxp-lpcg";
15 reg = <0x56243000 0x4>; 15 reg = <0x56243000 0x4>;
16 #clock-cells = <1>; 16 #clock-cells = <1>;
17 clock-output-names = "lvds0_li 17 clock-output-names = "lvds0_lis_lpcg_ipg_clk";
18 power-domains = <&pd IMX_SC_R_ 18 power-domains = <&pd IMX_SC_R_MIPI_1>;
19 }; 19 };
20 20
21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: 21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
22 compatible = "fsl,imx8qxp-lpcg 22 compatible = "fsl,imx8qxp-lpcg";
23 reg = <0x5624300c 0x4>; 23 reg = <0x5624300c 0x4>;
24 #clock-cells = <1>; 24 #clock-cells = <1>;
25 clock-output-names = "lvds0_pw 25 clock-output-names = "lvds0_pwm_lpcg_clk",
26 "lvds0_pw 26 "lvds0_pwm_lpcg_ipg_clk",
27 "lvds0_pw 27 "lvds0_pwm_lpcg_32k_clk";
28 power-domains = <&pd IMX_SC_R_ 28 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
29 }; 29 };
30 30
31 qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpc 31 qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
32 compatible = "fsl,imx8qxp-lpcg 32 compatible = "fsl,imx8qxp-lpcg";
33 reg = <0x56243010 0x4>; 33 reg = <0x56243010 0x4>;
34 #clock-cells = <1>; 34 #clock-cells = <1>;
35 clock-output-names = "lvds0_i2 35 clock-output-names = "lvds0_i2c0_lpcg_clk",
36 "lvds0_i2 36 "lvds0_i2c0_lpcg_ipg_clk";
37 power-domains = <&pd IMX_SC_R_ 37 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
38 }; 38 };
39 39
40 qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@ 40 qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
41 compatible = "fsl,imx8qxp-pwm" 41 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
42 reg = <0x56244000 0x1000>; 42 reg = <0x56244000 0x1000>;
43 clock-names = "ipg", "per"; 43 clock-names = "ipg", "per";
44 assigned-clocks = <&clk IMX_SC 44 assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
45 assigned-clock-rates = <240000 45 assigned-clock-rates = <24000000>;
46 #pwm-cells = <3>; 46 #pwm-cells = <3>;
47 power-domains = <&pd IMX_SC_R_ 47 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
48 status = "disabled"; 48 status = "disabled";
49 }; 49 };
50 50
51 qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2 51 qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
52 compatible = "fsl,imx8qxp-lpi2 52 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
53 reg = <0x56246000 0x1000>; 53 reg = <0x56246000 0x1000>;
54 #address-cells = <1>; 54 #address-cells = <1>;
55 #size-cells = <0>; 55 #size-cells = <0>;
56 interrupts = <8>; 56 interrupts = <8>;
57 clock-names = "per", "ipg"; 57 clock-names = "per", "ipg";
58 assigned-clocks = <&clk IMX_SC 58 assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
59 assigned-clock-rates = <240000 59 assigned-clock-rates = <24000000>;
60 power-domains = <&pd IMX_SC_R_ 60 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
61 status = "disabled"; 61 status = "disabled";
62 }; 62 };
63 }; 63 };
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