1 // SPDX-License-Identifier: GPL-2.0-only and M
2
3 /*
4 * Copyright 2024 NXP
5 */
6
7 lvds1_subsys: bus@57240000 {
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
12 ranges = <0x57240000 0x0 0x57240000 0x
13
14 irqsteer_lvds1: interrupt-controller@5
15 compatible = "fsl,imx8qm-irqst
16 reg = <0x57240000 0x1000>;
17 interrupts = <GIC_SPI 58 IRQ_T
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
21 clocks = <&lvds1_lis_lpcg IMX_
22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_
24 fsl,channel = <0>;
25 fsl,num-irqs = <32>;
26 };
27
28 lvds1_lis_lpcg: clock-controller@57243
29 compatible = "fsl,imx8qxp-lpcg
30 reg = <0x57243000 0x4>;
31 #clock-cells = <1>;
32 clocks = <&lvds_ipg_clk>;
33 clock-indices = <IMX_LPCG_CLK_
34 clock-output-names = "lvds1_li
35 power-domains = <&pd IMX_SC_R_
36 };
37
38 lvds1_pwm_lpcg: clock-controller@57243
39 compatible = "fsl,imx8qxp-lpcg
40 reg = <0x5724300c 0x4>;
41 #clock-cells = <1>;
42 clocks = <&clk IMX_SC_R_LVDS_1
43 <&lvds_ipg_clk>;
44 clock-indices = <IMX_LPCG_CLK_
45 clock-output-names = "lvds1_pw
46 "lvds1_pw
47 power-domains = <&pd IMX_SC_R_
48 };
49
50 lvds1_i2c0_lpcg: clock-controller@5724
51 compatible = "fsl,imx8qxp-lpcg
52 reg = <0x57243010 0x4>;
53 #clock-cells = <1>;
54 clocks = <&clk IMX_SC_R_LVDS_1
55 <&lvds_ipg_clk>;
56 clock-indices = <IMX_LPCG_CLK_
57 clock-output-names = "lvds1_i2
58 "lvds1_i2
59 power-domains = <&pd IMX_SC_R_
60 };
61
62 lvds1_i2c1_lpcg: clock-controller@5724
63 compatible = "fsl,imx8qxp-lpcg
64 reg = <0x57243014 0x4>;
65 #clock-cells = <1>;
66 clocks = <&clk IMX_SC_R_LVDS_1
67 <&lvds_ipg_clk>;
68 clock-indices = <IMX_LPCG_CLK_
69 clock-output-names = "lvds1_i2
70 "lvds1_i2
71 power-domains = <&pd IMX_SC_R_
72 };
73
74 pwm_lvds1: pwm@57244000 {
75 compatible = "fsl,imx8qxp-pwm"
76 reg = <0x57244000 0x1000>;
77 clocks = <&lvds1_pwm_lpcg IMX_
78 <&lvds1_pwm_lpcg IMX_
79 clock-names = "ipg", "per";
80 assigned-clocks = <&clk IMX_SC
81 assigned-clock-rates = <240000
82 #pwm-cells = <3>;
83 power-domains = <&pd IMX_SC_R_
84 status = "disabled";
85 };
86
87 i2c0_lvds1: i2c@57246000 {
88 compatible = "fsl,imx8qm-lpi2c
89 reg = <0x57246000 0x1000>;
90 #address-cells = <1>;
91 #size-cells = <0>;
92 interrupts = <8>;
93 clocks = <&lvds1_i2c0_lpcg IMX
94 <&lvds1_i2c0_lpcg IMX
95 clock-names = "per", "ipg";
96 assigned-clocks = <&clk IMX_SC
97 assigned-clock-rates = <240000
98 power-domains = <&pd IMX_SC_R_
99 status = "disabled";
100 };
101
102 i2c1_lvds1: i2c@57247000 {
103 compatible = "fsl,imx8qm-lpi2c
104 reg = <0x57247000 0x1000>;
105 interrupts = <9>;
106 clocks = <&lvds1_i2c1_lpcg IMX
107 <&lvds1_i2c1_lpcg IMX
108 clock-names = "per", "ipg";
109 assigned-clocks = <&clk IMX_SC
110 assigned-clock-rates = <240000
111 power-domains = <&pd IMX_SC_R_
112 status = "disabled";
113 };
114 };
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