1 // SPDX-License-Identifier: GPL-2.0-only and M 1 // SPDX-License-Identifier: GPL-2.0-only and MIT
2 2
3 /* 3 /*
4 * Copyright 2024 NXP 4 * Copyright 2024 NXP
5 */ 5 */
6 6
7 lvds1_subsys: bus@57240000 { 7 lvds1_subsys: bus@57240000 {
8 compatible = "simple-bus"; 8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>; 9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>; 10 #address-cells = <1>;
11 #size-cells = <1>; 11 #size-cells = <1>;
12 ranges = <0x57240000 0x0 0x57240000 0x 12 ranges = <0x57240000 0x0 0x57240000 0x10000>;
13 13
14 irqsteer_lvds1: interrupt-controller@5 14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqst 15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
16 reg = <0x57240000 0x1000>; 16 reg = <0x57240000 0x1000>;
17 interrupts = <GIC_SPI 58 IRQ_T 17 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
18 interrupt-controller; 18 interrupt-controller;
19 interrupt-parent = <&gic>; 19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>; 20 #interrupt-cells = <1>;
21 clocks = <&lvds1_lis_lpcg IMX_ 21 clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
22 clock-names = "ipg"; 22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_ 23 power-domains = <&pd IMX_SC_R_LVDS_1>;
24 fsl,channel = <0>; 24 fsl,channel = <0>;
25 fsl,num-irqs = <32>; 25 fsl,num-irqs = <32>;
26 }; 26 };
27 27
28 lvds1_lis_lpcg: clock-controller@57243 28 lvds1_lis_lpcg: clock-controller@57243000 {
29 compatible = "fsl,imx8qxp-lpcg 29 compatible = "fsl,imx8qxp-lpcg";
30 reg = <0x57243000 0x4>; 30 reg = <0x57243000 0x4>;
31 #clock-cells = <1>; 31 #clock-cells = <1>;
32 clocks = <&lvds_ipg_clk>; 32 clocks = <&lvds_ipg_clk>;
33 clock-indices = <IMX_LPCG_CLK_ 33 clock-indices = <IMX_LPCG_CLK_4>;
34 clock-output-names = "lvds1_li 34 clock-output-names = "lvds1_lis_lpcg_ipg_clk";
35 power-domains = <&pd IMX_SC_R_ 35 power-domains = <&pd IMX_SC_R_LVDS_1>;
36 }; 36 };
37 37
38 lvds1_pwm_lpcg: clock-controller@57243 38 lvds1_pwm_lpcg: clock-controller@5724300c {
39 compatible = "fsl,imx8qxp-lpcg 39 compatible = "fsl,imx8qxp-lpcg";
40 reg = <0x5724300c 0x4>; 40 reg = <0x5724300c 0x4>;
41 #clock-cells = <1>; 41 #clock-cells = <1>;
42 clocks = <&clk IMX_SC_R_LVDS_1 42 clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
43 <&lvds_ipg_clk>; 43 <&lvds_ipg_clk>;
44 clock-indices = <IMX_LPCG_CLK_ 44 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
45 clock-output-names = "lvds1_pw 45 clock-output-names = "lvds1_pwm_lpcg_clk",
46 "lvds1_pw 46 "lvds1_pwm_lpcg_ipg_clk";
47 power-domains = <&pd IMX_SC_R_ 47 power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
48 }; 48 };
49 49
50 lvds1_i2c0_lpcg: clock-controller@5724 50 lvds1_i2c0_lpcg: clock-controller@57243010 {
51 compatible = "fsl,imx8qxp-lpcg 51 compatible = "fsl,imx8qxp-lpcg";
52 reg = <0x57243010 0x4>; 52 reg = <0x57243010 0x4>;
53 #clock-cells = <1>; 53 #clock-cells = <1>;
54 clocks = <&clk IMX_SC_R_LVDS_1 54 clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
55 <&lvds_ipg_clk>; 55 <&lvds_ipg_clk>;
56 clock-indices = <IMX_LPCG_CLK_ 56 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
57 clock-output-names = "lvds1_i2 57 clock-output-names = "lvds1_i2c0_lpcg_clk",
58 "lvds1_i2 58 "lvds1_i2c0_lpcg_ipg_clk";
59 power-domains = <&pd IMX_SC_R_ 59 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
60 }; 60 };
61 61
62 lvds1_i2c1_lpcg: clock-controller@5724 62 lvds1_i2c1_lpcg: clock-controller@57243014 {
63 compatible = "fsl,imx8qxp-lpcg 63 compatible = "fsl,imx8qxp-lpcg";
64 reg = <0x57243014 0x4>; 64 reg = <0x57243014 0x4>;
65 #clock-cells = <1>; 65 #clock-cells = <1>;
66 clocks = <&clk IMX_SC_R_LVDS_1 66 clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
67 <&lvds_ipg_clk>; 67 <&lvds_ipg_clk>;
68 clock-indices = <IMX_LPCG_CLK_ 68 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
69 clock-output-names = "lvds1_i2 69 clock-output-names = "lvds1_i2c1_lpcg_clk",
70 "lvds1_i2 70 "lvds1_i2c1_lpcg_ipg_clk";
71 power-domains = <&pd IMX_SC_R_ 71 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
72 }; 72 };
73 73
74 pwm_lvds1: pwm@57244000 { 74 pwm_lvds1: pwm@57244000 {
75 compatible = "fsl,imx8qxp-pwm" 75 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
76 reg = <0x57244000 0x1000>; 76 reg = <0x57244000 0x1000>;
77 clocks = <&lvds1_pwm_lpcg IMX_ 77 clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
78 <&lvds1_pwm_lpcg IMX_ 78 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
79 clock-names = "ipg", "per"; 79 clock-names = "ipg", "per";
80 assigned-clocks = <&clk IMX_SC 80 assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <240000 81 assigned-clock-rates = <24000000>;
82 #pwm-cells = <3>; 82 #pwm-cells = <3>;
83 power-domains = <&pd IMX_SC_R_ 83 power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
84 status = "disabled"; 84 status = "disabled";
85 }; 85 };
86 86
87 i2c0_lvds1: i2c@57246000 { 87 i2c0_lvds1: i2c@57246000 {
88 compatible = "fsl,imx8qm-lpi2c 88 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
89 reg = <0x57246000 0x1000>; 89 reg = <0x57246000 0x1000>;
90 #address-cells = <1>; 90 #address-cells = <1>;
91 #size-cells = <0>; 91 #size-cells = <0>;
92 interrupts = <8>; 92 interrupts = <8>;
93 clocks = <&lvds1_i2c0_lpcg IMX 93 clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
94 <&lvds1_i2c0_lpcg IMX 94 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
95 clock-names = "per", "ipg"; 95 clock-names = "per", "ipg";
96 assigned-clocks = <&clk IMX_SC 96 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
97 assigned-clock-rates = <240000 97 assigned-clock-rates = <24000000>;
98 power-domains = <&pd IMX_SC_R_ 98 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
99 status = "disabled"; 99 status = "disabled";
100 }; 100 };
101 101
102 i2c1_lvds1: i2c@57247000 { 102 i2c1_lvds1: i2c@57247000 {
103 compatible = "fsl,imx8qm-lpi2c 103 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
104 reg = <0x57247000 0x1000>; 104 reg = <0x57247000 0x1000>;
105 interrupts = <9>; 105 interrupts = <9>;
106 clocks = <&lvds1_i2c1_lpcg IMX 106 clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
107 <&lvds1_i2c1_lpcg IMX 107 <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
108 clock-names = "per", "ipg"; 108 clock-names = "per", "ipg";
109 assigned-clocks = <&clk IMX_SC 109 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
110 assigned-clock-rates = <240000 110 assigned-clock-rates = <24000000>;
111 power-domains = <&pd IMX_SC_R_ 111 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
112 status = "disabled"; 112 status = "disabled";
113 }; 113 };
114 }; 114 };
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