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TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-mipi1.dtsi

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Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-mipi1.dtsi (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/freescale/imx8-ss-mipi1.dtsi (Version linux-5.7.19)


  1 // SPDX-License-Identifier: GPL-2.0-only and M    
  2                                                   
  3 /*                                                
  4  * Copyright 2024 NXP                             
  5  */                                               
  6                                                   
  7 mipi1_subsys: bus@57220000 {                      
  8         compatible = "simple-bus";                
  9         interrupt-parent = <&irqsteer_mipi1>;     
 10         #address-cells = <1>;                     
 11         #size-cells = <1>;                        
 12         ranges = <0x57220000 0x0 0x57220000 0x    
 13                                                   
 14         irqsteer_mipi1: interrupt-controller@5    
 15                 compatible = "fsl,imx8qm-irqst    
 16                 reg = <0x57220000 0x1000>;        
 17                 interrupts = <GIC_SPI 60 IRQ_T    
 18                 interrupt-controller;             
 19                 interrupt-parent = <&gic>;        
 20                 #interrupt-cells = <1>;           
 21                 clocks = <&mipi1_lis_lpcg IMX_    
 22                 clock-names = "ipg";              
 23                 power-domains = <&pd IMX_SC_R_    
 24                 fsl,channel = <0>;                
 25                 fsl,num-irqs = <32>;              
 26         };                                        
 27                                                   
 28         mipi1_lis_lpcg: clock-controller@57223    
 29                 compatible = "fsl,imx8qxp-lpcg    
 30                 reg = <0x57223000 0x4>;           
 31                 #clock-cells = <1>;               
 32                 clocks = <&dsi_ipg_clk>;          
 33                 clock-indices = <IMX_LPCG_CLK_    
 34                 clock-output-names = "mipi1_li    
 35                 power-domains = <&pd IMX_SC_R_    
 36         };                                        
 37                                                   
 38         mipi1_pwm_lpcg: clock-controller@57223    
 39                 compatible = "fsl,imx8qxp-lpcg    
 40                 reg = <0x5722300c 0x4>;           
 41                 #clock-cells = <1>;               
 42                 clocks = <&clk IMX_SC_R_MIPI_1    
 43                          <&dsi_ipg_clk>;          
 44                 clock-indices = <IMX_LPCG_CLK_    
 45                 clock-output-names = "mipi1_pw    
 46                                      "mipi1_pw    
 47                 power-domains = <&pd IMX_SC_R_    
 48         };                                        
 49                                                   
 50         mipi1_i2c0_lpcg_clk: clock-controller@    
 51                 compatible = "fsl,imx8qxp-lpcg    
 52                 reg = <0x5722301c 0x4>;           
 53                 #clock-cells = <1>;               
 54                 clocks = <&clk IMX_SC_R_MIPI_1    
 55                 clock-indices = <IMX_LPCG_CLK_    
 56                 clock-output-names = "mipi1_i2    
 57                 power-domains = <&pd IMX_SC_R_    
 58         };                                        
 59                                                   
 60         mipi1_i2c0_lpcg_ipg_clk: clock-control    
 61                 compatible = "fsl,imx8qxp-lpcg    
 62                 reg = <0x57223014 0x4>;           
 63                 #clock-cells = <1>;               
 64                 clocks = <&mipi1_i2c0_lpcg_ipg    
 65                 clock-indices = <IMX_LPCG_CLK_    
 66                 clock-output-names = "mipi1_i2    
 67                 power-domains = <&pd IMX_SC_R_    
 68         };                                        
 69                                                   
 70         mipi1_i2c0_lpcg_ipg_s_clk: clock-contr    
 71                 compatible = "fsl,imx8qxp-lpcg    
 72                 reg = <0x57223018 0x4>;           
 73                 #clock-cells = <1>;               
 74                 clocks = <&dsi_ipg_clk>;          
 75                 clock-indices = <IMX_LPCG_CLK_    
 76                 clock-output-names = "mipi1_i2    
 77                 power-domains = <&pd IMX_SC_R_    
 78         };                                        
 79                                                   
 80         mipi1_i2c1_lpcg_ipg_clk: clock-control    
 81                 compatible = "fsl,imx8qxp-lpcg    
 82                 reg = <0x57223024 0x4>;           
 83                 #clock-cells = <1>;               
 84                 clocks = <&mipi1_i2c1_lpcg_ipg    
 85                 clock-indices = <IMX_LPCG_CLK_    
 86                 clock-output-names = "mipi1_i2    
 87                 power-domains = <&pd IMX_SC_R_    
 88         };                                        
 89                                                   
 90         mipi1_i2c1_lpcg_ipg_s_clk: clock-contr    
 91                 compatible = "fsl,imx8qxp-lpcg    
 92                 reg = <0x57223028 0x4>;           
 93                 #clock-cells = <1>;               
 94                 clocks = <&dsi_ipg_clk>;          
 95                 clock-indices = <IMX_LPCG_CLK_    
 96                 clock-output-names = "mipi1_i2    
 97                 power-domains = <&pd IMX_SC_R_    
 98         };                                        
 99                                                   
100         mipi1_i2c1_lpcg_clk: clock-controller@    
101                 compatible = "fsl,imx8qxp-lpcg    
102                 reg = <0x5722302c 0x4>;           
103                 #clock-cells = <1>;               
104                 clocks = <&clk IMX_SC_R_MIPI_1    
105                 clock-indices = <IMX_LPCG_CLK_    
106                 clock-output-names = "mipi1_i2    
107                 power-domains = <&pd IMX_SC_R_    
108         };                                        
109                                                   
110         pwm_mipi1: pwm@57224000 {                 
111                 compatible = "fsl,imx8qxp-pwm"    
112                 reg = <0x57224000 0x1000>;        
113                 clocks = <&mipi1_pwm_lpcg IMX_    
114                          <&mipi1_pwm_lpcg IMX_    
115                 clock-names = "ipg", "per";       
116                 assigned-clocks = <&clk IMX_SC    
117                 assigned-clock-rates = <240000    
118                 #pwm-cells = <3>;                 
119                 power-domains = <&pd IMX_SC_R_    
120                 status = "disabled";              
121         };                                        
122                                                   
123         i2c0_mipi1: i2c@57226000 {                
124                 compatible = "fsl,imx8qm-lpi2c    
125                 reg = <0x57226000 0x1000>;        
126                 #address-cells = <1>;             
127                 #size-cells = <0>;                
128                 interrupts = <8>;                 
129                 interrupt-parent = <&irqsteer_    
130                 clocks = <&mipi1_i2c0_lpcg_clk    
131                          <&mipi1_i2c0_lpcg_ipg    
132                 clock-names = "per", "ipg";       
133                 assigned-clocks = <&mipi1_i2c0    
134                 assigned-clock-rates = <240000    
135                 power-domains = <&pd IMX_SC_R_    
136                 status = "disabled";              
137         };                                        
138 };                                                
                                                      

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