1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2019~2020, 2022 NXP
4 */
5
6 /dts-v1/;
7
8 #include "imx8dxl.dtsi"
9
10 / {
11 model = "Freescale i.MX8DXL EVK";
12 compatible = "fsl,imx8dxl-evk", "fsl,i
13
14 aliases {
15 i2c2 = &i2c2;
16 mmc0 = &usdhc1;
17 mmc1 = &usdhc2;
18 serial0 = &lpuart0;
19 serial1 = &lpuart1;
20 serial6 = &cm40_lpuart;
21 };
22
23 chosen {
24 stdout-path = &lpuart0;
25 };
26
27 imx8dxl-cm4 {
28 compatible = "fsl,imx8qxp-cm4"
29 clocks = <&clk_dummy>;
30 mbox-names = "tx", "rx", "rxdb
31 mboxes = <&lsio_mu5 0 1 &lsio_
32 memory-region = <&vdevbuffer>,
33 <&vdev1vring0>
34 power-domains = <&pd IMX_SC_R_
35 fsl,resource-id = <IMX_SC_R_M4
36 fsl,entry-address = <0x34fe000
37 };
38
39
40 memory@80000000 {
41 device_type = "memory";
42 reg = <0x00000000 0x80000000 0
43 };
44
45 reserved-memory {
46 #address-cells = <2>;
47 #size-cells = <2>;
48 ranges;
49
50 /*
51 * Memory reserved for optee u
52 * This will be automatically
53 * optee@96000000 {
54 * reg = <0 0x96000000 0 0
55 * no-map;
56 * };
57 */
58
59 /* global autoconfigured regio
60 linux,cma {
61 compatible = "shared-d
62 reusable;
63 size = <0 0x14000000>;
64 alloc-ranges = <0 0x98
65 linux,cma-default;
66 };
67
68 vdev0vring0: memory0@90000000
69 reg = <0 0x90000000 0
70 no-map;
71 };
72
73 vdev0vring1: memory@90008000 {
74 reg = <0 0x90008000 0
75 no-map;
76 };
77
78 vdev1vring0: memory@90010000 {
79 reg = <0 0x90010000 0
80 no-map;
81 };
82
83 vdev1vring1: memory@90018000 {
84 reg = <0 0x90018000 0
85 no-map;
86 };
87
88 rsc_table: memory-rsc-table@90
89 reg = <0 0x900ff000 0
90 no-map;
91 };
92
93 vdevbuffer: memory-vdevbuffer@
94 compatible = "shared-d
95 reg = <0 0x90400000 0
96 no-map;
97 };
98 };
99
100 m2_uart1_sel: regulator-m2uart1sel {
101 compatible = "regulator-fixed"
102 regulator-min-microvolt = <330
103 regulator-max-microvolt = <330
104 regulator-name = "m2_uart1_sel
105 gpio = <&pca6416_1 6 GPIO_ACTI
106 enable-active-high;
107 regulator-always-on;
108 };
109
110 mux3_en: regulator-0 {
111 compatible = "regulator-fixed"
112 regulator-min-microvolt = <330
113 regulator-max-microvolt = <330
114 regulator-name = "mux3_en";
115 gpio = <&pca6416_2 8 GPIO_ACTI
116 regulator-always-on;
117 };
118
119 reg_fec1_sel: regulator-1 {
120 compatible = "regulator-fixed"
121 regulator-name = "fec1_supply"
122 regulator-min-microvolt = <330
123 regulator-max-microvolt = <330
124 gpio = <&pca6416_1 11 GPIO_ACT
125 regulator-always-on;
126 status = "disabled";
127 };
128
129 reg_fec1_io: regulator-2 {
130 compatible = "regulator-fixed"
131 regulator-name = "fec1_io_supp
132 regulator-min-microvolt = <180
133 regulator-max-microvolt = <180
134 gpio = <&max7322 0 GPIO_ACTIVE
135 enable-active-high;
136 regulator-always-on;
137 status = "disabled";
138 };
139
140 reg_can0_stby: regulator-4 {
141 compatible = "regulator-fixed"
142 regulator-name = "can0-stby";
143 regulator-min-microvolt = <330
144 regulator-max-microvolt = <330
145 gpio = <&pca6416_3 0 GPIO_ACTI
146 enable-active-high;
147 };
148
149 reg_can1_stby: regulator-5 {
150 compatible = "regulator-fixed"
151 regulator-name = "can1-stby";
152 regulator-min-microvolt = <330
153 regulator-max-microvolt = <330
154 gpio = <&pca6416_3 1 GPIO_ACTI
155 enable-active-high;
156 };
157
158 reg_usdhc2_vmmc: regulator-3 {
159 compatible = "regulator-fixed"
160 regulator-name = "SD1_SPWR";
161 regulator-min-microvolt = <300
162 regulator-max-microvolt = <300
163 gpio = <&lsio_gpio4 30 GPIO_AC
164 enable-active-high;
165 off-on-delay-us = <3480>;
166 };
167
168 reg_vref_1v8: regulator-adc-vref {
169 compatible = "regulator-fixed"
170 regulator-name = "vref_1v8";
171 regulator-min-microvolt = <180
172 regulator-max-microvolt = <180
173 };
174
175 mii_select: regulator-4 {
176 compatible = "regulator-fixed"
177 regulator-name = "mii-select";
178 regulator-min-microvolt = <330
179 regulator-max-microvolt = <330
180 gpio = <&scu_gpio 6 GPIO_ACTIV
181 enable-active-high;
182 regulator-always-on;
183 };
184
185 bt_sco_codec: audio-codec-bt {
186 compatible = "linux,bt-sco";
187 #sound-dai-cells = <1>;
188 };
189
190 sound-bt-sco {
191 compatible = "simple-audio-car
192 simple-audio-card,name = "bt-s
193 simple-audio-card,format = "ds
194 simple-audio-card,bitclock-inv
195 simple-audio-card,frame-master
196 simple-audio-card,bitclock-mas
197
198 btcpu: simple-audio-card,cpu {
199 sound-dai = <&sai0>;
200 dai-tdm-slot-num = <2>
201 dai-tdm-slot-width = <
202 };
203
204 simple-audio-card,codec {
205 sound-dai = <&bt_sco_c
206 };
207 };
208
209 sound-wm8960-1 {
210 compatible = "fsl,imx-audio-wm
211 model = "wm8960-audio";
212 audio-cpu = <&sai1>;
213 audio-codec = <&wm8960_1>;
214 audio-asrc = <&asrc0>;
215 audio-routing = "Headphone Jac
216 "Headphone Jac
217 "Ext Spk", "SP
218 "Ext Spk", "SP
219 "Ext Spk", "SP
220 "Ext Spk", "SP
221 "LINPUT1", "Mi
222 "Mic Jack", "M
223 };
224
225 sound-wm8960-2 {
226 compatible = "fsl,imx-audio-wm
227 model = "wm8960-audio-2";
228 audio-cpu = <&sai2>;
229 audio-codec = <&wm8960_2>;
230 audio-routing = "Headphone Jac
231 "Headphone Jac
232 "Ext Spk", "SP
233 "Ext Spk", "SP
234 "Ext Spk", "SP
235 "Ext Spk", "SP
236 "LINPUT1", "Mi
237 "Mic Jack", "M
238 };
239
240 sound-wm8960-3 {
241 compatible = "fsl,imx-audio-wm
242 model = "wm8960-audio-3";
243 audio-cpu = <&sai3>;
244 audio-codec = <&wm8960_3>;
245 audio-routing = "Headphone Jac
246 "Headphone Jac
247 "Ext Spk", "SP
248 "Ext Spk", "SP
249 "Ext Spk", "SP
250 "Ext Spk", "SP
251 "LINPUT1", "Mi
252 "Mic Jack", "M
253 };
254 };
255
256 &adc0 {
257 vref-supply = <®_vref_1v8>;
258 status = "okay";
259 };
260
261 &asrc0 {
262 fsl,asrc-rate = <48000>;
263 status = "okay";
264 };
265
266 &eqos {
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_eqos>;
269 phy-mode = "rgmii-id";
270 phy-handle = <ðphy0>;
271 nvmem-cells = <&fec_mac1>;
272 nvmem-cell-names = "mac-address";
273 status = "okay";
274
275 mdio {
276 compatible = "snps,dwmac-mdio"
277 #address-cells = <1>;
278 #size-cells = <0>;
279
280 ethphy0: ethernet-phy@0 {
281 compatible = "ethernet
282 reg = <0>;
283 eee-broken-1000t;
284 qca,disable-smarteee;
285 qca,disable-hibernatio
286 reset-gpios = <&pca641
287 reset-assert-us = <20>
288 reset-deassert-us = <2
289 vddio-supply = <&vddio
290
291 vddio0: vddio-regulato
292 regulator-min-
293 regulator-max-
294 };
295 };
296 };
297 };
298
299 /*
300 * fec1 shares the some PINs with usdhc2.
301 * by default usdhc2 is enabled in this dts.
302 * Please disable usdhc2 to enable fec1
303 */
304 &fec1 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_fec1>;
307 phy-mode = "rgmii-txid";
308 phy-handle = <ðphy1>;
309 fsl,magic-packet;
310 rx-internal-delay-ps = <2000>;
311 nvmem-cells = <&fec_mac0>;
312 nvmem-cell-names = "mac-address";
313 status = "disabled";
314
315 mdio {
316 #address-cells = <1>;
317 #size-cells = <0>;
318
319 ethphy1: ethernet-phy@1 {
320 compatible = "ethernet
321 reg = <1>;
322 reset-gpios = <&pca641
323 reset-assert-us = <100
324 qca,disable-smarteee;
325 vddio-supply = <&vddio
326
327 vddio1: vddio-regulato
328 regulator-min-
329 regulator-max-
330 };
331 };
332 };
333 };
334
335 &flexspi0 {
336 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_flexspi0>;
338 status = "okay";
339
340 mt35xu512aba0: flash@0 {
341 reg = <0>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 compatible = "jedec,spi-nor";
345 spi-max-frequency = <133000000
346 spi-tx-bus-width = <8>;
347 spi-rx-bus-width = <8>;
348 };
349 };
350
351 &i2c2 {
352 #address-cells = <1>;
353 #size-cells = <0>;
354 clock-frequency = <100000>;
355 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>;
357 status = "okay";
358
359 pca6416_1: gpio@20 {
360 compatible = "ti,tca6416";
361 reg = <0x20>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 };
365
366 pca6416_2: gpio@21 {
367 compatible = "ti,tca6416";
368 reg = <0x21>;
369 gpio-controller;
370 #gpio-cells = <2>;
371 };
372
373 pca9548_1: i2c-mux@70 {
374 compatible = "nxp,pca9548";
375 #address-cells = <1>;
376 #size-cells = <0>;
377 reg = <0x70>;
378
379 i2c@0 {
380 #address-cells = <1>;
381 #size-cells = <0>;
382 reg = <0x0>;
383
384 max7322: gpio@68 {
385 compatible = "
386 reg = <0x68>;
387 gpio-controlle
388 #gpio-cells =
389 status = "disa
390 };
391 };
392
393 i2c@1 {
394 #address-cells = <1>;
395 #size-cells = <0>;
396 reg = <0x1>;
397
398 wm8960_1: audio-codec@
399 compatible = "
400 reg = <0x1a>;
401 clocks = <&mcl
402 clock-names =
403 assigned-clock
404
405
406
407 assigned-clock
408
409
410
411 wlf,shared-lrc
412 wlf,hp-cfg = <
413 wlf,gpio-cfg =
414 };
415 };
416
417 i2c@2 {
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <0x2>;
421
422 wm8960_2: audio-codec@
423 compatible = "
424 reg = <0x1a>;
425 clocks = <&mcl
426 clock-names =
427 assigned-clock
428
429
430
431 assigned-clock
432
433
434
435 wlf,shared-lrc
436 wlf,hp-cfg = <
437 wlf,gpio-cfg =
438 };
439 };
440
441 i2c@3 {
442 #address-cells = <1>;
443 #size-cells = <0>;
444 reg = <0x3>;
445
446 wm8960_3: audio-codec@
447 compatible = "
448 reg = <0x1a>;
449 clocks = <&mcl
450 clock-names =
451 assigned-clock
452
453
454
455 assigned-clock
456
457
458
459 wlf,shared-lrc
460 wlf,hp-cfg = <
461 wlf,gpio-cfg =
462 };
463 };
464
465 i2c@4 {
466 #address-cells = <1>;
467 #size-cells = <0>;
468 reg = <0x4>;
469 };
470
471 i2c@5 {
472 #address-cells = <1>;
473 #size-cells = <0>;
474 reg = <0x5>;
475 };
476
477 i2c@6 {
478 #address-cells = <1>;
479 #size-cells = <0>;
480 reg = <0x6>;
481 };
482 };
483 };
484
485 &i2c3 {
486 #address-cells = <1>;
487 #size-cells = <0>;
488 clock-frequency = <100000>;
489 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_i2c3>;
491 status = "okay";
492
493 pca6416_3: gpio@20 {
494 compatible = "ti,tca6416";
495 reg = <0x20>;
496 gpio-controller;
497 #gpio-cells = <2>;
498 interrupt-parent = <&lsio_gpio
499 interrupts = <5 IRQ_TYPE_EDGE_
500 };
501
502 pca9548_2: i2c-mux@70 {
503 compatible = "nxp,pca9548";
504 reg = <0x70>;
505 #address-cells = <1>;
506 #size-cells = <0>;
507
508 i2c@0 {
509 #address-cells = <1>;
510 #size-cells = <0>;
511 reg = <0x0>;
512 };
513
514 i2c@1 {
515 #address-cells = <1>;
516 #size-cells = <0>;
517 reg = <0x1>;
518 };
519
520 i2c@2 {
521 #address-cells = <1>;
522 #size-cells = <0>;
523 reg = <0x2>;
524 };
525
526 i2c@3 {
527 #address-cells = <1>;
528 #size-cells = <0>;
529 reg = <0x3>;
530 };
531
532 i2c@4 {
533 #address-cells = <1>;
534 #size-cells = <0>;
535 reg = <0x4>;
536 };
537 };
538 };
539
540 &lpuart0 {
541 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_lpuart0>;
543 status = "okay";
544 };
545
546 &lpuart1 {
547 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_lpuart1>;
549 status = "okay";
550 };
551
552 &lsio_mu5 {
553 status = "okay";
554 };
555
556 &flexcan2 {
557 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_flexcan2>;
559 xceiver-supply = <®_can0_stby>;
560 status = "okay";
561 };
562
563 &flexcan3 {
564 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_flexcan3>;
566 xceiver-supply = <®_can1_stby>;
567 status = "okay";
568 };
569
570 &cm40_intmux {
571 status = "disabled";
572 };
573
574 &cm40_lpuart {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_cm40_lpuart>;
577 status = "disabled";
578 };
579
580 &lsio_gpio4 {
581 status = "okay";
582 };
583
584 &lsio_gpio5 {
585 status = "okay";
586 };
587
588 &sai0 {
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_sai0>;
591 #sound-dai-cells = <0>;
592 assigned-clocks = <&clk IMX_SC_R_AUDIO
593 <&clk IMX_SC_R_AUDIO
594 <&clk IMX_SC_R_AUDIO
595 <&sai0_lpcg IMX_LPCG
596 assigned-clock-rates = <786432000>, <4
597 status = "okay";
598 };
599
600 &sai1 {
601 assigned-clocks = <&clk IMX_SC_R_AUDIO
602 <&clk IMX_SC_R_AUDIO
603 <&clk IMX_SC_R_AUDIO
604 <&sai1_lpcg IMX_LPCG
605 assigned-clock-rates = <786432000>, <4
606 pinctrl-names = "default";
607 pinctrl-0 = <&pinctrl_sai1>;
608 status = "okay";
609 };
610
611 &sai2 {
612 assigned-clocks = <&clk IMX_SC_R_AUDIO
613 <&clk IMX_SC_R_AUDIO
614 <&clk IMX_SC_R_AUDIO
615 <&sai2_lpcg IMX_LPCG
616 assigned-clock-rates = <786432000>, <4
617 pinctrl-names = "default";
618 pinctrl-0 = <&pinctrl_sai2>;
619 fsl,sai-asynchronous;
620 status = "okay";
621 };
622
623 &sai3 {
624 assigned-clocks = <&clk IMX_SC_R_AUDIO
625 <&clk IMX_SC_R_AUDIO
626 <&clk IMX_SC_R_AUDIO
627 <&sai3_lpcg IMX_LPCG
628 assigned-clock-rates = <786432000>, <4
629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_sai3>;
631 fsl,sai-asynchronous;
632 status = "okay";
633 };
634
635 &thermal_zones {
636 pmic-thermal {
637 polling-delay-passive = <250>;
638 polling-delay = <2000>;
639 thermal-sensors = <&tsens IMX_
640
641 trips {
642 pmic_alert0: trip0 {
643 temperature =
644 hysteresis = <
645 type = "passiv
646 };
647
648 pmic_crit0: trip1 {
649 temperature =
650 hysteresis = <
651 type = "critic
652 };
653 };
654
655 cooling-maps {
656 map0 {
657 trip = <&pmic_
658 cooling-device
659 <&A35_
660 <&A35_
661 };
662 };
663 };
664 };
665
666 &usbphy1 {
667 /* USB eye diagram tests result */
668 fsl,tx-d-cal = <114>;
669 status = "okay";
670 };
671
672 &usbotg1 {
673 pinctrl-names = "default";
674 pinctrl-0 = <&pinctrl_usbotg1>;
675 srp-disable;
676 hnp-disable;
677 adp-disable;
678 power-active-high;
679 disable-over-current;
680 status = "okay";
681 };
682
683 &usbphy2 {
684 /* USB eye diagram tests result */
685 fsl,tx-d-cal = <111>;
686 status = "okay";
687 };
688
689 &usbotg2 {
690 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_usbotg2>;
692 srp-disable;
693 hnp-disable;
694 adp-disable;
695 power-active-high;
696 disable-over-current;
697 status = "okay";
698 };
699
700 &usdhc1 {
701 pinctrl-names = "default";
702 pinctrl-0 = <&pinctrl_usdhc1>;
703 bus-width = <8>;
704 no-sd;
705 no-sdio;
706 non-removable;
707 status = "okay";
708 };
709
710 &usdhc2 {
711 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
713 bus-width = <4>;
714 vmmc-supply = <®_usdhc2_vmmc>;
715 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_
716 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_
717 status = "okay";
718 };
719
720 &lpspi3 {
721 fsl,spi-only-use-cs1-sel;
722 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_lpspi3>;
724 status = "okay";
725 };
726
727 &iomuxc {
728 pinctrl-names = "default";
729 pinctrl-0 = <&pinctrl_hog>;
730
731 pinctrl_hog: hoggrp {
732 fsl,pins = <
733 IMX8DXL_COMP_CTL_GPIO_
734 IMX8DXL_COMP_CTL_GPIO_
735 IMX8DXL_SPI3_CS0_ADMA_
736 IMX8DXL_SNVS_TAMPER_OU
737 >;
738 };
739
740 pinctrl_usbotg1: usbotg1grp {
741 fsl,pins = <
742 IMX8DXL_USB_SS3_TC0_CO
743 >;
744 };
745
746 pinctrl_usbotg2: usbotg2grp {
747 fsl,pins = <
748 IMX8DXL_USB_SS3_TC1_CO
749 >;
750 };
751
752 pinctrl_eqos: eqosgrp {
753 fsl,pins = <
754 IMX8DXL_ENET0_MDC_CONN
755 IMX8DXL_ENET0_MDIO_CON
756 IMX8DXL_ENET1_RGMII_RX
757 IMX8DXL_ENET1_RGMII_RX
758 IMX8DXL_ENET1_RGMII_RX
759 IMX8DXL_ENET1_RGMII_RX
760 IMX8DXL_ENET1_RGMII_RX
761 IMX8DXL_ENET1_RGMII_RX
762 IMX8DXL_ENET1_RGMII_TX
763 IMX8DXL_ENET1_RGMII_TX
764 IMX8DXL_ENET1_RGMII_TX
765 IMX8DXL_ENET1_RGMII_TX
766 IMX8DXL_ENET1_RGMII_TX
767 IMX8DXL_ENET1_RGMII_TX
768 >;
769 };
770
771 pinctrl_flexspi0: flexspi0grp {
772 fsl,pins = <
773 IMX8DXL_QSPI0A_DATA0_L
774 IMX8DXL_QSPI0A_DATA1_L
775 IMX8DXL_QSPI0A_DATA2_L
776 IMX8DXL_QSPI0A_DATA3_L
777 IMX8DXL_QSPI0A_DQS_LSI
778 IMX8DXL_QSPI0A_SS0_B_L
779 IMX8DXL_QSPI0A_SCLK_LS
780 IMX8DXL_QSPI0B_SCLK_LS
781 IMX8DXL_QSPI0B_DATA0_L
782 IMX8DXL_QSPI0B_DATA1_L
783 IMX8DXL_QSPI0B_DATA2_L
784 IMX8DXL_QSPI0B_DATA3_L
785 IMX8DXL_QSPI0B_DQS_LSI
786 IMX8DXL_QSPI0B_SS0_B_L
787 >;
788 };
789
790 pinctrl_flexcan2: flexcan2grp {
791 fsl,pins = <
792 IMX8DXL_UART2_TX_ADMA_
793 IMX8DXL_UART2_RX_ADMA_
794 >;
795 };
796
797 pinctrl_flexcan3: flexcan3grp {
798 fsl,pins = <
799 IMX8DXL_FLEXCAN2_TX_AD
800 IMX8DXL_FLEXCAN2_RX_AD
801 >;
802 };
803
804 pinctrl_fec1: fec1grp {
805 fsl,pins = <
806 IMX8DXL_COMP_CTL_GPIO_
807 IMX8DXL_COMP_CTL_GPIO_
808 IMX8DXL_ENET0_MDC_CONN
809 IMX8DXL_ENET0_MDIO_CON
810 IMX8DXL_ENET0_RGMII_RX
811 IMX8DXL_ENET0_RGMII_RX
812 IMX8DXL_ENET0_RGMII_RX
813 IMX8DXL_ENET0_RGMII_RX
814 IMX8DXL_ENET0_RGMII_RX
815 IMX8DXL_ENET0_RGMII_RX
816 IMX8DXL_ENET0_RGMII_TX
817 IMX8DXL_ENET0_RGMII_TX
818 IMX8DXL_ENET0_RGMII_TX
819 IMX8DXL_ENET0_RGMII_TX
820 IMX8DXL_ENET0_RGMII_TX
821 IMX8DXL_ENET0_RGMII_TX
822 >;
823 };
824
825 pinctrl_lpspi3: lpspi3grp {
826 fsl,pins = <
827 IMX8DXL_SPI3_SCK_ADMA_
828 IMX8DXL_SPI3_SDO_ADMA_
829 IMX8DXL_SPI3_SDI_ADMA_
830 IMX8DXL_SPI3_CS1_ADMA_
831 >;
832 };
833
834 pinctrl_i2c2: i2c2grp {
835 fsl,pins = <
836 IMX8DXL_SPI1_SCK_ADMA_
837 IMX8DXL_SPI1_SDO_ADMA_
838 >;
839 };
840
841 pinctrl_cm40_lpuart: cm40lpuartgrp {
842 fsl,pins = <
843 IMX8DXL_ADC_IN2_M40_UA
844 IMX8DXL_ADC_IN3_M40_UA
845 >;
846 };
847
848 pinctrl_i2c3: i2c3grp {
849 fsl,pins = <
850 IMX8DXL_SPI1_CS0_ADMA_
851 IMX8DXL_SPI1_SDI_ADMA_
852 >;
853 };
854
855 pinctrl_lpuart0: lpuart0grp {
856 fsl,pins = <
857 IMX8DXL_UART0_RX_ADMA_
858 IMX8DXL_UART0_TX_ADMA_
859 >;
860 };
861
862 pinctrl_lpuart1: lpuart1grp {
863 fsl,pins = <
864 IMX8DXL_UART1_TX_ADMA_
865 IMX8DXL_UART1_RX_ADMA_
866 IMX8DXL_UART1_RTS_B_AD
867 IMX8DXL_UART1_CTS_B_AD
868 >;
869 };
870
871 pinctrl_sai0: sai0grp {
872 fsl,pins = <
873 IMX8DXL_SPI0_CS0_ADMA_
874 IMX8DXL_SPI0_CS1_ADMA_
875 IMX8DXL_SPI0_SCK_ADMA_
876 IMX8DXL_SPI0_SDI_ADMA_
877 IMX8DXL_SPI0_SDO_ADMA_
878 >;
879 };
880
881 pinctrl_sai1: sai1grp {
882 fsl,pins = <
883 IMX8DXL_FLEXCAN0_RX_AD
884 IMX8DXL_FLEXCAN0_TX_AD
885 IMX8DXL_FLEXCAN1_RX_AD
886 IMX8DXL_FLEXCAN1_TX_AD
887 >;
888 };
889
890 pinctrl_sai2: sai2grp {
891 fsl,pins = <
892 IMX8DXL_SNVS_TAMPER_OU
893 IMX8DXL_SNVS_TAMPER_IN
894 IMX8DXL_SNVS_TAMPER_OU
895 >;
896 };
897
898 pinctrl_sai3: sai3grp {
899 fsl,pins = <
900 IMX8DXL_SNVS_TAMPER_IN
901 IMX8DXL_SNVS_TAMPER_IN
902 IMX8DXL_SNVS_TAMPER_IN
903 >;
904 };
905
906 pinctrl_usdhc1: usdhc1grp {
907 fsl,pins = <
908 IMX8DXL_EMMC0_CLK_CONN
909 IMX8DXL_EMMC0_CMD_CONN
910 IMX8DXL_EMMC0_DATA0_CO
911 IMX8DXL_EMMC0_DATA1_CO
912 IMX8DXL_EMMC0_DATA2_CO
913 IMX8DXL_EMMC0_DATA3_CO
914 IMX8DXL_EMMC0_DATA4_CO
915 IMX8DXL_EMMC0_DATA5_CO
916 IMX8DXL_EMMC0_DATA6_CO
917 IMX8DXL_EMMC0_DATA7_CO
918 IMX8DXL_EMMC0_STROBE_C
919 >;
920 };
921
922 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
923 fsl,pins = <
924 IMX8DXL_ENET0_RGMII_TX
925 IMX8DXL_ENET0_RGMII_TX
926 IMX8DXL_ENET0_RGMII_TX
927 >;
928 };
929
930 pinctrl_usdhc2: usdhc2grp {
931 fsl,pins = <
932 IMX8DXL_ENET0_RGMII_RX
933 IMX8DXL_ENET0_RGMII_RX
934 IMX8DXL_ENET0_RGMII_RX
935 IMX8DXL_ENET0_RGMII_RX
936 IMX8DXL_ENET0_RGMII_RX
937 IMX8DXL_ENET0_RGMII_RX
938 IMX8DXL_ENET0_RGMII_TX
939 >;
940 };
941 };
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