1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019~2020, 2022 NXP 3 * Copyright 2019~2020, 2022 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8dxl.dtsi" 8 #include "imx8dxl.dtsi"
9 9
10 / { 10 / {
11 model = "Freescale i.MX8DXL EVK"; 11 model = "Freescale i.MX8DXL EVK";
12 compatible = "fsl,imx8dxl-evk", "fsl,i 12 compatible = "fsl,imx8dxl-evk", "fsl,imx8dxl";
13 13
14 aliases { 14 aliases {
15 i2c2 = &i2c2; 15 i2c2 = &i2c2;
16 mmc0 = &usdhc1; 16 mmc0 = &usdhc1;
17 mmc1 = &usdhc2; 17 mmc1 = &usdhc2;
18 serial0 = &lpuart0; 18 serial0 = &lpuart0;
19 serial1 = &lpuart1; 19 serial1 = &lpuart1;
20 serial6 = &cm40_lpuart; 20 serial6 = &cm40_lpuart;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &lpuart0; 24 stdout-path = &lpuart0;
25 }; 25 };
26 26
27 imx8dxl-cm4 { <<
28 compatible = "fsl,imx8qxp-cm4" <<
29 clocks = <&clk_dummy>; <<
30 mbox-names = "tx", "rx", "rxdb <<
31 mboxes = <&lsio_mu5 0 1 &lsio_ <<
32 memory-region = <&vdevbuffer>, <<
33 <&vdev1vring0> <<
34 power-domains = <&pd IMX_SC_R_ <<
35 fsl,resource-id = <IMX_SC_R_M4 <<
36 fsl,entry-address = <0x34fe000 <<
37 }; <<
38 <<
39 <<
40 memory@80000000 { 27 memory@80000000 {
41 device_type = "memory"; 28 device_type = "memory";
42 reg = <0x00000000 0x80000000 0 29 reg = <0x00000000 0x80000000 0 0x40000000>;
43 }; 30 };
44 31
45 reserved-memory { 32 reserved-memory {
46 #address-cells = <2>; 33 #address-cells = <2>;
47 #size-cells = <2>; 34 #size-cells = <2>;
48 ranges; 35 ranges;
49 36
50 /* 37 /*
51 * Memory reserved for optee u 38 * Memory reserved for optee usage. Please do not use.
52 * This will be automatically 39 * This will be automatically added to dtb if OP-TEE is installed.
53 * optee@96000000 { 40 * optee@96000000 {
54 * reg = <0 0x96000000 0 0 41 * reg = <0 0x96000000 0 0x2000000>;
55 * no-map; 42 * no-map;
56 * }; 43 * };
57 */ 44 */
58 45
59 /* global autoconfigured regio 46 /* global autoconfigured region for contiguous allocations */
60 linux,cma { 47 linux,cma {
61 compatible = "shared-d 48 compatible = "shared-dma-pool";
62 reusable; 49 reusable;
63 size = <0 0x14000000>; 50 size = <0 0x14000000>;
64 alloc-ranges = <0 0x98 51 alloc-ranges = <0 0x98000000 0 0x14000000>;
65 linux,cma-default; 52 linux,cma-default;
66 }; 53 };
67 <<
68 vdev0vring0: memory0@90000000 <<
69 reg = <0 0x90000000 0 <<
70 no-map; <<
71 }; <<
72 <<
73 vdev0vring1: memory@90008000 { <<
74 reg = <0 0x90008000 0 <<
75 no-map; <<
76 }; <<
77 <<
78 vdev1vring0: memory@90010000 { <<
79 reg = <0 0x90010000 0 <<
80 no-map; <<
81 }; <<
82 <<
83 vdev1vring1: memory@90018000 { <<
84 reg = <0 0x90018000 0 <<
85 no-map; <<
86 }; <<
87 <<
88 rsc_table: memory-rsc-table@90 <<
89 reg = <0 0x900ff000 0 <<
90 no-map; <<
91 }; <<
92 <<
93 vdevbuffer: memory-vdevbuffer@ <<
94 compatible = "shared-d <<
95 reg = <0 0x90400000 0 <<
96 no-map; <<
97 }; <<
98 }; 54 };
99 55
100 m2_uart1_sel: regulator-m2uart1sel { 56 m2_uart1_sel: regulator-m2uart1sel {
101 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
102 regulator-min-microvolt = <330 58 regulator-min-microvolt = <3300000>;
103 regulator-max-microvolt = <330 59 regulator-max-microvolt = <3300000>;
104 regulator-name = "m2_uart1_sel 60 regulator-name = "m2_uart1_sel";
105 gpio = <&pca6416_1 6 GPIO_ACTI 61 gpio = <&pca6416_1 6 GPIO_ACTIVE_HIGH>;
106 enable-active-high; 62 enable-active-high;
107 regulator-always-on; 63 regulator-always-on;
108 }; 64 };
109 65
110 mux3_en: regulator-0 { 66 mux3_en: regulator-0 {
111 compatible = "regulator-fixed" 67 compatible = "regulator-fixed";
112 regulator-min-microvolt = <330 68 regulator-min-microvolt = <3300000>;
113 regulator-max-microvolt = <330 69 regulator-max-microvolt = <3300000>;
114 regulator-name = "mux3_en"; 70 regulator-name = "mux3_en";
115 gpio = <&pca6416_2 8 GPIO_ACTI 71 gpio = <&pca6416_2 8 GPIO_ACTIVE_LOW>;
116 regulator-always-on; 72 regulator-always-on;
117 }; 73 };
118 74
119 reg_fec1_sel: regulator-1 { 75 reg_fec1_sel: regulator-1 {
120 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
121 regulator-name = "fec1_supply" 77 regulator-name = "fec1_supply";
122 regulator-min-microvolt = <330 78 regulator-min-microvolt = <3300000>;
123 regulator-max-microvolt = <330 79 regulator-max-microvolt = <3300000>;
124 gpio = <&pca6416_1 11 GPIO_ACT 80 gpio = <&pca6416_1 11 GPIO_ACTIVE_LOW>;
125 regulator-always-on; 81 regulator-always-on;
126 status = "disabled"; 82 status = "disabled";
127 }; 83 };
128 84
129 reg_fec1_io: regulator-2 { 85 reg_fec1_io: regulator-2 {
130 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
131 regulator-name = "fec1_io_supp 87 regulator-name = "fec1_io_supply";
132 regulator-min-microvolt = <180 88 regulator-min-microvolt = <1800000>;
133 regulator-max-microvolt = <180 89 regulator-max-microvolt = <1800000>;
134 gpio = <&max7322 0 GPIO_ACTIVE 90 gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
135 enable-active-high; 91 enable-active-high;
136 regulator-always-on; 92 regulator-always-on;
137 status = "disabled"; 93 status = "disabled";
138 }; 94 };
139 95
140 reg_can0_stby: regulator-4 { 96 reg_can0_stby: regulator-4 {
141 compatible = "regulator-fixed" 97 compatible = "regulator-fixed";
142 regulator-name = "can0-stby"; 98 regulator-name = "can0-stby";
143 regulator-min-microvolt = <330 99 regulator-min-microvolt = <3300000>;
144 regulator-max-microvolt = <330 100 regulator-max-microvolt = <3300000>;
145 gpio = <&pca6416_3 0 GPIO_ACTI 101 gpio = <&pca6416_3 0 GPIO_ACTIVE_HIGH>;
146 enable-active-high; 102 enable-active-high;
147 }; 103 };
148 104
149 reg_can1_stby: regulator-5 { 105 reg_can1_stby: regulator-5 {
150 compatible = "regulator-fixed" 106 compatible = "regulator-fixed";
151 regulator-name = "can1-stby"; 107 regulator-name = "can1-stby";
152 regulator-min-microvolt = <330 108 regulator-min-microvolt = <3300000>;
153 regulator-max-microvolt = <330 109 regulator-max-microvolt = <3300000>;
154 gpio = <&pca6416_3 1 GPIO_ACTI 110 gpio = <&pca6416_3 1 GPIO_ACTIVE_HIGH>;
155 enable-active-high; 111 enable-active-high;
156 }; 112 };
157 113
158 reg_usdhc2_vmmc: regulator-3 { 114 reg_usdhc2_vmmc: regulator-3 {
159 compatible = "regulator-fixed" 115 compatible = "regulator-fixed";
160 regulator-name = "SD1_SPWR"; 116 regulator-name = "SD1_SPWR";
161 regulator-min-microvolt = <300 117 regulator-min-microvolt = <3000000>;
162 regulator-max-microvolt = <300 118 regulator-max-microvolt = <3000000>;
163 gpio = <&lsio_gpio4 30 GPIO_AC 119 gpio = <&lsio_gpio4 30 GPIO_ACTIVE_HIGH>;
164 enable-active-high; 120 enable-active-high;
165 off-on-delay-us = <3480>; 121 off-on-delay-us = <3480>;
166 }; 122 };
167 123
168 reg_vref_1v8: regulator-adc-vref { 124 reg_vref_1v8: regulator-adc-vref {
169 compatible = "regulator-fixed" 125 compatible = "regulator-fixed";
170 regulator-name = "vref_1v8"; 126 regulator-name = "vref_1v8";
171 regulator-min-microvolt = <180 127 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <180 128 regulator-max-microvolt = <1800000>;
173 }; 129 };
174 130
175 mii_select: regulator-4 { 131 mii_select: regulator-4 {
176 compatible = "regulator-fixed" 132 compatible = "regulator-fixed";
177 regulator-name = "mii-select"; 133 regulator-name = "mii-select";
178 regulator-min-microvolt = <330 134 regulator-min-microvolt = <3300000>;
179 regulator-max-microvolt = <330 135 regulator-max-microvolt = <3300000>;
180 gpio = <&scu_gpio 6 GPIO_ACTIV 136 gpio = <&scu_gpio 6 GPIO_ACTIVE_HIGH>;
181 enable-active-high; 137 enable-active-high;
182 regulator-always-on; 138 regulator-always-on;
183 }; 139 };
184 <<
185 bt_sco_codec: audio-codec-bt { <<
186 compatible = "linux,bt-sco"; <<
187 #sound-dai-cells = <1>; <<
188 }; <<
189 <<
190 sound-bt-sco { <<
191 compatible = "simple-audio-car <<
192 simple-audio-card,name = "bt-s <<
193 simple-audio-card,format = "ds <<
194 simple-audio-card,bitclock-inv <<
195 simple-audio-card,frame-master <<
196 simple-audio-card,bitclock-mas <<
197 <<
198 btcpu: simple-audio-card,cpu { <<
199 sound-dai = <&sai0>; <<
200 dai-tdm-slot-num = <2> <<
201 dai-tdm-slot-width = < <<
202 }; <<
203 <<
204 simple-audio-card,codec { <<
205 sound-dai = <&bt_sco_c <<
206 }; <<
207 }; <<
208 <<
209 sound-wm8960-1 { <<
210 compatible = "fsl,imx-audio-wm <<
211 model = "wm8960-audio"; <<
212 audio-cpu = <&sai1>; <<
213 audio-codec = <&wm8960_1>; <<
214 audio-asrc = <&asrc0>; <<
215 audio-routing = "Headphone Jac <<
216 "Headphone Jac <<
217 "Ext Spk", "SP <<
218 "Ext Spk", "SP <<
219 "Ext Spk", "SP <<
220 "Ext Spk", "SP <<
221 "LINPUT1", "Mi <<
222 "Mic Jack", "M <<
223 }; <<
224 <<
225 sound-wm8960-2 { <<
226 compatible = "fsl,imx-audio-wm <<
227 model = "wm8960-audio-2"; <<
228 audio-cpu = <&sai2>; <<
229 audio-codec = <&wm8960_2>; <<
230 audio-routing = "Headphone Jac <<
231 "Headphone Jac <<
232 "Ext Spk", "SP <<
233 "Ext Spk", "SP <<
234 "Ext Spk", "SP <<
235 "Ext Spk", "SP <<
236 "LINPUT1", "Mi <<
237 "Mic Jack", "M <<
238 }; <<
239 <<
240 sound-wm8960-3 { <<
241 compatible = "fsl,imx-audio-wm <<
242 model = "wm8960-audio-3"; <<
243 audio-cpu = <&sai3>; <<
244 audio-codec = <&wm8960_3>; <<
245 audio-routing = "Headphone Jac <<
246 "Headphone Jac <<
247 "Ext Spk", "SP <<
248 "Ext Spk", "SP <<
249 "Ext Spk", "SP <<
250 "Ext Spk", "SP <<
251 "LINPUT1", "Mi <<
252 "Mic Jack", "M <<
253 }; <<
254 }; 140 };
255 141
256 &adc0 { 142 &adc0 {
257 vref-supply = <®_vref_1v8>; 143 vref-supply = <®_vref_1v8>;
258 status = "okay"; 144 status = "okay";
259 }; 145 };
260 146
261 &asrc0 { <<
262 fsl,asrc-rate = <48000>; <<
263 status = "okay"; <<
264 }; <<
265 <<
266 &eqos { 147 &eqos {
267 pinctrl-names = "default"; 148 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_eqos>; 149 pinctrl-0 = <&pinctrl_eqos>;
269 phy-mode = "rgmii-id"; 150 phy-mode = "rgmii-id";
270 phy-handle = <ðphy0>; 151 phy-handle = <ðphy0>;
271 nvmem-cells = <&fec_mac1>; 152 nvmem-cells = <&fec_mac1>;
272 nvmem-cell-names = "mac-address"; 153 nvmem-cell-names = "mac-address";
273 status = "okay"; 154 status = "okay";
274 155
275 mdio { 156 mdio {
276 compatible = "snps,dwmac-mdio" 157 compatible = "snps,dwmac-mdio";
277 #address-cells = <1>; 158 #address-cells = <1>;
278 #size-cells = <0>; 159 #size-cells = <0>;
279 160
280 ethphy0: ethernet-phy@0 { 161 ethphy0: ethernet-phy@0 {
281 compatible = "ethernet 162 compatible = "ethernet-phy-ieee802.3-c22";
282 reg = <0>; 163 reg = <0>;
283 eee-broken-1000t; 164 eee-broken-1000t;
284 qca,disable-smarteee; 165 qca,disable-smarteee;
285 qca,disable-hibernatio 166 qca,disable-hibernation-mode;
286 reset-gpios = <&pca641 167 reset-gpios = <&pca6416_1 2 GPIO_ACTIVE_LOW>;
287 reset-assert-us = <20> 168 reset-assert-us = <20>;
288 reset-deassert-us = <2 169 reset-deassert-us = <200000>;
289 vddio-supply = <&vddio 170 vddio-supply = <&vddio0>;
290 171
291 vddio0: vddio-regulato 172 vddio0: vddio-regulator {
292 regulator-min- 173 regulator-min-microvolt = <1800000>;
293 regulator-max- 174 regulator-max-microvolt = <1800000>;
294 }; 175 };
295 }; 176 };
296 }; 177 };
297 }; 178 };
298 179
299 /* 180 /*
300 * fec1 shares the some PINs with usdhc2. 181 * fec1 shares the some PINs with usdhc2.
301 * by default usdhc2 is enabled in this dts. 182 * by default usdhc2 is enabled in this dts.
302 * Please disable usdhc2 to enable fec1 183 * Please disable usdhc2 to enable fec1
303 */ 184 */
304 &fec1 { 185 &fec1 {
305 pinctrl-names = "default"; 186 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_fec1>; 187 pinctrl-0 = <&pinctrl_fec1>;
307 phy-mode = "rgmii-txid"; 188 phy-mode = "rgmii-txid";
308 phy-handle = <ðphy1>; 189 phy-handle = <ðphy1>;
309 fsl,magic-packet; 190 fsl,magic-packet;
310 rx-internal-delay-ps = <2000>; 191 rx-internal-delay-ps = <2000>;
311 nvmem-cells = <&fec_mac0>; 192 nvmem-cells = <&fec_mac0>;
312 nvmem-cell-names = "mac-address"; 193 nvmem-cell-names = "mac-address";
313 status = "disabled"; 194 status = "disabled";
314 195
315 mdio { 196 mdio {
316 #address-cells = <1>; 197 #address-cells = <1>;
317 #size-cells = <0>; 198 #size-cells = <0>;
318 199
319 ethphy1: ethernet-phy@1 { 200 ethphy1: ethernet-phy@1 {
320 compatible = "ethernet 201 compatible = "ethernet-phy-ieee802.3-c22";
321 reg = <1>; 202 reg = <1>;
322 reset-gpios = <&pca641 203 reset-gpios = <&pca6416_1 0 GPIO_ACTIVE_LOW>;
323 reset-assert-us = <100 204 reset-assert-us = <10000>;
324 qca,disable-smarteee; 205 qca,disable-smarteee;
325 vddio-supply = <&vddio 206 vddio-supply = <&vddio1>;
326 207
327 vddio1: vddio-regulato 208 vddio1: vddio-regulator {
328 regulator-min- 209 regulator-min-microvolt = <1800000>;
329 regulator-max- 210 regulator-max-microvolt = <1800000>;
330 }; 211 };
331 }; 212 };
332 }; 213 };
333 }; 214 };
334 215
335 &flexspi0 { 216 &flexspi0 {
336 pinctrl-names = "default"; 217 pinctrl-names = "default";
337 pinctrl-0 = <&pinctrl_flexspi0>; 218 pinctrl-0 = <&pinctrl_flexspi0>;
338 status = "okay"; 219 status = "okay";
339 220
340 mt35xu512aba0: flash@0 { 221 mt35xu512aba0: flash@0 {
341 reg = <0>; 222 reg = <0>;
342 #address-cells = <1>; 223 #address-cells = <1>;
343 #size-cells = <1>; 224 #size-cells = <1>;
344 compatible = "jedec,spi-nor"; 225 compatible = "jedec,spi-nor";
345 spi-max-frequency = <133000000 226 spi-max-frequency = <133000000>;
346 spi-tx-bus-width = <8>; 227 spi-tx-bus-width = <8>;
347 spi-rx-bus-width = <8>; 228 spi-rx-bus-width = <8>;
348 }; 229 };
349 }; 230 };
350 231
351 &i2c2 { 232 &i2c2 {
352 #address-cells = <1>; 233 #address-cells = <1>;
353 #size-cells = <0>; 234 #size-cells = <0>;
354 clock-frequency = <100000>; 235 clock-frequency = <100000>;
355 pinctrl-names = "default"; 236 pinctrl-names = "default";
356 pinctrl-0 = <&pinctrl_i2c2>; 237 pinctrl-0 = <&pinctrl_i2c2>;
357 status = "okay"; 238 status = "okay";
358 239
359 pca6416_1: gpio@20 { 240 pca6416_1: gpio@20 {
360 compatible = "ti,tca6416"; 241 compatible = "ti,tca6416";
361 reg = <0x20>; 242 reg = <0x20>;
362 gpio-controller; 243 gpio-controller;
363 #gpio-cells = <2>; 244 #gpio-cells = <2>;
364 }; 245 };
365 246
366 pca6416_2: gpio@21 { 247 pca6416_2: gpio@21 {
367 compatible = "ti,tca6416"; 248 compatible = "ti,tca6416";
368 reg = <0x21>; 249 reg = <0x21>;
369 gpio-controller; 250 gpio-controller;
370 #gpio-cells = <2>; 251 #gpio-cells = <2>;
371 }; 252 };
372 253
373 pca9548_1: i2c-mux@70 { 254 pca9548_1: i2c-mux@70 {
374 compatible = "nxp,pca9548"; 255 compatible = "nxp,pca9548";
375 #address-cells = <1>; 256 #address-cells = <1>;
376 #size-cells = <0>; 257 #size-cells = <0>;
377 reg = <0x70>; 258 reg = <0x70>;
378 259
379 i2c@0 { 260 i2c@0 {
380 #address-cells = <1>; 261 #address-cells = <1>;
381 #size-cells = <0>; 262 #size-cells = <0>;
382 reg = <0x0>; 263 reg = <0x0>;
383 264
384 max7322: gpio@68 { 265 max7322: gpio@68 {
385 compatible = " 266 compatible = "maxim,max7322";
386 reg = <0x68>; 267 reg = <0x68>;
387 gpio-controlle 268 gpio-controller;
388 #gpio-cells = 269 #gpio-cells = <2>;
389 status = "disa 270 status = "disabled";
390 }; 271 };
391 }; 272 };
392 273
393 i2c@1 { <<
394 #address-cells = <1>; <<
395 #size-cells = <0>; <<
396 reg = <0x1>; <<
397 <<
398 wm8960_1: audio-codec@ <<
399 compatible = " <<
400 reg = <0x1a>; <<
401 clocks = <&mcl <<
402 clock-names = <<
403 assigned-clock <<
404 <<
405 <<
406 <<
407 assigned-clock <<
408 <<
409 <<
410 <<
411 wlf,shared-lrc <<
412 wlf,hp-cfg = < <<
413 wlf,gpio-cfg = <<
414 }; <<
415 }; <<
416 <<
417 i2c@2 { <<
418 #address-cells = <1>; <<
419 #size-cells = <0>; <<
420 reg = <0x2>; <<
421 <<
422 wm8960_2: audio-codec@ <<
423 compatible = " <<
424 reg = <0x1a>; <<
425 clocks = <&mcl <<
426 clock-names = <<
427 assigned-clock <<
428 <<
429 <<
430 <<
431 assigned-clock <<
432 <<
433 <<
434 <<
435 wlf,shared-lrc <<
436 wlf,hp-cfg = < <<
437 wlf,gpio-cfg = <<
438 }; <<
439 }; <<
440 <<
441 i2c@3 { <<
442 #address-cells = <1>; <<
443 #size-cells = <0>; <<
444 reg = <0x3>; <<
445 <<
446 wm8960_3: audio-codec@ <<
447 compatible = " <<
448 reg = <0x1a>; <<
449 clocks = <&mcl <<
450 clock-names = <<
451 assigned-clock <<
452 <<
453 <<
454 <<
455 assigned-clock <<
456 <<
457 <<
458 <<
459 wlf,shared-lrc <<
460 wlf,hp-cfg = < <<
461 wlf,gpio-cfg = <<
462 }; <<
463 }; <<
464 <<
465 i2c@4 { 274 i2c@4 {
466 #address-cells = <1>; 275 #address-cells = <1>;
467 #size-cells = <0>; 276 #size-cells = <0>;
468 reg = <0x4>; 277 reg = <0x4>;
469 }; 278 };
470 279
471 i2c@5 { 280 i2c@5 {
472 #address-cells = <1>; 281 #address-cells = <1>;
473 #size-cells = <0>; 282 #size-cells = <0>;
474 reg = <0x5>; 283 reg = <0x5>;
475 }; 284 };
476 285
477 i2c@6 { 286 i2c@6 {
478 #address-cells = <1>; 287 #address-cells = <1>;
479 #size-cells = <0>; 288 #size-cells = <0>;
480 reg = <0x6>; 289 reg = <0x6>;
481 }; 290 };
482 }; 291 };
483 }; 292 };
484 293
485 &i2c3 { 294 &i2c3 {
486 #address-cells = <1>; 295 #address-cells = <1>;
487 #size-cells = <0>; 296 #size-cells = <0>;
488 clock-frequency = <100000>; 297 clock-frequency = <100000>;
489 pinctrl-names = "default"; 298 pinctrl-names = "default";
490 pinctrl-0 = <&pinctrl_i2c3>; 299 pinctrl-0 = <&pinctrl_i2c3>;
491 status = "okay"; 300 status = "okay";
492 301
493 pca6416_3: gpio@20 { 302 pca6416_3: gpio@20 {
494 compatible = "ti,tca6416"; 303 compatible = "ti,tca6416";
495 reg = <0x20>; 304 reg = <0x20>;
496 gpio-controller; 305 gpio-controller;
497 #gpio-cells = <2>; 306 #gpio-cells = <2>;
498 interrupt-parent = <&lsio_gpio 307 interrupt-parent = <&lsio_gpio2>;
499 interrupts = <5 IRQ_TYPE_EDGE_ 308 interrupts = <5 IRQ_TYPE_EDGE_RISING>;
500 }; 309 };
501 310
502 pca9548_2: i2c-mux@70 { 311 pca9548_2: i2c-mux@70 {
503 compatible = "nxp,pca9548"; 312 compatible = "nxp,pca9548";
504 reg = <0x70>; 313 reg = <0x70>;
505 #address-cells = <1>; 314 #address-cells = <1>;
506 #size-cells = <0>; 315 #size-cells = <0>;
507 316
508 i2c@0 { 317 i2c@0 {
509 #address-cells = <1>; 318 #address-cells = <1>;
510 #size-cells = <0>; 319 #size-cells = <0>;
511 reg = <0x0>; 320 reg = <0x0>;
512 }; 321 };
513 322
514 i2c@1 { 323 i2c@1 {
515 #address-cells = <1>; 324 #address-cells = <1>;
516 #size-cells = <0>; 325 #size-cells = <0>;
517 reg = <0x1>; 326 reg = <0x1>;
518 }; 327 };
519 328
520 i2c@2 { 329 i2c@2 {
521 #address-cells = <1>; 330 #address-cells = <1>;
522 #size-cells = <0>; 331 #size-cells = <0>;
523 reg = <0x2>; 332 reg = <0x2>;
524 }; 333 };
525 334
526 i2c@3 { 335 i2c@3 {
527 #address-cells = <1>; 336 #address-cells = <1>;
528 #size-cells = <0>; 337 #size-cells = <0>;
529 reg = <0x3>; 338 reg = <0x3>;
530 }; 339 };
531 340
532 i2c@4 { 341 i2c@4 {
533 #address-cells = <1>; 342 #address-cells = <1>;
534 #size-cells = <0>; 343 #size-cells = <0>;
535 reg = <0x4>; 344 reg = <0x4>;
536 }; 345 };
537 }; 346 };
538 }; 347 };
539 348
540 &lpuart0 { 349 &lpuart0 {
541 pinctrl-names = "default"; 350 pinctrl-names = "default";
542 pinctrl-0 = <&pinctrl_lpuart0>; 351 pinctrl-0 = <&pinctrl_lpuart0>;
543 status = "okay"; 352 status = "okay";
544 }; 353 };
545 354
546 &lpuart1 { 355 &lpuart1 {
547 pinctrl-names = "default"; 356 pinctrl-names = "default";
548 pinctrl-0 = <&pinctrl_lpuart1>; 357 pinctrl-0 = <&pinctrl_lpuart1>;
549 status = "okay"; 358 status = "okay";
550 }; 359 };
551 360
552 &lsio_mu5 { <<
553 status = "okay"; <<
554 }; <<
555 <<
556 &flexcan2 { 361 &flexcan2 {
557 pinctrl-names = "default"; 362 pinctrl-names = "default";
558 pinctrl-0 = <&pinctrl_flexcan2>; 363 pinctrl-0 = <&pinctrl_flexcan2>;
559 xceiver-supply = <®_can0_stby>; 364 xceiver-supply = <®_can0_stby>;
560 status = "okay"; 365 status = "okay";
561 }; 366 };
562 367
563 &flexcan3 { 368 &flexcan3 {
564 pinctrl-names = "default"; 369 pinctrl-names = "default";
565 pinctrl-0 = <&pinctrl_flexcan3>; 370 pinctrl-0 = <&pinctrl_flexcan3>;
566 xceiver-supply = <®_can1_stby>; 371 xceiver-supply = <®_can1_stby>;
567 status = "okay"; 372 status = "okay";
568 }; 373 };
569 374
570 &cm40_intmux { 375 &cm40_intmux {
571 status = "disabled"; 376 status = "disabled";
572 }; 377 };
573 378
574 &cm40_lpuart { 379 &cm40_lpuart {
575 pinctrl-names = "default"; 380 pinctrl-names = "default";
576 pinctrl-0 = <&pinctrl_cm40_lpuart>; 381 pinctrl-0 = <&pinctrl_cm40_lpuart>;
577 status = "disabled"; 382 status = "disabled";
578 }; 383 };
579 384
580 &lsio_gpio4 { 385 &lsio_gpio4 {
581 status = "okay"; 386 status = "okay";
582 }; 387 };
583 388
584 &lsio_gpio5 { 389 &lsio_gpio5 {
585 status = "okay"; 390 status = "okay";
586 }; 391 };
587 392
588 &sai0 { <<
589 pinctrl-names = "default"; <<
590 pinctrl-0 = <&pinctrl_sai0>; <<
591 #sound-dai-cells = <0>; <<
592 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
593 <&clk IMX_SC_R_AUDIO <<
594 <&clk IMX_SC_R_AUDIO <<
595 <&sai0_lpcg IMX_LPCG <<
596 assigned-clock-rates = <786432000>, <4 <<
597 status = "okay"; <<
598 }; <<
599 <<
600 &sai1 { <<
601 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
602 <&clk IMX_SC_R_AUDIO <<
603 <&clk IMX_SC_R_AUDIO <<
604 <&sai1_lpcg IMX_LPCG <<
605 assigned-clock-rates = <786432000>, <4 <<
606 pinctrl-names = "default"; <<
607 pinctrl-0 = <&pinctrl_sai1>; <<
608 status = "okay"; <<
609 }; <<
610 <<
611 &sai2 { <<
612 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
613 <&clk IMX_SC_R_AUDIO <<
614 <&clk IMX_SC_R_AUDIO <<
615 <&sai2_lpcg IMX_LPCG <<
616 assigned-clock-rates = <786432000>, <4 <<
617 pinctrl-names = "default"; <<
618 pinctrl-0 = <&pinctrl_sai2>; <<
619 fsl,sai-asynchronous; <<
620 status = "okay"; <<
621 }; <<
622 <<
623 &sai3 { <<
624 assigned-clocks = <&clk IMX_SC_R_AUDIO <<
625 <&clk IMX_SC_R_AUDIO <<
626 <&clk IMX_SC_R_AUDIO <<
627 <&sai3_lpcg IMX_LPCG <<
628 assigned-clock-rates = <786432000>, <4 <<
629 pinctrl-names = "default"; <<
630 pinctrl-0 = <&pinctrl_sai3>; <<
631 fsl,sai-asynchronous; <<
632 status = "okay"; <<
633 }; <<
634 <<
635 &thermal_zones { 393 &thermal_zones {
636 pmic-thermal { 394 pmic-thermal {
637 polling-delay-passive = <250>; 395 polling-delay-passive = <250>;
638 polling-delay = <2000>; 396 polling-delay = <2000>;
639 thermal-sensors = <&tsens IMX_ 397 thermal-sensors = <&tsens IMX_SC_R_PMIC_0>;
640 398
641 trips { 399 trips {
642 pmic_alert0: trip0 { 400 pmic_alert0: trip0 {
643 temperature = 401 temperature = <110000>;
644 hysteresis = < 402 hysteresis = <2000>;
645 type = "passiv 403 type = "passive";
646 }; 404 };
647 405
648 pmic_crit0: trip1 { 406 pmic_crit0: trip1 {
649 temperature = 407 temperature = <125000>;
650 hysteresis = < 408 hysteresis = <2000>;
651 type = "critic 409 type = "critical";
652 }; 410 };
653 }; 411 };
654 412
655 cooling-maps { 413 cooling-maps {
656 map0 { 414 map0 {
657 trip = <&pmic_ 415 trip = <&pmic_alert0>;
658 cooling-device 416 cooling-device =
659 <&A35_ 417 <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
660 <&A35_ 418 <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
661 }; 419 };
662 }; 420 };
663 }; 421 };
664 }; 422 };
665 423
666 &usbphy1 { 424 &usbphy1 {
667 /* USB eye diagram tests result */ 425 /* USB eye diagram tests result */
668 fsl,tx-d-cal = <114>; 426 fsl,tx-d-cal = <114>;
669 status = "okay"; 427 status = "okay";
670 }; 428 };
671 429
672 &usbotg1 { 430 &usbotg1 {
673 pinctrl-names = "default"; 431 pinctrl-names = "default";
674 pinctrl-0 = <&pinctrl_usbotg1>; 432 pinctrl-0 = <&pinctrl_usbotg1>;
675 srp-disable; 433 srp-disable;
676 hnp-disable; 434 hnp-disable;
677 adp-disable; 435 adp-disable;
678 power-active-high; 436 power-active-high;
679 disable-over-current; 437 disable-over-current;
680 status = "okay"; 438 status = "okay";
681 }; 439 };
682 440
683 &usbphy2 { 441 &usbphy2 {
684 /* USB eye diagram tests result */ 442 /* USB eye diagram tests result */
685 fsl,tx-d-cal = <111>; 443 fsl,tx-d-cal = <111>;
686 status = "okay"; 444 status = "okay";
687 }; 445 };
688 446
689 &usbotg2 { 447 &usbotg2 {
690 pinctrl-names = "default"; 448 pinctrl-names = "default";
691 pinctrl-0 = <&pinctrl_usbotg2>; 449 pinctrl-0 = <&pinctrl_usbotg2>;
692 srp-disable; 450 srp-disable;
693 hnp-disable; 451 hnp-disable;
694 adp-disable; 452 adp-disable;
695 power-active-high; 453 power-active-high;
696 disable-over-current; 454 disable-over-current;
697 status = "okay"; 455 status = "okay";
698 }; 456 };
699 457
700 &usdhc1 { 458 &usdhc1 {
701 pinctrl-names = "default"; 459 pinctrl-names = "default";
702 pinctrl-0 = <&pinctrl_usdhc1>; 460 pinctrl-0 = <&pinctrl_usdhc1>;
703 bus-width = <8>; 461 bus-width = <8>;
704 no-sd; 462 no-sd;
705 no-sdio; 463 no-sdio;
706 non-removable; 464 non-removable;
707 status = "okay"; 465 status = "okay";
708 }; 466 };
709 467
710 &usdhc2 { 468 &usdhc2 {
711 pinctrl-names = "default"; 469 pinctrl-names = "default";
712 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 470 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
713 bus-width = <4>; 471 bus-width = <4>;
714 vmmc-supply = <®_usdhc2_vmmc>; 472 vmmc-supply = <®_usdhc2_vmmc>;
715 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_ 473 cd-gpios = <&lsio_gpio5 1 GPIO_ACTIVE_LOW>;
716 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_ 474 wp-gpios = <&lsio_gpio5 0 GPIO_ACTIVE_HIGH>;
717 status = "okay"; 475 status = "okay";
718 }; 476 };
719 477
720 &lpspi3 { 478 &lpspi3 {
721 fsl,spi-only-use-cs1-sel; 479 fsl,spi-only-use-cs1-sel;
722 pinctrl-names = "default"; 480 pinctrl-names = "default";
723 pinctrl-0 = <&pinctrl_lpspi3>; 481 pinctrl-0 = <&pinctrl_lpspi3>;
724 status = "okay"; 482 status = "okay";
>> 483
>> 484 spidev0: spi@0 {
>> 485 reg = <0>;
>> 486 compatible = "rohm,dh2228fv";
>> 487 spi-max-frequency = <30000000>;
>> 488 };
725 }; 489 };
726 490
727 &iomuxc { 491 &iomuxc {
728 pinctrl-names = "default"; 492 pinctrl-names = "default";
729 pinctrl-0 = <&pinctrl_hog>; 493 pinctrl-0 = <&pinctrl_hog>;
730 494
731 pinctrl_hog: hoggrp { 495 pinctrl_hog: hoggrp {
732 fsl,pins = < 496 fsl,pins = <
733 IMX8DXL_COMP_CTL_GPIO_ 497 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
734 IMX8DXL_COMP_CTL_GPIO_ 498 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD 0x000014a0
735 IMX8DXL_SPI3_CS0_ADMA_ 499 IMX8DXL_SPI3_CS0_ADMA_ACM_MCLK_OUT1 0x0600004c
736 IMX8DXL_SNVS_TAMPER_OU 500 IMX8DXL_SNVS_TAMPER_OUT1_LSIO_GPIO2_IO05_IN 0x0600004c
737 >; 501 >;
738 }; 502 };
739 503
740 pinctrl_usbotg1: usbotg1grp { 504 pinctrl_usbotg1: usbotg1grp {
741 fsl,pins = < 505 fsl,pins = <
742 IMX8DXL_USB_SS3_TC0_CO 506 IMX8DXL_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
743 >; 507 >;
744 }; 508 };
745 509
746 pinctrl_usbotg2: usbotg2grp { 510 pinctrl_usbotg2: usbotg2grp {
747 fsl,pins = < 511 fsl,pins = <
748 IMX8DXL_USB_SS3_TC1_CO 512 IMX8DXL_USB_SS3_TC1_CONN_USB_OTG2_PWR 0x00000021
749 >; 513 >;
750 }; 514 };
751 515
752 pinctrl_eqos: eqosgrp { 516 pinctrl_eqos: eqosgrp {
753 fsl,pins = < 517 fsl,pins = <
754 IMX8DXL_ENET0_MDC_CONN 518 IMX8DXL_ENET0_MDC_CONN_EQOS_MDC 0x06000020
755 IMX8DXL_ENET0_MDIO_CON 519 IMX8DXL_ENET0_MDIO_CONN_EQOS_MDIO 0x06000020
756 IMX8DXL_ENET1_RGMII_RX 520 IMX8DXL_ENET1_RGMII_RXC_CONN_EQOS_RGMII_RXC 0x06000020
757 IMX8DXL_ENET1_RGMII_RX 521 IMX8DXL_ENET1_RGMII_RXD0_CONN_EQOS_RGMII_RXD0 0x06000020
758 IMX8DXL_ENET1_RGMII_RX 522 IMX8DXL_ENET1_RGMII_RXD1_CONN_EQOS_RGMII_RXD1 0x06000020
759 IMX8DXL_ENET1_RGMII_RX 523 IMX8DXL_ENET1_RGMII_RXD2_CONN_EQOS_RGMII_RXD2 0x06000020
760 IMX8DXL_ENET1_RGMII_RX 524 IMX8DXL_ENET1_RGMII_RXD3_CONN_EQOS_RGMII_RXD3 0x06000020
761 IMX8DXL_ENET1_RGMII_RX 525 IMX8DXL_ENET1_RGMII_RX_CTL_CONN_EQOS_RGMII_RX_CTL 0x06000020
762 IMX8DXL_ENET1_RGMII_TX 526 IMX8DXL_ENET1_RGMII_TXC_CONN_EQOS_RGMII_TXC 0x06000020
763 IMX8DXL_ENET1_RGMII_TX 527 IMX8DXL_ENET1_RGMII_TXD0_CONN_EQOS_RGMII_TXD0 0x06000020
764 IMX8DXL_ENET1_RGMII_TX 528 IMX8DXL_ENET1_RGMII_TXD1_CONN_EQOS_RGMII_TXD1 0x06000020
765 IMX8DXL_ENET1_RGMII_TX 529 IMX8DXL_ENET1_RGMII_TXD2_CONN_EQOS_RGMII_TXD2 0x06000020
766 IMX8DXL_ENET1_RGMII_TX 530 IMX8DXL_ENET1_RGMII_TXD3_CONN_EQOS_RGMII_TXD3 0x06000020
767 IMX8DXL_ENET1_RGMII_TX 531 IMX8DXL_ENET1_RGMII_TX_CTL_CONN_EQOS_RGMII_TX_CTL 0x06000020
768 >; 532 >;
769 }; 533 };
770 534
771 pinctrl_flexspi0: flexspi0grp { 535 pinctrl_flexspi0: flexspi0grp {
772 fsl,pins = < 536 fsl,pins = <
773 IMX8DXL_QSPI0A_DATA0_L 537 IMX8DXL_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021
774 IMX8DXL_QSPI0A_DATA1_L 538 IMX8DXL_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021
775 IMX8DXL_QSPI0A_DATA2_L 539 IMX8DXL_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021
776 IMX8DXL_QSPI0A_DATA3_L 540 IMX8DXL_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021
777 IMX8DXL_QSPI0A_DQS_LSI 541 IMX8DXL_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021
778 IMX8DXL_QSPI0A_SS0_B_L 542 IMX8DXL_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021
779 IMX8DXL_QSPI0A_SCLK_LS 543 IMX8DXL_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021
780 IMX8DXL_QSPI0B_SCLK_LS 544 IMX8DXL_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021
781 IMX8DXL_QSPI0B_DATA0_L 545 IMX8DXL_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021
782 IMX8DXL_QSPI0B_DATA1_L 546 IMX8DXL_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021
783 IMX8DXL_QSPI0B_DATA2_L 547 IMX8DXL_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021
784 IMX8DXL_QSPI0B_DATA3_L 548 IMX8DXL_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021
785 IMX8DXL_QSPI0B_DQS_LSI 549 IMX8DXL_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021
786 IMX8DXL_QSPI0B_SS0_B_L 550 IMX8DXL_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021
787 >; 551 >;
788 }; 552 };
789 553
790 pinctrl_flexcan2: flexcan2grp { 554 pinctrl_flexcan2: flexcan2grp {
791 fsl,pins = < 555 fsl,pins = <
792 IMX8DXL_UART2_TX_ADMA_ 556 IMX8DXL_UART2_TX_ADMA_FLEXCAN1_TX 0x00000021
793 IMX8DXL_UART2_RX_ADMA_ 557 IMX8DXL_UART2_RX_ADMA_FLEXCAN1_RX 0x00000021
794 >; 558 >;
795 }; 559 };
796 560
797 pinctrl_flexcan3: flexcan3grp { 561 pinctrl_flexcan3: flexcan3grp {
798 fsl,pins = < 562 fsl,pins = <
799 IMX8DXL_FLEXCAN2_TX_AD 563 IMX8DXL_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x00000021
800 IMX8DXL_FLEXCAN2_RX_AD 564 IMX8DXL_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x00000021
801 >; 565 >;
802 }; 566 };
803 567
804 pinctrl_fec1: fec1grp { 568 pinctrl_fec1: fec1grp {
805 fsl,pins = < 569 fsl,pins = <
806 IMX8DXL_COMP_CTL_GPIO_ 570 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
807 IMX8DXL_COMP_CTL_GPIO_ 571 IMX8DXL_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
808 IMX8DXL_ENET0_MDC_CONN 572 IMX8DXL_ENET0_MDC_CONN_ENET0_MDC 0x06000020
809 IMX8DXL_ENET0_MDIO_CON 573 IMX8DXL_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
810 IMX8DXL_ENET0_RGMII_RX 574 IMX8DXL_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060
811 IMX8DXL_ENET0_RGMII_RX 575 IMX8DXL_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060
812 IMX8DXL_ENET0_RGMII_RX 576 IMX8DXL_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060
813 IMX8DXL_ENET0_RGMII_RX 577 IMX8DXL_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060
814 IMX8DXL_ENET0_RGMII_RX 578 IMX8DXL_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060
815 IMX8DXL_ENET0_RGMII_RX 579 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060
816 IMX8DXL_ENET0_RGMII_TX 580 IMX8DXL_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060
817 IMX8DXL_ENET0_RGMII_TX 581 IMX8DXL_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060
818 IMX8DXL_ENET0_RGMII_TX 582 IMX8DXL_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060
819 IMX8DXL_ENET0_RGMII_TX 583 IMX8DXL_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060
820 IMX8DXL_ENET0_RGMII_TX 584 IMX8DXL_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060
821 IMX8DXL_ENET0_RGMII_TX 585 IMX8DXL_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060
822 >; 586 >;
823 }; 587 };
824 588
825 pinctrl_lpspi3: lpspi3grp { 589 pinctrl_lpspi3: lpspi3grp {
826 fsl,pins = < 590 fsl,pins = <
827 IMX8DXL_SPI3_SCK_ADMA_ 591 IMX8DXL_SPI3_SCK_ADMA_SPI3_SCK 0x6000040
828 IMX8DXL_SPI3_SDO_ADMA_ 592 IMX8DXL_SPI3_SDO_ADMA_SPI3_SDO 0x6000040
829 IMX8DXL_SPI3_SDI_ADMA_ 593 IMX8DXL_SPI3_SDI_ADMA_SPI3_SDI 0x6000040
830 IMX8DXL_SPI3_CS1_ADMA_ 594 IMX8DXL_SPI3_CS1_ADMA_SPI3_CS1 0x6000040
831 >; 595 >;
832 }; 596 };
833 597
834 pinctrl_i2c2: i2c2grp { 598 pinctrl_i2c2: i2c2grp {
835 fsl,pins = < 599 fsl,pins = <
836 IMX8DXL_SPI1_SCK_ADMA_ 600 IMX8DXL_SPI1_SCK_ADMA_I2C2_SDA 0x06000021
837 IMX8DXL_SPI1_SDO_ADMA_ 601 IMX8DXL_SPI1_SDO_ADMA_I2C2_SCL 0x06000021
838 >; 602 >;
839 }; 603 };
840 604
841 pinctrl_cm40_lpuart: cm40lpuartgrp { 605 pinctrl_cm40_lpuart: cm40lpuartgrp {
842 fsl,pins = < 606 fsl,pins = <
843 IMX8DXL_ADC_IN2_M40_UA 607 IMX8DXL_ADC_IN2_M40_UART0_RX 0x06000020
844 IMX8DXL_ADC_IN3_M40_UA 608 IMX8DXL_ADC_IN3_M40_UART0_TX 0x06000020
845 >; 609 >;
846 }; 610 };
847 611
848 pinctrl_i2c3: i2c3grp { 612 pinctrl_i2c3: i2c3grp {
849 fsl,pins = < 613 fsl,pins = <
850 IMX8DXL_SPI1_CS0_ADMA_ 614 IMX8DXL_SPI1_CS0_ADMA_I2C3_SDA 0x06000021
851 IMX8DXL_SPI1_SDI_ADMA_ 615 IMX8DXL_SPI1_SDI_ADMA_I2C3_SCL 0x06000021
852 >; 616 >;
853 }; 617 };
854 618
855 pinctrl_lpuart0: lpuart0grp { 619 pinctrl_lpuart0: lpuart0grp {
856 fsl,pins = < 620 fsl,pins = <
857 IMX8DXL_UART0_RX_ADMA_ 621 IMX8DXL_UART0_RX_ADMA_UART0_RX 0x06000020
858 IMX8DXL_UART0_TX_ADMA_ 622 IMX8DXL_UART0_TX_ADMA_UART0_TX 0x06000020
859 >; 623 >;
860 }; 624 };
861 625
862 pinctrl_lpuart1: lpuart1grp { 626 pinctrl_lpuart1: lpuart1grp {
863 fsl,pins = < 627 fsl,pins = <
864 IMX8DXL_UART1_TX_ADMA_ 628 IMX8DXL_UART1_TX_ADMA_UART1_TX 0x06000020
865 IMX8DXL_UART1_RX_ADMA_ 629 IMX8DXL_UART1_RX_ADMA_UART1_RX 0x06000020
866 IMX8DXL_UART1_RTS_B_AD 630 IMX8DXL_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020
867 IMX8DXL_UART1_CTS_B_AD 631 IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
868 >; <<
869 }; <<
870 <<
871 pinctrl_sai0: sai0grp { <<
872 fsl,pins = < <<
873 IMX8DXL_SPI0_CS0_ADMA_ <<
874 IMX8DXL_SPI0_CS1_ADMA_ <<
875 IMX8DXL_SPI0_SCK_ADMA_ <<
876 IMX8DXL_SPI0_SDI_ADMA_ <<
877 IMX8DXL_SPI0_SDO_ADMA_ <<
878 >; <<
879 }; <<
880 <<
881 pinctrl_sai1: sai1grp { <<
882 fsl,pins = < <<
883 IMX8DXL_FLEXCAN0_RX_AD <<
884 IMX8DXL_FLEXCAN0_TX_AD <<
885 IMX8DXL_FLEXCAN1_RX_AD <<
886 IMX8DXL_FLEXCAN1_TX_AD <<
887 >; <<
888 }; <<
889 <<
890 pinctrl_sai2: sai2grp { <<
891 fsl,pins = < <<
892 IMX8DXL_SNVS_TAMPER_OU <<
893 IMX8DXL_SNVS_TAMPER_IN <<
894 IMX8DXL_SNVS_TAMPER_OU <<
895 >; <<
896 }; <<
897 <<
898 pinctrl_sai3: sai3grp { <<
899 fsl,pins = < <<
900 IMX8DXL_SNVS_TAMPER_IN <<
901 IMX8DXL_SNVS_TAMPER_IN <<
902 IMX8DXL_SNVS_TAMPER_IN <<
903 >; 632 >;
904 }; 633 };
905 634
906 pinctrl_usdhc1: usdhc1grp { 635 pinctrl_usdhc1: usdhc1grp {
907 fsl,pins = < 636 fsl,pins = <
908 IMX8DXL_EMMC0_CLK_CONN 637 IMX8DXL_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
909 IMX8DXL_EMMC0_CMD_CONN 638 IMX8DXL_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
910 IMX8DXL_EMMC0_DATA0_CO 639 IMX8DXL_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
911 IMX8DXL_EMMC0_DATA1_CO 640 IMX8DXL_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
912 IMX8DXL_EMMC0_DATA2_CO 641 IMX8DXL_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
913 IMX8DXL_EMMC0_DATA3_CO 642 IMX8DXL_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
914 IMX8DXL_EMMC0_DATA4_CO 643 IMX8DXL_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
915 IMX8DXL_EMMC0_DATA5_CO 644 IMX8DXL_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
916 IMX8DXL_EMMC0_DATA6_CO 645 IMX8DXL_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
917 IMX8DXL_EMMC0_DATA7_CO 646 IMX8DXL_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
918 IMX8DXL_EMMC0_STROBE_C 647 IMX8DXL_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
919 >; 648 >;
920 }; 649 };
921 650
922 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 651 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
923 fsl,pins = < 652 fsl,pins = <
924 IMX8DXL_ENET0_RGMII_TX 653 IMX8DXL_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x00000040 /* RESET_B */
925 IMX8DXL_ENET0_RGMII_TX 654 IMX8DXL_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x00000021 /* WP */
926 IMX8DXL_ENET0_RGMII_TX 655 IMX8DXL_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x00000021 /* CD */
927 >; 656 >;
928 }; 657 };
929 658
930 pinctrl_usdhc2: usdhc2grp { 659 pinctrl_usdhc2: usdhc2grp {
931 fsl,pins = < 660 fsl,pins = <
932 IMX8DXL_ENET0_RGMII_RX 661 IMX8DXL_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
933 IMX8DXL_ENET0_RGMII_RX 662 IMX8DXL_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
934 IMX8DXL_ENET0_RGMII_RX 663 IMX8DXL_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
935 IMX8DXL_ENET0_RGMII_RX 664 IMX8DXL_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
936 IMX8DXL_ENET0_RGMII_RX 665 IMX8DXL_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
937 IMX8DXL_ENET0_RGMII_RX 666 IMX8DXL_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
938 IMX8DXL_ENET0_RGMII_TX 667 IMX8DXL_ENET0_RGMII_TXD0_CONN_USDHC1_VSELECT 0x00000021
939 >; 668 >;
940 }; 669 };
941 }; 670 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.