1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2019~2020, 2022 NXP 4 */ 5 6 /delete-node/ &asrc1; 7 /delete-node/ &asrc1_lpcg; 8 /delete-node/ &adc1; 9 /delete-node/ &adc1_lpcg; 10 /delete-node/ &amix; 11 /delete-node/ &amix_lpcg; 12 /delete-node/ &edma1; 13 /delete-node/ &esai0; 14 /delete-node/ &esai0_lpcg; 15 /delete-node/ &sai4; 16 /delete-node/ &sai4_lpcg; 17 /delete-node/ &sai5; 18 /delete-node/ &sai5_lpcg; 19 20 &acm { 21 compatible = "fsl,imx8dxl-acm"; 22 power-domains = <&pd IMX_SC_R_AUDIO_CL 23 <&pd IMX_SC_R_AUDIO_CL 24 <&pd IMX_SC_R_MCLK_OUT 25 <&pd IMX_SC_R_MCLK_OUT 26 <&pd IMX_SC_R_AUDIO_PL 27 <&pd IMX_SC_R_AUDIO_PL 28 <&pd IMX_SC_R_ASRC_0>, 29 <&pd IMX_SC_R_SAI_0>, 30 <&pd IMX_SC_R_SAI_1>, 31 <&pd IMX_SC_R_SAI_2>, 32 <&pd IMX_SC_R_SAI_3>, 33 <&pd IMX_SC_R_SPDIF_0> 34 <&pd IMX_SC_R_MQS_0>; 35 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_ 36 <&aud_rec1_lpcg IMX_LPCG_CLK_ 37 <&aud_pll_div0_lpcg IMX_LPCG_ 38 <&aud_pll_div1_lpcg IMX_LPCG_ 39 <&clk_ext_aud_mclk0>, 40 <&clk_ext_aud_mclk1>, 41 <&clk_spdif0_rx>, 42 <&clk_sai0_rx_bclk>, 43 <&clk_sai0_tx_bclk>, 44 <&clk_sai1_rx_bclk>, 45 <&clk_sai1_tx_bclk>, 46 <&clk_sai2_rx_bclk>, 47 <&clk_sai3_rx_bclk>; 48 clock-names = "aud_rec_clk0_lpcg_clk", 49 "aud_rec_clk1_lpcg_clk", 50 "aud_pll_div_clk0_lpcg_c 51 "aud_pll_div_clk1_lpcg_c 52 "ext_aud_mclk0", 53 "ext_aud_mclk1", 54 "spdif0_rx", 55 "sai0_rx_bclk", 56 "sai0_tx_bclk", 57 "sai1_rx_bclk", 58 "sai1_tx_bclk", 59 "sai2_rx_bclk", 60 "sai3_rx_bclk"; 61 }; 62 63 &audio_ipg_clk { 64 clock-frequency = <160000000>; 65 }; 66 67 &dma_ipg_clk { 68 clock-frequency = <160000000>; 69 }; 70 71 &adc0 { 72 interrupts = <GIC_SPI 146 IRQ_TYPE_LEV 73 }; 74 75 &edma0 { 76 reg = <0x591f0000 0x1a0000>; 77 #dma-cells = <3>; 78 dma-channels = <25>; 79 dma-channel-mask = <0x1c0cc0>; 80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEV 81 <GIC_SPI 263 IRQ_TYPE_LEVEL_HI 82 <GIC_SPI 264 IRQ_TYPE_LEVEL_HI 83 <GIC_SPI 265 IRQ_TYPE_LEVEL_HI 84 <GIC_SPI 266 IRQ_TYPE_LEVEL_HI 85 <GIC_SPI 267 IRQ_TYPE_LEVEL_HI 86 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 87 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 88 <GIC_SPI 327 IRQ_TYPE_LEVEL_HI 89 <GIC_SPI 329 IRQ_TYPE_LEVEL_HI 90 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 91 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 92 <GIC_SPI 189 IRQ_TYPE_LEVEL_HI 93 <GIC_SPI 189 IRQ_TYPE_LEVEL_HI 94 <GIC_SPI 191 IRQ_TYPE_LEVEL_HI 95 <GIC_SPI 191 IRQ_TYPE_LEVEL_HI 96 <GIC_SPI 193 IRQ_TYPE_LEVEL_HI 97 <GIC_SPI 199 IRQ_TYPE_LEVEL_HI 98 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 99 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 100 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 101 <GIC_SPI 268 IRQ_TYPE_LEVEL_HI 102 <GIC_SPI 269 IRQ_TYPE_LEVEL_HI 103 <GIC_SPI 270 IRQ_TYPE_LEVEL_HI 104 <GIC_SPI 271 IRQ_TYPE_LEVEL_HI 105 power-domains = <&pd IMX_SC_R_DMA_0_CH 106 <&pd IMX_SC_R_DMA_0_CH 107 <&pd IMX_SC_R_DMA_0_CH 108 <&pd IMX_SC_R_DMA_0_CH 109 <&pd IMX_SC_R_DMA_0_CH 110 <&pd IMX_SC_R_DMA_0_CH 111 <&pd IMX_SC_R_DMA_0_CH 112 <&pd IMX_SC_R_DMA_0_CH 113 <&pd IMX_SC_R_DMA_0_CH 114 <&pd IMX_SC_R_DMA_0_CH 115 <&pd IMX_SC_R_DMA_0_CH 116 <&pd IMX_SC_R_DMA_0_CH 117 <&pd IMX_SC_R_DMA_0_CH 118 <&pd IMX_SC_R_DMA_0_CH 119 <&pd IMX_SC_R_DMA_0_CH 120 <&pd IMX_SC_R_DMA_0_CH 121 <&pd IMX_SC_R_DMA_0_CH 122 <&pd IMX_SC_R_DMA_0_CH 123 <&pd IMX_SC_R_DMA_0_CH 124 <&pd IMX_SC_R_DMA_0_CH 125 <&pd IMX_SC_R_DMA_0_CH 126 <&pd IMX_SC_R_DMA_0_CH 127 <&pd IMX_SC_R_DMA_0_CH 128 <&pd IMX_SC_R_DMA_0_CH 129 <&pd IMX_SC_R_DMA_0_CH 130 }; 131 132 &edma2 { 133 interrupts = <GIC_SPI 288 IRQ_TYPE_LEV 134 <GIC_SPI 289 IRQ_TYPE_LEV 135 <GIC_SPI 290 IRQ_TYPE_LEV 136 <GIC_SPI 291 IRQ_TYPE_LEV 137 <GIC_SPI 292 IRQ_TYPE_LEV 138 <GIC_SPI 293 IRQ_TYPE_LEV 139 <GIC_SPI 294 IRQ_TYPE_LEV 140 <GIC_SPI 295 IRQ_TYPE_LEV 141 <GIC_SPI 308 IRQ_TYPE_LEV 142 <GIC_SPI 309 IRQ_TYPE_LEV 143 <GIC_SPI 310 IRQ_TYPE_LEV 144 <GIC_SPI 311 IRQ_TYPE_LEV 145 <GIC_SPI 312 IRQ_TYPE_LEV 146 <GIC_SPI 313 IRQ_TYPE_LEV 147 <GIC_SPI 314 IRQ_TYPE_LEV 148 <GIC_SPI 315 IRQ_TYPE_LEV 149 }; 150 151 &edma3 { 152 interrupts = <GIC_SPI 296 IRQ_TYPE_LEV 153 <GIC_SPI 297 IRQ_TYPE_LEV 154 <GIC_SPI 298 IRQ_TYPE_LEV 155 <GIC_SPI 299 IRQ_TYPE_LEV 156 <GIC_SPI 300 IRQ_TYPE_LEV 157 <GIC_SPI 301 IRQ_TYPE_LEV 158 <GIC_SPI 302 IRQ_TYPE_LEV 159 <GIC_SPI 303 IRQ_TYPE_LEV 160 }; 161 162 &flexcan1 { 163 interrupts = <GIC_SPI 238 IRQ_TYPE_LEV 164 }; 165 166 &flexcan2 { 167 interrupts = <GIC_SPI 239 IRQ_TYPE_LEV 168 }; 169 170 &flexcan3 { 171 interrupts = <GIC_SPI 240 IRQ_TYPE_LEV 172 }; 173 174 &i2c0 { 175 compatible = "fsl,imx8dxl-lpi2c", "fsl 176 interrupts = <GIC_SPI 222 IRQ_TYPE_LEV 177 dma-names = "tx","rx"; 178 dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL 179 }; 180 181 &i2c1 { 182 compatible = "fsl,imx8dxl-lpi2c", "fsl 183 interrupts = <GIC_SPI 223 IRQ_TYPE_LEV 184 dma-names = "tx","rx"; 185 dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL 186 }; 187 188 &i2c2 { 189 compatible = "fsl,imx8dxl-lpi2c", "fsl 190 interrupts = <GIC_SPI 224 IRQ_TYPE_LEV 191 dma-names = "tx","rx"; 192 dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL 193 }; 194 195 &i2c3 { 196 compatible = "fsl,imx8dxl-lpi2c", "fsl 197 interrupts = <GIC_SPI 225 IRQ_TYPE_LEV 198 dma-names = "tx","rx"; 199 dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL 200 }; 201 202 &lpuart0 { 203 compatible = "fsl,imx8dxl-lpuart", "fs 204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEV 205 }; 206 207 &lpuart1 { 208 compatible = "fsl,imx8dxl-lpuart", "fs 209 interrupts = <GIC_SPI 229 IRQ_TYPE_LEV 210 }; 211 212 &lpuart2 { 213 compatible = "fsl,imx8dxl-lpuart", "fs 214 interrupts = <GIC_SPI 230 IRQ_TYPE_LEV 215 }; 216 217 &lpuart3 { 218 compatible = "fsl,imx8dxl-lpuart", "fs 219 interrupts = <GIC_SPI 231 IRQ_TYPE_LEV 220 }; 221 222 &lpspi0 { 223 interrupts = <GIC_SPI 218 IRQ_TYPE_LEV 224 }; 225 226 &lpspi1 { 227 interrupts = <GIC_SPI 219 IRQ_TYPE_LEV 228 }; 229 230 &lpspi2 { 231 interrupts = <GIC_SPI 220 IRQ_TYPE_LEV 232 }; 233 234 &lpspi3 { 235 interrupts = <GIC_SPI 221 IRQ_TYPE_LEV 236 }; 237 238 &sai0 { 239 interrupts = <GIC_SPI 188 IRQ_TYPE_LEV 240 }; 241 242 &sai1 { 243 interrupts = <GIC_SPI 190 IRQ_TYPE_LEV 244 }; 245 246 &sai2 { 247 interrupts = <GIC_SPI 192 IRQ_TYPE_LEV 248 }; 249 250 &sai3 { 251 interrupts = <GIC_SPI 198 IRQ_TYPE_LEV 252 }; 253 254 &spdif0 { 255 interrupts = <GIC_SPI 326 IRQ_TYPE_LEV 256 <GIC_SPI 328 IRQ_TYPE_LEV 257 };
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