1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2019~2020, 2022 NXP 3 * Copyright 2019~2020, 2022 NXP
4 */ 4 */
5 5
6 /delete-node/ &asrc1; <<
7 /delete-node/ &asrc1_lpcg; <<
8 /delete-node/ &adc1; <<
9 /delete-node/ &adc1_lpcg; <<
10 /delete-node/ &amix; <<
11 /delete-node/ &amix_lpcg; <<
12 /delete-node/ &edma1; <<
13 /delete-node/ &esai0; <<
14 /delete-node/ &esai0_lpcg; <<
15 /delete-node/ &sai4; <<
16 /delete-node/ &sai4_lpcg; <<
17 /delete-node/ &sai5; <<
18 /delete-node/ &sai5_lpcg; <<
19 <<
20 &acm { <<
21 compatible = "fsl,imx8dxl-acm"; <<
22 power-domains = <&pd IMX_SC_R_AUDIO_CL <<
23 <&pd IMX_SC_R_AUDIO_CL <<
24 <&pd IMX_SC_R_MCLK_OUT <<
25 <&pd IMX_SC_R_MCLK_OUT <<
26 <&pd IMX_SC_R_AUDIO_PL <<
27 <&pd IMX_SC_R_AUDIO_PL <<
28 <&pd IMX_SC_R_ASRC_0>, <<
29 <&pd IMX_SC_R_SAI_0>, <<
30 <&pd IMX_SC_R_SAI_1>, <<
31 <&pd IMX_SC_R_SAI_2>, <<
32 <&pd IMX_SC_R_SAI_3>, <<
33 <&pd IMX_SC_R_SPDIF_0> <<
34 <&pd IMX_SC_R_MQS_0>; <<
35 clocks = <&aud_rec0_lpcg IMX_LPCG_CLK_ <<
36 <&aud_rec1_lpcg IMX_LPCG_CLK_ <<
37 <&aud_pll_div0_lpcg IMX_LPCG_ <<
38 <&aud_pll_div1_lpcg IMX_LPCG_ <<
39 <&clk_ext_aud_mclk0>, <<
40 <&clk_ext_aud_mclk1>, <<
41 <&clk_spdif0_rx>, <<
42 <&clk_sai0_rx_bclk>, <<
43 <&clk_sai0_tx_bclk>, <<
44 <&clk_sai1_rx_bclk>, <<
45 <&clk_sai1_tx_bclk>, <<
46 <&clk_sai2_rx_bclk>, <<
47 <&clk_sai3_rx_bclk>; <<
48 clock-names = "aud_rec_clk0_lpcg_clk", <<
49 "aud_rec_clk1_lpcg_clk", <<
50 "aud_pll_div_clk0_lpcg_c <<
51 "aud_pll_div_clk1_lpcg_c <<
52 "ext_aud_mclk0", <<
53 "ext_aud_mclk1", <<
54 "spdif0_rx", <<
55 "sai0_rx_bclk", <<
56 "sai0_tx_bclk", <<
57 "sai1_rx_bclk", <<
58 "sai1_tx_bclk", <<
59 "sai2_rx_bclk", <<
60 "sai3_rx_bclk"; <<
61 }; <<
62 <<
63 &audio_ipg_clk { 6 &audio_ipg_clk {
64 clock-frequency = <160000000>; 7 clock-frequency = <160000000>;
65 }; 8 };
66 9
67 &dma_ipg_clk { 10 &dma_ipg_clk {
68 clock-frequency = <160000000>; 11 clock-frequency = <160000000>;
69 }; 12 };
70 13
71 &adc0 { 14 &adc0 {
72 interrupts = <GIC_SPI 146 IRQ_TYPE_LEV 15 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
73 }; 16 };
74 17
75 &edma0 { 18 &edma0 {
76 reg = <0x591f0000 0x1a0000>; 19 reg = <0x591f0000 0x1a0000>;
77 #dma-cells = <3>; 20 #dma-cells = <3>;
78 dma-channels = <25>; 21 dma-channels = <25>;
79 dma-channel-mask = <0x1c0cc0>; 22 dma-channel-mask = <0x1c0cc0>;
80 interrupts = <GIC_SPI 262 IRQ_TYPE_LEV 23 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */
81 <GIC_SPI 263 IRQ_TYPE_LEVEL_HI 24 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 264 IRQ_TYPE_LEVEL_HI 25 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 265 IRQ_TYPE_LEVEL_HI 26 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 266 IRQ_TYPE_LEVEL_HI 27 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 267 IRQ_TYPE_LEVEL_HI 28 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 29 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 30 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 327 IRQ_TYPE_LEVEL_HI 31 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
89 <GIC_SPI 329 IRQ_TYPE_LEVEL_HI 32 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 33 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 34 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 189 IRQ_TYPE_LEVEL_HI 35 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
93 <GIC_SPI 189 IRQ_TYPE_LEVEL_HI 36 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 191 IRQ_TYPE_LEVEL_HI 37 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
95 <GIC_SPI 191 IRQ_TYPE_LEVEL_HI 38 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 193 IRQ_TYPE_LEVEL_HI 39 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* sai2 */
97 <GIC_SPI 199 IRQ_TYPE_LEVEL_HI 40 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, /* sai3 */
98 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 41 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 42 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 0 IRQ_TYPE_LEVEL_HI 43 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 268 IRQ_TYPE_LEVEL_HI 44 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* gpt0 */
102 <GIC_SPI 269 IRQ_TYPE_LEVEL_HI 45 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, /* gpt1 */
103 <GIC_SPI 270 IRQ_TYPE_LEVEL_HI 46 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, /* gpt2 */
104 <GIC_SPI 271 IRQ_TYPE_LEVEL_HI 47 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>; /* gpt3 */
105 power-domains = <&pd IMX_SC_R_DMA_0_CH 48 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
106 <&pd IMX_SC_R_DMA_0_CH 49 <&pd IMX_SC_R_DMA_0_CH1>,
107 <&pd IMX_SC_R_DMA_0_CH 50 <&pd IMX_SC_R_DMA_0_CH2>,
108 <&pd IMX_SC_R_DMA_0_CH 51 <&pd IMX_SC_R_DMA_0_CH3>,
109 <&pd IMX_SC_R_DMA_0_CH 52 <&pd IMX_SC_R_DMA_0_CH4>,
110 <&pd IMX_SC_R_DMA_0_CH 53 <&pd IMX_SC_R_DMA_0_CH5>,
111 <&pd IMX_SC_R_DMA_0_CH 54 <&pd IMX_SC_R_DMA_0_CH6>,
112 <&pd IMX_SC_R_DMA_0_CH 55 <&pd IMX_SC_R_DMA_0_CH7>,
113 <&pd IMX_SC_R_DMA_0_CH 56 <&pd IMX_SC_R_DMA_0_CH8>,
114 <&pd IMX_SC_R_DMA_0_CH 57 <&pd IMX_SC_R_DMA_0_CH9>,
115 <&pd IMX_SC_R_DMA_0_CH 58 <&pd IMX_SC_R_DMA_0_CH10>,
116 <&pd IMX_SC_R_DMA_0_CH 59 <&pd IMX_SC_R_DMA_0_CH11>,
117 <&pd IMX_SC_R_DMA_0_CH 60 <&pd IMX_SC_R_DMA_0_CH12>,
118 <&pd IMX_SC_R_DMA_0_CH 61 <&pd IMX_SC_R_DMA_0_CH13>,
119 <&pd IMX_SC_R_DMA_0_CH 62 <&pd IMX_SC_R_DMA_0_CH14>,
120 <&pd IMX_SC_R_DMA_0_CH 63 <&pd IMX_SC_R_DMA_0_CH15>,
121 <&pd IMX_SC_R_DMA_0_CH 64 <&pd IMX_SC_R_DMA_0_CH16>,
122 <&pd IMX_SC_R_DMA_0_CH 65 <&pd IMX_SC_R_DMA_0_CH17>,
123 <&pd IMX_SC_R_DMA_0_CH 66 <&pd IMX_SC_R_DMA_0_CH18>,
124 <&pd IMX_SC_R_DMA_0_CH 67 <&pd IMX_SC_R_DMA_0_CH19>,
125 <&pd IMX_SC_R_DMA_0_CH 68 <&pd IMX_SC_R_DMA_0_CH20>,
126 <&pd IMX_SC_R_DMA_0_CH 69 <&pd IMX_SC_R_DMA_0_CH21>,
127 <&pd IMX_SC_R_DMA_0_CH 70 <&pd IMX_SC_R_DMA_0_CH22>,
128 <&pd IMX_SC_R_DMA_0_CH 71 <&pd IMX_SC_R_DMA_0_CH23>,
129 <&pd IMX_SC_R_DMA_0_CH 72 <&pd IMX_SC_R_DMA_0_CH24>;
130 }; 73 };
131 74
132 &edma2 { 75 &edma2 {
133 interrupts = <GIC_SPI 288 IRQ_TYPE_LEV 76 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 289 IRQ_TYPE_LEV 77 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 290 IRQ_TYPE_LEV 78 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 291 IRQ_TYPE_LEV 79 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 292 IRQ_TYPE_LEV 80 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 293 IRQ_TYPE_LEV 81 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 294 IRQ_TYPE_LEV 82 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 295 IRQ_TYPE_LEV 83 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 308 IRQ_TYPE_LEV 84 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 309 IRQ_TYPE_LEV 85 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 310 IRQ_TYPE_LEV 86 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 311 IRQ_TYPE_LEV 87 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 312 IRQ_TYPE_LEV 88 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 313 IRQ_TYPE_LEV 89 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 314 IRQ_TYPE_LEV 90 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 315 IRQ_TYPE_LEV 91 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
149 }; 92 };
150 93
151 &edma3 { 94 &edma3 {
152 interrupts = <GIC_SPI 296 IRQ_TYPE_LEV 95 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 297 IRQ_TYPE_LEV 96 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 298 IRQ_TYPE_LEV 97 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 299 IRQ_TYPE_LEV 98 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 300 IRQ_TYPE_LEV 99 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 301 IRQ_TYPE_LEV 100 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
158 <GIC_SPI 302 IRQ_TYPE_LEV 101 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
159 <GIC_SPI 303 IRQ_TYPE_LEV 102 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
160 }; 103 };
161 104
162 &flexcan1 { 105 &flexcan1 {
163 interrupts = <GIC_SPI 238 IRQ_TYPE_LEV 106 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
164 }; 107 };
165 108
166 &flexcan2 { 109 &flexcan2 {
167 interrupts = <GIC_SPI 239 IRQ_TYPE_LEV 110 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
168 }; 111 };
169 112
170 &flexcan3 { 113 &flexcan3 {
171 interrupts = <GIC_SPI 240 IRQ_TYPE_LEV 114 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
172 }; 115 };
173 116
174 &i2c0 { 117 &i2c0 {
175 compatible = "fsl,imx8dxl-lpi2c", "fsl 118 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
176 interrupts = <GIC_SPI 222 IRQ_TYPE_LEV 119 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
177 dma-names = "tx","rx"; 120 dma-names = "tx","rx";
178 dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL 121 dmas = <&edma3 1 0 0>, <&edma3 0 0 FSL_EDMA_RX>;
179 }; 122 };
180 123
181 &i2c1 { 124 &i2c1 {
182 compatible = "fsl,imx8dxl-lpi2c", "fsl 125 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
183 interrupts = <GIC_SPI 223 IRQ_TYPE_LEV 126 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
184 dma-names = "tx","rx"; 127 dma-names = "tx","rx";
185 dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL 128 dmas = <&edma3 3 0 0>, <&edma3 2 0 FSL_EDMA_RX>;
186 }; 129 };
187 130
188 &i2c2 { 131 &i2c2 {
189 compatible = "fsl,imx8dxl-lpi2c", "fsl 132 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
190 interrupts = <GIC_SPI 224 IRQ_TYPE_LEV 133 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
191 dma-names = "tx","rx"; 134 dma-names = "tx","rx";
192 dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL 135 dmas = <&edma3 5 0 0>, <&edma3 4 0 FSL_EDMA_RX>;
193 }; 136 };
194 137
195 &i2c3 { 138 &i2c3 {
196 compatible = "fsl,imx8dxl-lpi2c", "fsl 139 compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c";
197 interrupts = <GIC_SPI 225 IRQ_TYPE_LEV 140 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
198 dma-names = "tx","rx"; 141 dma-names = "tx","rx";
199 dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL 142 dmas = <&edma3 7 0 0>, <&edma3 6 0 FSL_EDMA_RX>;
200 }; 143 };
201 144
202 &lpuart0 { 145 &lpuart0 {
203 compatible = "fsl,imx8dxl-lpuart", "fs 146 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEV 147 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
205 }; 148 };
206 149
207 &lpuart1 { 150 &lpuart1 {
208 compatible = "fsl,imx8dxl-lpuart", "fs 151 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
209 interrupts = <GIC_SPI 229 IRQ_TYPE_LEV 152 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
210 }; 153 };
211 154
212 &lpuart2 { 155 &lpuart2 {
213 compatible = "fsl,imx8dxl-lpuart", "fs 156 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
214 interrupts = <GIC_SPI 230 IRQ_TYPE_LEV 157 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
215 }; 158 };
216 159
217 &lpuart3 { 160 &lpuart3 {
218 compatible = "fsl,imx8dxl-lpuart", "fs 161 compatible = "fsl,imx8dxl-lpuart", "fsl,imx8qxp-lpuart";
219 interrupts = <GIC_SPI 231 IRQ_TYPE_LEV 162 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
220 }; 163 };
221 164
222 &lpspi0 { 165 &lpspi0 {
223 interrupts = <GIC_SPI 218 IRQ_TYPE_LEV 166 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
224 }; 167 };
225 168
226 &lpspi1 { 169 &lpspi1 {
227 interrupts = <GIC_SPI 219 IRQ_TYPE_LEV 170 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
228 }; 171 };
229 172
230 &lpspi2 { 173 &lpspi2 {
231 interrupts = <GIC_SPI 220 IRQ_TYPE_LEV 174 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
232 }; 175 };
233 176
234 &lpspi3 { 177 &lpspi3 {
235 interrupts = <GIC_SPI 221 IRQ_TYPE_LEV 178 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
236 }; <<
237 <<
238 &sai0 { <<
239 interrupts = <GIC_SPI 188 IRQ_TYPE_LEV <<
240 }; <<
241 <<
242 &sai1 { <<
243 interrupts = <GIC_SPI 190 IRQ_TYPE_LEV <<
244 }; <<
245 <<
246 &sai2 { <<
247 interrupts = <GIC_SPI 192 IRQ_TYPE_LEV <<
248 }; <<
249 <<
250 &sai3 { <<
251 interrupts = <GIC_SPI 198 IRQ_TYPE_LEV <<
252 }; <<
253 <<
254 &spdif0 { <<
255 interrupts = <GIC_SPI 326 IRQ_TYPE_LEV <<
256 <GIC_SPI 328 IRQ_TYPE_LEV <<
257 }; 179 };
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